Add support for 100M on RTL8221B ports

Merge pull request #209 from hlyi/pr
Add Steamemo IG204 V1 support
2026-08-30 14:52:51 +08:00 · 2026-06-15 18:40:03 +02:00 · 2026-06-12 17:35:17 +02:00 · 2026-06-10 08:40:35 +02:00 · 2026-06-10 08:21:48 +02:00 · 2026-06-10 05:45:19 +02:00
180 changed files with 16770 additions and 2208 deletions
@@ -0,0 +1,23 @@
+name: Build firmware
+
+on:
+  push:
+    branches: ['**']
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    container:
+      image: debian:trixie
+
+    steps:
+      - uses: actions/checkout@v6
+
+      - name: Install dependencies
+        run: |
+          apt update
+          apt install make gcc sdcc xxd python-is-python3 libjson-c-dev -y
+      - name: Check if machine.c can be compiled for all machines
+        run: make machine_check
+      - name: Make project
+        run: make MACHINE="KP_9000_6XHML_X2"
@@ -0,0 +1,9 @@
+.gitignore
+.idea/
+output/
+html_data.c
+html_data.h
+version.h
+tools/httpd_sim
+tools/injector
+tools/fileadder
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2025 The RTLPlayground Contributors
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
@@ -1,21 +1,59 @@
-BOOTLOADER_ADDRESS=0x100
+VERSION=0.1.0
+IMAGESIZE = 524288
+DEFAULT_CONFIG_LOCATION = 454656
+CONFIG_LOCATION = 458752
+HTML_LOCATION = 262144

 CC = sdcc
-CC_FLAGS = -mmcs51 -Ihttpd -Iuip
+CC_FLAGS = -mmcs51 -I. -Ihttpd -Iuip
 ASM = sdas8051
 AFLAGS= -plosgff

-SUBDIRS := tools uip httpd
+SUBDIRS := tools
 SUBDIRSCLEAN=$(addsuffix clean,$(SUBDIRS))

-all: $(SUBDIRS) rtlplayground.bin
+ifeq ($(MACHINE),)
+	MACHINE:= $(shell grep "^\s*#define MACHINE_" machine.h | sed "s/^\s*#define MACHINE_//")
+else
+	CC_FLAGS += -DMACHINE_$(MACHINE)
+endif

-SRCS = rtlplayground.c rtl837x_flash.c rtl837x_phy.c rtl837x_port.c cmd_parser.c html_data.c
-OBJS = ${SRCS:.c=.rel}
-OBJS += uip/timer.rel uip/uip-fw.rel uip/uip-neighbor.rel uip/uip-split.rel uip/uip.rel uip/uip_arp.rel uip/uiplib.rel httpd/httpd.rel httpd/page_impl.rel
+BUILDDIR = output/$(MACHINE)
+VERSION_HEADER := version.h

-html_data.c html_data.h: html tools
-	tools/fileadder -a -s -b BANK1 -d html -p html_data
+GIT_VERSION := $(shell git rev-parse --short HEAD)
+ifeq ($(shell git status --porcelain --untracked-files=no),)
+else
+	GIT_VERSION := $(GIT_VERSION)-dirty
+endif
+
+VERSION_EXTENSION = v$(VERSION)-$(GIT_VERSION)
+FILENAME_EXTENSION = $(VERSION_EXTENSION)-$(MACHINE)
+
+all: create_build_dir $(VERSION_HEADER) $(SUBDIRS) $(BUILDDIR)/rtlplayground-$(FILENAME_EXTENSION).bin
+
+create_build_dir:
+	mkdir -p $(BUILDDIR)
+	mkdir -p $(BUILDDIR)/uip
+	mkdir -p $(BUILDDIR)/httpd
+
+SRCS = rtlplayground.c rtl837x_flash.c rtl837x_leds.c rtl837x_phy.c rtl837x_port.c cmd_parser.c html_data.c rtl837x_igmp.c
+SRCS += rtl837x_stp.c rtl837x_pins.c dhcp.c machine.c cmd_editor.c rtl837x_bandwidth.c rtl837x_init.c syslog.c
+SRCS += uip/timer.c uip/uip.c uip/uip_arp.c uip/uiplib.c uip/uip-fw.c uip/uip-neighbor.c uip/uip-split.c udp_apps.c
+SRCS += httpd/httpd.c httpd/page_impl.c
+OBJS = ${SRCS:%.c=$(BUILDDIR)/%.rel}
+DEPS := ${SRCS:%.c=$(BUILDDIR)/%.d}
+HTML := $(shell find $(html) -name '*.js' -or -name '*.html' -or -name '*.svg')
+
+html_data.c html_data.h: $(HTML) tools/output/fileadder
+	tools/output/fileadder -a $(HTML_LOCATION) -s $(IMAGESIZE) -b BANK1 -d html -p html_data
+
+$(VERSION_HEADER):
+	@echo "#ifndef VERSION_H" > $(VERSION_HEADER)
+	@echo "#define VERSION_H" >> $(VERSION_HEADER)
+	@echo "#define VERSION_SW \"$(VERSION_EXTENSION)\"" >> $(VERSION_HEADER)
+	@echo "#define BUILD_DATE \"$(shell date +"%Y-%m-%d %H:%M:%S")\"" >> $(VERSION_HEADER)
+	@echo "#endif" >> $(VERSION_HEADER)

 httpd: html_data.h

@@ -23,35 +61,46 @@ $(SUBDIRS):
 	$(MAKE) -C $@

 clean:
-	-make -C uip clean
-	-make -C httpd clean
-	-rm html_data.c html_data.c
-	if [ -e rtlplayground.bin ]; then rm rtlplayground.bin; fi
-	if [ -e rtlplayground.asm ]; then rm rtlplayground.asm; fi
-	-rm *.ihx *.lk *.lst *.map *.mem *.rel *.rst *.sym *.bin
+	-rm -f html_data.c html_data.h $(VERSION_HEADER)
+	-if [ -d $(BUILDDIR) ]; then find $(BUILDDIR) -type f ! -name "*.bin" -delete; fi

+distclean:
+	-rm -f html_data.c html_data.h $(VERSION_HEADER)
+	-rm -rf $(BUILDDIR)

-%.rel: %.c
-	$(CC) $(CC_FLAGS) -c $<
+$(BUILDDIR)/%.rel: %.c
+	$(CC) -MMD $(CC_FLAGS) -o $@ -c $<

-%.rel: %.asm
-	${ASM} ${AFLAGS} $^
+$(BUILDDIR)/%.rel: %.asm
+	${ASM} ${AFLAGS} -o $@ $<
 #	mv -f $(addprefix $(basename $^), .lst .rel .sym) .

-rtlplayground.ihx:  crtstart.rel $(OBJS) 
-	$(CC) $(CC_FLAGS) -Wl-bHOME=${BOOTLOADER_ADDRESS}  -Wl-bBANK1=0x14000 -Wl-r -o $@ $^
+$(BUILDDIR)/rtlplayground.ihx: $(OBJS) $(BUILDDIR)/crtstart.rel $(BUILDDIR)/crc16.rel
+	$(CC) $(CC_FLAGS) -Wl-bHOME=0x00000 -Wl-bBANK1=0x14000 -Wl-bBANK2=0x24000 -Wl-r -o $@ $^

-%.img: %.ihx
+$(BUILDDIR)/rtlplayground.img: $(BUILDDIR)/rtlplayground.ihx
 	objcopy --input-target=ihex -O binary $< $@

-%.bin: %.img
+$(BUILDDIR)/rtlplayground-$(FILENAME_EXTENSION).bin: $(BUILDDIR)/rtlplayground.img
 	if [ -e $@ ]; then rm $@; fi
-	echo "0000000: 00 40" | xxd -r - $@
-	cat $< >> $@
-	truncate --size=16K $@
-	dd if=$< skip=80 bs=1024 >>$@
-	tools/fileadder -s -d config.txt $@
-	tools/fileadder -a -s -d html -p html_data $@
+	tools/output/imagebuilder -i $^ $@
+	tools/output/fileadder -a $(DEFAULT_CONFIG_LOCATION) -s $(IMAGESIZE) -d config.txt $@
+	tools/output/fileadder -a $(CONFIG_LOCATION) -s $(IMAGESIZE) -d config.txt $@
+	tools/output/fileadder -a $(HTML_LOCATION) -s $(IMAGESIZE) -d html -p html_data -b BANK1 $@
+	tools/output/crc_calculator -u $@
+	ln -sf $(MACHINE)/rtlplayground-$(FILENAME_EXTENSION).bin output/rtlplayground.bin

-.PHONY: clean all $(SUBDIRS)
-.PRECIOUS: %.rel %.ihx .img
+.PHONY: clean all $(SUBDIRS) $(VERSION_HEADER)
+
+.PHONY:
+machine_check:
+	@mkdir -p $(BUILDDIR)/tmp
+	@set -eo pipefail; \
+	for MACHINE in `grep -e ' MACHINE_' machine.c | sed -e 's%^.* MACHINE_%%' -e 's%[ ]*//.*$$%%' | sort -u`; \
+	do \
+	echo "Checking $${MACHINE}"; \
+	$(CC) $(CC_FLAGS) -DMACHINE_$${MACHINE} -MMD -o $(BUILDDIR)/tmp/machine_check -c machine.c; \
+	done
+	@rm -rf $(BUILDDIR)/tmp
+
+-include $(DEPS)
@@ -1,223 +1,196 @@
 # RTLPlayground
-A Playground for Firmware development for RTL8372/RTL8373 based 2.5GBit Switches.
+A Playground for Firmware development for advanced user of RTL8372/RTL8373 based 2.5GBit Switches.

 For each hardware configuration of these devices, there is usually a managed and an
 umanaged version sold, with mostly identical hardware. The aim is to provide management
 features also for unmanaged devices with additional features such as Management VLAN,
-dhcp servers, multi-language support, IPv6 and TLS-encrypted web-pages.
+dhcp servers, multi-language support, IPv6 and TLS-encrypted web-pages. At present, however
+only the following features are provided:
+- A modern web-interface with mouse-over to display further information
+- A serial console interface to configure all features
+- IGMP to configure Multicast streaming
+- Port configuration showing detailed informtion about own and Link-partner advertised
+  Speed settins and configuration of these settings on the local side
+- Per-port configuration of frame sizes (MTUs) for Jumbo-Frame support or limiting MTUs
+  for particular devices
+- EEE (Energy Efficient Ethernet) can be configured per-port. Detailed information is
+  provided for support offered by the link partner and the EEE status of a port.
+- VLAN configuration
+- SFP information is displayed on the inserted modules, the current sensor values such as
+  temperatures, RX and TX power are displayed in the CLI and as mouse-over on the web
+- Mirror configuration
+- Link Aggregation Groups can be set up
+- Detailed information on port packet statistics
+- Configuration saved to flash via the web-interface
+- Firmware updates via the web
+- Installation as a firmware upgrade from the original web-interface

-The playground currently provides a minimal alternative firmware for both the managed and unmanaged switches.
-When used with unmanaged switches, it will provide some management features such as
-setting up VLANs, mirroring ports and provide a Web-Server (currently no functions,
-really), but will need to be configured via a serial connection. Installation on
-managed devices only makes sense for developers, as plenty of features of the managed
-switches are not supported, yet.
+<img width="1420" height="623" alt="GUI" src="doc/images/gui.png" />

-At this point, the firmware can be installed on the hardware as given below,
-all of the ports and SFP-slots will be supported. The following has been tested:
-On the keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+),
-at present the system will provide the same featurs as a dumb switch plus a tiny
-TCP stack that will allow to reply to ARP and ping messages, thus enabling pinging the device.
-VLAN and mirroring can be configured (but not saved to flash).
-The ports served by the RTL8372 will be 100M/1G/2.5G auto-detect. Port 5 to RTL8221B PHY
-SerDes configuration works and supports 1GBit and 2.5GBit Ethernet (SGMII/HISGMII).
-SFP module insert/removal identification and reading of the SFP EEProm works. SFP
-module configuration works, too, tested for 1G, 2.5G and 10G Ethernet and Fiber modules.
+While the firmware provides already considerable improvements over the original managed firmware,
+the firmware still lacks support for STP and the proprietary loop prevention
+protocols as well as DHCP. If you need these features, do not install the playground on your managed
+devices. In any case, installation is strongly discouraged unless you can at least make
+a backup of the original flash content via a SOIC clamp such as also used for BIOS
+backups and can re-install that firmware in case something is wrong. For this no soldering
+skills are necessary.

-The 4-Port Ethernet + 2 Port SFP+ devices (e.g. KP-9000-6HX-x2) are fully supported, too
-(e.g. KP-9000-6hx-x2) with the same features as above. In particular all fiber/Ethernet
-modules work in both SFP+ ports.
-
-On the 9-port devices with RTL8273 + RTL8224 (for example kp-9000-9xh-x) all ports will
-work for switching and CPU-access, the  SFP+ port will work normally and TCP connectivity
-will work as above. Not all features of the RTL8224-ports (the first 4) have been tested.
+The firmware supports all hardware featues of devices with
+- 4 2.5GBit ports + 2 SFP+ ports
+- 5 2.5GBIT + 1 SFP+ port
+- 8 2.5GBit + 1 SFP+ port
+Devices sold usually have a fairly common design, however there may be differences in the LED
+configuration (switches have LEDs with different colours and use types of LEDs). The list
+of tested devices can be found in [Supported devices](doc/supported_devices.md).

 To do meaningful development you will need to use a serial console, so soldering skills
 are required. Flashing must be done via a SOIC-8 PatchClamp or by soldering a socket
 for the flash chip.

-UPDATE: The Code comes with a port of the [uIP](https://github.com/adamdunkels/uip)
-TCP/IP stack and includes a minimal web-server that can be used to work with the switch,
-so if you use a patch-clamp for updating the firmware (~3 USD/EUR), you can try this
-out without the need to solder anything. See the instructions below.
-Note that updating the firmware of a managed switch with the images created in this
-project via the OEM web-interface will not work, because it is currently unknown how
-to generate the require checksum, see this
-[issue](https://github.com/up-n-atom/SWTG118AS/issues/4).
-However, if you use the patch-clamp to flash, this is not a problem.
-
 If you don't want to open your device, you can use the project's code to learn about the
-devices by looking at the image using e.g. Ghidra.
+devices by looking at the image using e.g. Ghidra. If you want to contribute to the
+design of the web-interface or get a feeling for the interface first, a standalone
+device simulator is provided, which runs entirely under Linux as a local webserver.

-## Compiling
-Install the following particular build requisites (Debian 12, should work on Ubuntu)
+## (0) Compiling Requirements
+
+Install the following particular build requisites (Debian 12/13), note that Ubuntu 24.04
+still has an older version of sdcc, but you will need sdcc version 4.5 for the code to compile:
 ```
-sudo apt install sdcc xxd
+sudo apt install make gcc sdcc xxd python-is-python3 libjson-c-dev
 ```

+## (1) Compiling for direct chip flashing AND upgrading an existing RTLPlayground running device
+
+Edit machine.h with an editor like vi or nano. Select the correct machine the firmware should build for.
+
+> [!TIP]
+> You can write configuration parameters in config.txt (see below) in order your switch to get
+> straight at the first boot, a correct IP configuration.
+
 Now, building the firmware image should work:
 ```
-$ make
-sdas8051 -plosgff crtstart.asm
-sdcc -mmcs51 -c rtlplayground.c
-sdcc -mmcs51 -c rtl837x_flash.c
-sdcc -mmcs51 -Wl-bHOME=0x100 -o rtlplayground.ihx crtstart.rel rtlplayground.rel rtl837x_flash.rel
-objcopy --input-target=ihex -O binary rtlplayground.ihx rtlplayground.img
-if [ -e rtlplayground.bin ]; then rm rtlplayground.bin; fi
-echo "0000000: 00 40" | xxd -r - rtlplayground.bin
-cat rtlplayground.img >> rtlplayground.bin 
+make 
 ```
-Note, that the image generated ends in .bin, not .img, in order to make
-IMSProg happy.
+Note, that the image generated ends in .bin, not .img, in order to make IMSProg happy.

-## Installation
-You can play with the image using ghidra or flash real Switch Hardware
-
-### Supported Hardware
-If you do not have an RTL837x-based switch device such as the ones
-mentionned here: [Up-N-Atoms 2.5 GBit RTL Switch hacking guide]
-(https://github.com/up-n-atom/SWTG118AS) or one of the other that
-deployment was tested on, including:
- keepLINK kp-9000-6hx-x2 (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
- keepLINK KP-9000-6XHML-X2, same as above, but Managed
- keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+)
- keepLINK kp-9000-9xh-x-eu (1 x RTL8373 + RTL8224: 8x 2.5GBit + 1x 10GBit SFP+)
- Lianguo LG-SWTGW218AS (RTL8373 + RTL8224 PHY: 8x 2.5GBit + 1x 10GBit SFP+)
- No-Name ZX-SWTGW215AS, managed version of kp-9000-6hx-x, ordered on
-  AliExpress as keepLINK 5+1 port managed
-
-### Understanding the image using ghidra
-Start ghidra, load file starting from offset 0x0002 into
-memory starting at 0x0000. The lengthe is 0x10000. Select generic 8051, big
-endian.
-
-After loading, the boot vector is at 0x0000, which will jump to 0x0100 for
-the boot routine.
-
-The firmware uses only bank 1 of the RTL837x since it is quite short.
-Otherwise the firmware would be organized as follows
+image location is stored in `RTLPlayground/output/rtlplayground_version_machine.bin`
+for example
 ```
--------------------------- 0x0000 ---------------------------------
-Boot-Vector
-ISRs
-Common Code
-Trampoline for inter-bank calls
-Inter-bank calls, calling trampoline, one for each callable function
-
----- Bank 1 0x4000 ------   ---- Bank 2 0x4000 -----  -------- .....
-Overlay 1                    Overlay 2                 Overlay n
-
--------- 0xffff ---------   -------- 0xffff --------  -------- 0xffff
+rtlplayground-v0.1.0-12c98ba-dirty-LIANGUO_ZX_SWTGW215AS.bin
 ```
-The RTL837x firmware images are organized as follows:
-The first 2 bytes of the image give the size of the prefetched data at the
-start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which
-means that the entire shared area of the code memory in all banks,
-0x4000 bytes is read immediately into the code RAM.
-
-Common code starts at
-0x0002 in the image and has length 0x3ffd, the first bank starts at 0x4000
-in the image, is mapped to 0x4000 and has length 0xc000. The second bank
-starts at 0x10000, is mapped to 0x4000 and has length 0xc000. The third
-bank would start at 0x1c000 and would again be mapped to 0x4000.
-There are about 30 banks in use for managed switches, unmanaged ones use
-2-3, while the hardware would allow to use 0x3f banks, i.e. up to 4 MB of
-flash.
-
-The current image uses Common BANK0 and the first BANK1 via sdccs __banked
-function keyword and custom banking trampoline code for the RTL837x in
-assembler.
-
-
-### Hardware supported by the code so far
-
-The following hardware is supported:
- Clock generation, including different divider settings
- Interrupt control for timer, serial, external irqs 0, 1
- Serial console via SFRs
- Flash operations via SFRs
- Bank switching via SFRs
- Access to Switch registers via SFRs
-  - LED setup
-  - Reset
-  - Some switch settings such as MAC configuration
-  - GPIO to detect SFP module insert/removal/RX-LOS
-  - I2C to read SFP EEPROM on 1 and 2 SFP slot devices
-  - NIC setup
-  - L2 learning table access, L2 table flushing
-  - VLAN setup/configuration
-  - Port mirroring
- Access to PHYs via MDIO (clause 45 via SFR):
-  - Internal PHYs of RTL8372 and RTL8373
-  - RTL8221 (1x2.5GBit port on devices with 5 ports)
-  - RTL8224 (4x2.5GBit ports on devices with 8 ports)
- SerDes settings of SoC via SFR:
-  - Configure SFPs with 10Gbit/2.5Gbit/1Gbit (Ethernet and Fiber SFP(+) tested)
-  - RTL8221, RTL8224
- NIC TX and RX of packets via SFRs
-  - send and receive Ethernet frames via SFRs and Switch registers
-  - RTL-tags and VLAN ingress-tag decoding for CPU-port
-
-Ethernet frame RX IRQ via IRQ1 is conceptually understood, but not activated. RX is
-currently done via polling, which allows ping-times of <10ms.
-
-The RTL8372/3 have 256 bytes of internal RAM (INTMEM) accessible through MOV
-instructions, which are used for the stack and important globals. Some of
-these are bit-adressable, e.g. for storing global flags.
-
-Additionally, 64kB of extended RAM (XMEM) is built in, which is accessed
-through the MOVX instruction. It is used for global variables, for most
-of the function argument passing that is not done using the 8 registers
-R0-R7 or registers A/B, and for local variables (which requires extremely
-careful planning). The flash memory is transparently accessible for code
-being executed and can be used to store configuration. Access is done through
-the MOVC instruction, possibly setting the bank register before and
-resetting it to access the entire 4MB space. Code is prefetched from flash
-and cached in a small RAM automatically by the HW.
-
-The peripherial functions are accessed through 2 different mechanisms:
- Special Function Registers (SFRs, 0x80-0xff) for banking, timers, UART, access to
-  switch registers, MDIO, SPI (flash) and NIC transfers. Some SFRs are not
-  used for HW purposes and can be used as RAM. Some SFRs are bit-adressable,
-  allowing for very tight event wait loops (a single 2-byte instruction).
- 0x10000 switch registers, which appear to be very similar to the registers
-  of the RTL838x, for which source code and datasheets are available. This
-  controls clock dividers, GPIO/LEDs and general  switch functionality. 
-
-The playground image shows access to the different types of memory using the
-SDCC compiler. Any support of Linux or e.g. Zephyr would require porting gcc.
-There are FreeRTOS ports to 8051 processors using sdcc, however.
-
-
-### Installation on an actual switch

 > [!CAUTION]
-> NOTE THAT WHILE THIS PROCEDURE HAS BEEN SUCCESSFULLY TESTED ON ALL DEVICES ABOVE,
-> ABSOLUTELY NO GUARANTY CAN BE GIVEN THAT YOU WILL NOT DESTROY YOUR SWITCH,
-> ANY OTHER EQUIPMENT INVOLVED OR HARM YOURSELF BY OPENING THE ELECTRONIC
-> DEVICE. OPENING THE SWITCH WILL VOID ITS WARRANTY.
+> This image can be flashed directly to the chip OR through the firmware update/upgrade
+> interface of RTLPlaygound interface

-There is no support for uploading the firmware via ethernet. Instead you
-need to open the switch and flash the image directly onto the flash chip,
-which is done easiest using a SOIC-8 clip (alternatively you de-solder the
-flash chip and install a SOIC adapter):
- Disconnect power from switch
- Attach the clip onto the flash chip
- Connect USB of flash programmer, the power LED on the switch will light
-  up, check cabling if not. Don't panic, mixing up GND and 3.3V does not
-  seem to destroy the switch (at leasts the on I did this to).
- Use IMSProg (flashrom should work, too) to detect the clip
- MAKE A BACKUP OF THE EXISTING FIRMWARE!
- then load the firmware into IMSProg
- and program flash
+## (2) Compiling for OEM running device with management options (web upgrade)

-Now you can connect a serial cable to the UART port found on all the
-devices, set 8N1 @ 115200 baud and power up the switch.
+Managed switches can be updated from the existing original firmware using a SPECIFIC upgrade image.
+You first need to build the firmware for direct chip flashing : See below (1)

-The device will perform some examples and provide a minimal console, the
-documentation of which can be found in the source code rtlplayground.c`.
+Then
+
+```
+cd installer
+make 
+```
+image location is stored in  `RTLPlayground/installer/output/rtlplayground_oem_upgrade.bin`
+
+> [!CAUTION]
+> This image must ONLY be used for original OEM firmware web interface firmware upgrade.
+> You do not need this image if you are already on RTLplayground firmware.
+> Unless you go back to the original OEM firmware, you would only flash this specific firmware
+> only once. Future upgrades of RTLPlayground will only need to follow (1)
+
+example of compilation console output
+
+```
+RTLPlayground/installer$ make
+mkdir -p output
+gcc updatebuilder.c -o output/updatebuilder
+sdas8051 -plosgff -o output/crtstart.rel crtstart.asm
+sdcc -mmcs51 --code-loc 0x1000 -o output/installer.rel -c installer.c
+sdcc -mmcs51 -Wl-bHOME=0x1100 -Wl-r -o output/rtlinstaller.ihx output/crtstart.rel output/installer.rel
+./output/updatebuilder -i output/rtlinstaller.ihx -o output/rtlplayground_oem_upgrade.bin ../output/rtlplayground.bin
+Input file size: 524288
+Bytes read: 524288
+EOF
+Payload sum 1 is: 0x25100
+Payload sum 2 is: 0x25100
+Payload sum with header is: 0x264ec
+Payload sum is: 0xf8fe94
+Header checksum is: 0x5a1
+```
+
+## (3) Sandbox Usage with Ghidra (optional)
+
+You can play with the image using ghidra or flash real Switch Hardware. For
+ghidra see this information about [Ghidra images](ghidra.md).
+
+## (4) Installation through the Web interface (software way)
+
+Managed switches (OEM firmware of RTLplaygroud firmware) can be upgraded via the web interface.
+Unmanaged switch cannot be flashed this way (see 5).
+
+Go to "Firmware update" tab, select the correct file.
+
+> [!IMPORTANT]
+> If your device already runs RTLPlayground, you must upload the binary file /RTLPlayground/output/rtlplayground_Version_Machine.bin
+> If your device is OEM, you must upload the binary file /RTLPlayground/installer/outputrtlplayground_oem_upgrade.bin
+
+> [!CAUTION]
+> Check one more time that your device matches the machine type before flashing.
+> Be shure you have a backup of the original firmware before diving in RTLPlaygroung.
+
+Finally, push the Upload File Button and you're done !
+
+
+## (5) Flashing the ROM directly (hardware way, but also only way to rescue)
+
+This procedure is the only way to flash unmanaged switches, if the ROM chip is large enough.
+This is also the only way to unbrick your device if something went wroong.
+
+> [!IMPORTANT]
+> You need a SOIC-8 clip to flash the ROM chip directly onboard.
+> Alternatively you can de-solder the flash chip and install a SOIC adapter).
+> For flashing the chip directly, you must use the binary file /RTLPlayground/output/rtlplayground_Version_Machine.bin
+
+> [!CAUTION]
+> As you need to open your switch case, consider that the warranty is gone.
+
+- Disconnect power from switch.
+- Open the switch.
+- Attach the clip onto the flash chip (Red line on Pin 1, Pin 1 has a point marker).
+- Connect USB of flash programmer, the power LED on the switch will light up, check cabling if not.
+- Don't panic, mixing up GND and 3.3V usually does not destroy the switch.
+- Use IMSProg, Flashrom, or whatever Programmer to detect the chip.
+- MAKE A BACKUP (DUMP) OF THE EXISTING FIRMWARE !
+- ERASE THE ROM (BLANK) !
+- Load the firmware into IMSProg.
+- Flash is to the ROM chip.
+- Disconect the clip from the ROM chip.
+- You're done, ready for the first boot.
+
+## (6) Connecting a serial interface (optional)
+
+You can connect a serial cable to the UART port found on all the devices, set 8N1 @ 115200 baud.
+
+## (7) Power Up
+
+When you power up the switch, the device will perform some examples and provide a minimal console
+(if wired to a serial interface), the documentation of which can be found in the source code rtlplayground.c`.
+
+## (8) The web-interface
+
+The web-interface can be reached under the [default 192.168.10.247](http://192.168.10.247) unless you
+specified an IP adress in the config.txt before compilation.
+
+> [!TIP]
+> The default password is `1234`.
+
+## (9) The command line

-## The command line
 The command line is very rudimentary and mostly for testing purposes.
 The following is a boot-log with some examples:
 ```
@@ -282,7 +255,6 @@ PORT 04 1G
 <MODULE INSERTED>  Rate: 67  Encoding: 01
 Lightron Inc.   WSPXG-ES3LC-IHA 0000

-
 > stat
  CMD: stat
 Port   State   Link    TxGood          TxBad           RxGood          RxBad
@@ -300,16 +272,42 @@ Lightron Inc.   WSPXG-ES3LC-IHA 0000
  CMD: sfp
 Rate: 67  Encoding: 01
 Lightron Inc.   WSPXG-ES3LC-IHA 0000
+```
+
+## (10) Advanced configuration
+
+You can configure more deeply the switch without the need of the console mode.
+
+While in compilation part, you might write directly to config.txt file before making the binary firmware

 ```
+nano config.txt
+```
+
+If you want to modify settings after the flash is done, go to the Advanced Settings tab in System Settings
+
+<img width="1085" height="646" alt="ADVANCED SETTINGS" src="doc/images/advanced_settings.png" />
+
+```
+ip xxx.xxx.xxx.xxx      = IP adress of the switch
+gw yyy.yyy.yyy.yyy      = IP adress of the gateway
+netmask zzz.zzz.zzz.zzz = Network mask of the switch 
+port x name xxx         = Name xxx the port number x
+port z 1g               = Set 1g speed for port z
+igmp on/off             = Turn IGMP on or off
+```
+[To be continue]
+
 Enjoy playing!

-## Other documents
-The following documents give further documentation on specific features of
-the RTL837x SoCs:
+## (11) Other documents
+
+The following documents give further documentation on specific features of the RTL837x SoCs:
+- [RTL8372/3 Feature support](doc/hardware.md)
 - [CPU Port](doc/CpuPort.md)
 - [L2 learning](doc/l2.md) 
- [Mirroring](doc/mirroring.md)
+- [IGMP (IP-MC streaming)](doc/igmp.md)
 - [SFP+ ports](doc/sfp.md) 
 - [Trunking aka. port aggregation](doc/trunking.md)
 - [VLAN](doc/vlan.md)
+- [Modifications and Flash replacement](doc/mods.md)
@@ -0,0 +1,208 @@
+#include "cmd_parser.h"
+#include "machine.h"
+
+#pragma codeseg BANK2
+#pragma constseg BANK2
+
+// Position in the serial buffer
+__xdata uint8_t l;
+// Properties of currently edited command line in cmd_buffer[CMD_BUF_SIZE]
+__xdata uint8_t cursor;
+__xdata uint8_t cmd_line_len;
+__xdata uint8_t current_cmdline[CMD_BUF_SIZE];
+__xdata uint16_t history_editptr;
+
+
+extern __xdata uint8_t cmd_history[CMD_HISTORY_SIZE];
+extern __xdata uint16_t cmd_history_ptr;
+
+void cmd_editor_init(void) __banked
+{
+	l = sbuf_ptr; // We have printed out entered characters until l
+	cursor = 0;
+	cmd_line_len = 0;
+	cmd_available = 0;
+	history_editptr = 0xffff;
+}
+
+/*
+ * Allows editing the current command line held in cmd_buffer[CMD_BUF_SIZE] by
+ * identifying new characters typed or up to 4-byte escape sequences in the
+ * serial buffer ring sbuf[SBUF_SIZE].
+ * Upon detecting new characters or escape sequences, the cmd_buffer and the
+ * representation of the command line in the terminal are updated.
+ * To debug, the easist is to interpose a tty-interceptor between the physical
+ * serial device and a logical one created by interceptty:
+ * sudo interceptty -s 'ispeed 115200 ospeed 115200' /dev/ttyUSB0 /dev/tmpS
+ * picocom -b 115200 /dev/tmpS
+ */
+void cmd_edit(void) __banked
+{
+	while (l != sbuf_ptr) {
+		if (sbuf[l] >= ' ' && sbuf[l] < 127) { // A printable character, copy to command line
+			if (cmd_line_len >= CMD_BUF_SIZE)
+				continue;
+			write_char(sbuf[l]);
+			// Shift buffer to right
+			for (uint8_t i = cmd_line_len; i > cursor; i--)
+				cmd_buffer[i] = cmd_buffer[i-1];
+			// Insert char in comand buffer
+			cmd_buffer[cursor++] = sbuf[l];
+			cmd_line_len++;
+			// Print rest of line
+			for (uint8_t i = cursor; i < cmd_line_len; i++)
+				write_char(cmd_buffer[i]);
+			// Move backwards
+			for (uint8_t i = cursor; i < cmd_line_len; i++)
+				write_char('\010'); // BS works like cursor-left
+		} else if (sbuf[l] == '\033') { // ESC-Sequence
+			// Wait until we have at least 3 characters including the ESC character in the serial buffer
+			if (((sbuf_ptr + SBUF_SIZE - l) & SBUF_MASK) < 3)
+				continue;
+			if (((sbuf_ptr > l ? sbuf_ptr - l : SBUF_SIZE + sbuf_ptr - l) >= 4)
+				   && sbuf[l] == '\033' && sbuf[(l + 1) & SBUF_MASK] == '[' && sbuf[(l + 2) & SBUF_MASK] == '3' && sbuf[(l + 3) & SBUF_MASK] == '~') { // DEL
+				if (cursor < cmd_line_len) {
+					write_char('\033'); write_char('['); write_char('1'); write_char('P'); // Delete to end of line
+					cmd_line_len--;
+					for (uint8_t i = cursor; i < cmd_line_len; i++) {
+						cmd_buffer[i] = cmd_buffer[i+1];
+						write_char(cmd_buffer[i]);
+					}
+					for (uint8_t i = cursor; i < cmd_line_len; i++)
+						write_char('\010');
+				}
+				l += 4;
+				l &= SBUF_MASK;
+				continue;
+			} else if (sbuf[l] == '\033' && sbuf[(l + 1) & SBUF_MASK] == '[' && sbuf[(l + 2) & SBUF_MASK] == 'D') { // <CURSOR-LEFT>
+				if (cursor) {
+					write_char('\010'); // BS works like cursor-left
+					cursor--;
+				}
+				l += 3;
+				l &= SBUF_MASK;
+				continue;
+			} else if (sbuf[l] == '\033' && sbuf[(l + 1) & SBUF_MASK] == '[' && sbuf[(l + 2) & SBUF_MASK] == 'C') { // <CURSOR-RIGHT>
+				if (cursor < cmd_line_len) {
+					write_char('\033'); write_char('['); write_char('C');
+					cursor++;
+				}
+				l += 3;
+				l &= SBUF_MASK;
+				continue;
+			} else if (sbuf[l] == '\033' && sbuf[(l + 1) & SBUF_MASK] == '[' && sbuf[(l + 2) & SBUF_MASK] == 'A') { // <CURSOR-UP>
+				for (uint8_t i = 0; i < cmd_line_len; i++)
+					current_cmdline[i] = cmd_buffer[i];
+				current_cmdline[cmd_line_len] = 0;
+				__xdata uint16_t p;
+				if (history_editptr == 0xffff)
+					p = (cmd_history_ptr - 2) & CMD_HISTORY_MASK;
+				else
+					p = history_editptr;
+				// Move cursor to beginning of line
+				write_char('\033'); write_char('['); itoa(cursor + 2); write_char('D');
+				cursor = 0;
+				while (cmd_history[p] && cmd_history[p] != '\n') {
+					cursor++;
+					p--;
+					p &= CMD_HISTORY_MASK;
+				}
+				history_editptr = (p - 1) & CMD_HISTORY_MASK;
+				p = (p + 1) & CMD_HISTORY_MASK;
+				if (cursor) {
+					print_string("\033[2K> "); // Clear entire line: ^[[2K and print new prompt
+					for (uint8_t i = 0; i < cursor; i++) {
+						cmd_buffer[i] = cmd_history[p];
+						write_char(cmd_buffer[i]);
+						p = (p+1) & CMD_HISTORY_MASK;
+					}
+					cmd_line_len = cursor;
+				} else {
+					print_string("\033[2C"); // Move 2 right to start of editing space
+				}
+				l += 3;
+				l &= SBUF_MASK;
+				continue;
+			} else if (sbuf[l] == '\033' && sbuf[(l + 1) & SBUF_MASK] == '[' && sbuf[(l + 2) & SBUF_MASK] == 'B') { // <CURSOR-DOWN>
+				if (history_editptr != 0xffff) {
+					__xdata uint16_t p = (history_editptr + 2) & CMD_HISTORY_MASK;
+					// Move cursor to beginning of line
+					write_char('\033'); write_char('['); itoa(cursor + 2); write_char('D');
+					print_string("\033[2K> "); // Clear entire line: ^[[2K and print new prompt
+					uint8_t i = 0;
+					while (cmd_history[p] && cmd_history[p] != '\n') {
+						p = (p + 1) & CMD_HISTORY_MASK;
+					}
+					p = (p + 1) & CMD_HISTORY_MASK;
+					while (cmd_history[p] && cmd_history[p] != '\n') {
+						cmd_buffer[i] = cmd_history[p];
+						write_char(cmd_buffer[i++]);
+						p = (p + 1) & CMD_HISTORY_MASK;
+					}
+					history_editptr = (p - 1) & CMD_HISTORY_MASK;
+					if (!i) {
+						if (current_cmdline[i]) {
+							while (current_cmdline[i]) {
+								cmd_buffer[i] = current_cmdline[i];
+								write_char(cmd_buffer[i++]);
+							}
+						} else {
+							write_char('\033'); write_char('['); write_char('C');
+						}
+						history_editptr = 0xffff;
+						// Move cursor right
+					}
+					cmd_line_len = i;
+					cursor = 0;
+					// Move cursor again to beginning of line
+					write_char('\033'); write_char('['); itoa(i); write_char('D');
+				} else {
+					// If we are at the last entry of the history, just move the cursor to the end of the line
+					if (cursor < cmd_line_len) {
+						write_char('\033'); write_char('['); itoa(cmd_line_len - cursor); write_char('C');
+					}
+					cursor = cmd_line_len;
+				}
+				l += 3;
+				l &= SBUF_MASK;
+				continue;
+			} else { // An unknown or not yet complete Escape sequence: wait
+				continue;
+			}
+		} else if (sbuf[l] == 127 || sbuf[l] == 8) {  // Backspace DEL or BS/^H
+			if (cursor > 0) {
+				write_char('\010');
+				for (uint8_t i = cursor; i < cmd_line_len; i++)
+					write_char(cmd_buffer[i]);
+				write_char(' '); // Overwrite end of line
+				// Move backwards n steps:
+				for (uint8_t i = cursor; i <= cmd_line_len; i++)
+					write_char('\010');
+				cursor--;
+				for (uint8_t i = cursor; i <= cmd_line_len; i++)
+					cmd_buffer[i] = cmd_buffer[i+1];
+				cmd_line_len--;
+			}
+		}
+		// If the command buffer is currently in use, we cannot copy to it
+		if (cmd_available)
+			break;
+		// Check whether return was pressed:
+		if (sbuf[l] == '\n' || sbuf[l] == '\r') {
+			write_char('\n');
+			cmd_buffer[cmd_line_len] = '\0';
+//			write_char('>'); print_string_x(cmd_buffer); write_char('<');
+			// If there is a command we print the prompt after execution
+			// otherwise immediately because there is nothing to execute
+			if (cmd_line_len)
+				cmd_available = 1;
+			else
+				print_cmd_prompt();
+			cursor = 0;
+			cmd_line_len = 0;
+			history_editptr = 0xffff;
+		}
+		l++;
+		l &= SBUF_MASK;
+	}
+}
@@ -0,0 +1,9 @@
+#ifndef _CMD_EDITOR_H_
+#define _CMD_EDITOR_H_
+
+#include <stdint.h>
+
+void cmd_editor_init(void) __banked;
+void cmd_edit(void) __banked;
+
+#endif
@@ -1,7 +1,19 @@
 #ifndef _CMD_PARSER_H_
 #define _CMD_PARSER_H_

+#include <stdint.h>
+
+#include "rtl837x_common.h"
+
+extern __xdata uint8_t cmd_buffer[CMD_BUF_SIZE];
+extern __xdata uint8_t cmd_available;
+extern __xdata uint8_t err_status;
+
+void cmd_tokenize(void) __banked;
 void cmd_parser(void) __banked;
-void cmd_parser_setup(void) __banked;
-void execute_config() __banked;
+void execute_config(void) __banked;
+void execute_commands(__xdata uint8_t *p) __banked;
+void print_sw_version(void) __banked;
+void clear_command_history(void) __banked;
+
 #endif
@@ -0,0 +1,3 @@
+ip 192.168.10.247
+gw 192.168.10.1
+netmask 255.255.255.0
@@ -0,0 +1,121 @@
+;
+; CRC16 calculation module
+;
+	.globl 	_crc_value
+	.globl 	_crc16
+	.equ	BANK, 0x96
+;	.equ	DPS, 0x86
+; Variable in XMEM holding current CRC16 value, being updated
+	.area XSEG    (XDATA)
+_crc_value::
+	.ds 2
+
+;-------------------------------------------------------
+; CRC16 subroutine
+; - dptr points to byte to be CRCd in xmem
+; - algorithm uses table lookup
+;-------------------------------------------------------
+	.area HOME    (CODE)
+	.area CSEG    (CODE)
+;	.area BANK1   (CODE)
+_crc16:
+	mov	BANK, #1
+	push	dph
+	push	dpl
+	movx	a, @dptr
+;	inc	DPS
+	mov	b, a
+	mov	dptr, #_crc_value
+	movx	a, @dptr
+
+	xrl	a, b 			; create index into tables
+	push	a 			; save index
+	mov	dptr, #crc16_table_l 	; low part of table address
+	movc	a, @a+dptr		; get low byte
+	mov	b, a
+
+	mov	dptr, #_crc_value + 1
+	movx	a, @dptr
+
+	xrl	a, b
+	mov	dptr, #_crc_value
+	movx	@dptr, a		; save result low part
+	mov	dptr, #crc16_table_h	; high part of table address
+	pop	a			; restore index
+	movc	a, @a+dptr
+	mov	dptr, #_crc_value+1
+	movx	@dptr, a		; save result high part
+	pop	dpl
+	pop	dph
+;	clr	DPS
+	ret
+
+	.area BANK1   (CODE)
+
+crc16_table_l:
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x00, #0xc1, #0x81, #0x40, #0x01, #0xc0, #0x80, #0x41
+	.byte #0x01, #0xc0, #0x80, #0x41, #0x00, #0xc1, #0x81, #0x40
+
+crc16_table_h:
+	.byte #0x00, #0xc0, #0xc1, #0x01, #0xc3, #0x03, #0x02, #0xc2
+	.byte #0xc6, #0x06, #0x07, #0xc7, #0x05, #0xc5, #0xc4, #0x04
+	.byte #0xcc, #0x0c, #0x0d, #0xcd, #0x0f, #0xcf, #0xce, #0x0e
+	.byte #0x0a, #0xca, #0xcb, #0x0b, #0xc9, #0x09, #0x08, #0xc8
+	.byte #0xd8, #0x18, #0x19, #0xd9, #0x1b, #0xdb, #0xda, #0x1a
+	.byte #0x1e, #0xde, #0xdf, #0x1f, #0xdd, #0x1d, #0x1c, #0xdc
+	.byte #0x14, #0xd4, #0xd5, #0x15, #0xd7, #0x17, #0x16, #0xd6
+	.byte #0xd2, #0x12, #0x13, #0xd3, #0x11, #0xd1, #0xd0, #0x10
+	.byte #0xf0, #0x30, #0x31, #0xf1, #0x33, #0xf3, #0xf2, #0x32
+	.byte #0x36, #0xf6, #0xf7, #0x37, #0xf5, #0x35, #0x34, #0xf4
+	.byte #0x3c, #0xfc, #0xfd, #0x3d, #0xff, #0x3f, #0x3e, #0xfe
+	.byte #0xfa, #0x3a, #0x3b, #0xfb, #0x39, #0xf9, #0xf8, #0x38
+	.byte #0x28, #0xe8, #0xe9, #0x29, #0xeb, #0x2b, #0x2a, #0xea
+	.byte #0xee, #0x2e, #0x2f, #0xef, #0x2d, #0xed, #0xec, #0x2c
+	.byte #0xe4, #0x24, #0x25, #0xe5, #0x27, #0xe7, #0xe6, #0x26
+	.byte #0x22, #0xe2, #0xe3, #0x23, #0xe1, #0x21, #0x20, #0xe0
+	.byte #0xa0, #0x60, #0x61, #0xa1, #0x63, #0xa3, #0xa2, #0x62
+	.byte #0x66, #0xa6, #0xa7, #0x67, #0xa5, #0x65, #0x64, #0xa4
+	.byte #0x6c, #0xac, #0xad, #0x6d, #0xaf, #0x6f, #0x6e, #0xae
+	.byte #0xaa, #0x6a, #0x6b, #0xab, #0x69, #0xa9, #0xa8, #0x68
+	.byte #0x78, #0xb8, #0xb9, #0x79, #0xbb, #0x7b, #0x7a, #0xba
+	.byte #0xbe, #0x7e, #0x7f, #0xbf, #0x7d, #0xbd, #0xbc, #0x7c
+	.byte #0xb4, #0x74, #0x75, #0xb5, #0x77, #0xb7, #0xb6, #0x76
+	.byte #0x72, #0xb2, #0xb3, #0x73, #0xb1, #0x71, #0x70, #0xb0
+	.byte #0x50, #0x90, #0x91, #0x51, #0x93, #0x53, #0x52, #0x92
+	.byte #0x96, #0x56, #0x57, #0x97, #0x55, #0x95, #0x94, #0x54
+	.byte #0x9c, #0x5c, #0x5d, #0x9d, #0x5f, #0x9f, #0x9e, #0x5e
+	.byte #0x5a, #0x9a, #0x9b, #0x5b, #0x99, #0x59, #0x58, #0x98
+	.byte #0x88, #0x48, #0x49, #0x89, #0x4b, #0x8b, #0x8a, #0x4a
+	.byte #0x4e, #0x8e, #0x8f, #0x4f, #0x8d, #0x4d, #0x4c, #0x8c
+	.byte #0x44, #0x84, #0x85, #0x45, #0x87, #0x47, #0x46, #0x86
+	.byte #0x82, #0x42, #0x43, #0x83, #0x41, #0x81, #0x80, #0x40
@@ -1,44 +1,4 @@
-	.globl __start__stack
-;--------------------------------------------------------
-; Stack segment in internal ram
-;--------------------------------------------------------
-	.area	SSEG	(DATA)
-__start__stack:
-	.ds	1
-
- 	.area VECTOR    (CODE)
-	.globl __interrupt_vect
-__interrupt_vect:
- 	ljmp	__sdcc_gsinit_startup
- 	ljmp	_isr_ext0	; 0x03
-	.ds     5
-	ljmp	_isr_timer0	; 0x0b
-	.ds     5
-	ljmp	_isr_ext1	; 0x13
-	.ds     5
-	reti
-	.ds     7
- 	ljmp    _isr_serial	; 0x23
-	.ds     5
-	reti			; 0x2b TIMER 2 IRQ
-	.ds     7
-	reti			; 0x33 NOT used by DW8051
-	.ds     7
-	reti			; 0x3b Serial port 1 RX/TX IRQ
-	.ds     7
- 	ljmp    _isr_ext2	; 0x43
-	.ds     5
- 	ljmp    _isr_ext3	; 0x4b
-
-	.globl __start__stack
-
-	.area GSINIT0 (CODE)
-
-__sdcc_gsinit_startup::
-        mov     sp,#__start__stack - 1
-
 	.area GSFINAL (CODE)
-        ljmp	_bootloader

 __sdcc_banked_call::
 	push	_PSBANK
@@ -0,0 +1,18 @@
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+#ifdef DEBUG
+#define dbg_string(s) print_string(s)
+#define dbg_string_x(s) print_string_x(s)
+#define dbg_byte(s) print_byte(s)
+#define dbg_short(s) print_short(s)
+#define dbg_char(s) write_char(s)
+#else
+#define dbg_string(s)
+#define dbg_string_x(s)
+#define dbg_byte(s)
+#define dbg_short(s)
+#define dbg_char(s)
+#endif
+
+#endif
@@ -0,0 +1,387 @@
+/*
+ * This is a DHCP client implementation for the RTL837x-based switches
+ */
+
+// #define REGDBG
+// #define DEBUG
+
+#include <stdint.h>
+#include "rtl837x_sfr.h"
+#include "rtl837x_common.h"
+#include "dhcp.h"
+#include "uip.h"
+#include "uip/uip.h"
+
+__xdata struct dhcp_state dhcp_state;
+__xdata uip_ipaddr_t server;
+
+#define DHCP_HW_TYPE_ETH	1
+
+#define DHCP_SUBNET_MASK 	1
+#define DHCP_SUBNET_MASK_LEN 	4
+#define DHCP_ROUTER	 	3
+#define DHCP_ROUTER_LEN 	4
+#define DHCP_DNS	 	6
+#define DHCP_DNS_LEN	 	4
+#define DHCP_BROADCAST 		28
+#define DHCP_BROADCAST_LEN	4
+#define DHCP_SERVER_ID		54
+#define DHCP_SERVER_ID_LEN	4
+#define DHCP_MESSAGE_TYPE 	53
+#define DHCP_MESSAGE_TYPE_LEN	1
+#define DHCP_MESSAGE_DISCOVER	1
+#define DHCP_MESSAGE_OFFER	2
+#define DHCP_MESSAGE_REQUEST	3
+#define DHCP_MESSAGE_ACK	5
+#define DHCP_LEASE 		51
+#define DHCP_LEASE_LEN		4
+#define DHCP_RENEWAL 		58
+#define DHCP_RENEWAL_LEN	4
+#define DHCP_REBIND 		59
+#define DHCP_REBIND_LEN		4
+#define DHCP_CLIENT_ID		61
+#define DHCP_CLIENT_ID_LEN	7
+#define DHCP_REQUEST_IP		50
+#define DHCP_REQUEST_IP_LEN	4
+#define DHCP_PARAMS		55
+#define DHCP_PARAM_SUBNET	1
+#define DHCP_PARAM_ROUTER	3
+#define DHCP_PARAM_DNS		6
+#define DHCP_END		255
+
+#pragma codeseg BANK2
+#pragma constseg BANK2
+
+struct dhcp_pkt {
+	uint8_t type;
+	uint8_t hw;
+	uint8_t hw_len;
+	uint8_t hops;
+	uint32_t tid;
+	uint16_t delay;
+	uint16_t flags;
+	uint8_t client_ip[4];
+	uint8_t your_ip[4];
+	uint8_t next_server_ip[4];
+	uint8_t relay_ip[4];
+	uint8_t client_addr[6];
+	uint8_t client_pad[10];
+	uint8_t server_name[64];
+	uint8_t file[128];
+	uint8_t cookie[4];
+};
+
+#define DHCP_P ((__xdata struct dhcp_pkt *)uip_appdata)
+#define DHCP_OPT ((__xdata uint8_t *)(uip_appdata) + sizeof (struct dhcp_pkt))
+
+__xdata uint32_t long_value;
+
+
+void dhcp_print_ip(__xdata uint8_t *a)
+{
+	itoa(a[0]); write_char('.');
+	itoa(a[1]); write_char('.');
+	itoa(a[2]); write_char('.');
+	itoa(a[3]);
+}
+
+
+void dhcp_prepare_request(void)
+{
+	DHCP_P->type = 1;
+	DHCP_P->hw = DHCP_HW_TYPE_ETH;
+	DHCP_P->hw_len = 6;
+	DHCP_P->hops = 0;
+
+	DHCP_P->tid = HTONS(dhcp_state.transaction_id);
+	DHCP_P->delay = HTONS(0);
+	DHCP_P->flags = 0;
+	// Clear fields client_ip to bootp_file
+	memset(DHCP_P->client_ip, 0, 224);
+	memcpy(DHCP_P->client_addr, uip_ethaddr.addr, 6);
+	DHCP_P->cookie[0] = 0x63;
+	DHCP_P->cookie[1] = 0x82;
+	DHCP_P->cookie[2] = 0x53;
+	DHCP_P->cookie[3] = 0x63;
+}
+
+
+void dhcp_addopt_client_id(void)
+{
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_CLIENT_ID;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_CLIENT_ID_LEN;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_HW_TYPE_ETH;
+	memcpy(&DHCP_OPT[dhcp_state.opt_ptr], uip_ethaddr.addr, 6);
+	dhcp_state.opt_ptr += 6;
+}
+
+
+void dhcp_addopt_request_ip(void)
+{
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_REQUEST_IP;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_REQUEST_IP_LEN;
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.current_ip[0];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.current_ip[1];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.current_ip[2];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.current_ip[3];
+	memcpy(&DHCP_OPT[dhcp_state.opt_ptr], uip_ethaddr.addr, 4);
+}
+
+
+void dhcp_addopt_server_id(void)
+{
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_SERVER_ID;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_SERVER_ID_LEN;
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.server[0];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.server[1];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.server[2];
+	DHCP_OPT[dhcp_state.opt_ptr++] = dhcp_state.server[3];
+	memcpy(&DHCP_OPT[dhcp_state.opt_ptr], uip_ethaddr.addr, 4);
+}
+
+
+void dhcp_send_discover(void)
+{
+	print_string("dhcp_send_discover called\n");
+	dhcp_prepare_request();
+
+	dhcp_state.opt_ptr = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_TYPE;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_TYPE_LEN;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_DISCOVER;
+
+	dhcp_addopt_client_id();
+	dhcp_addopt_request_ip();
+
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAMS;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 3;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_SUBNET;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_ROUTER;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_DNS;
+
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_END;
+	// Padding to 300 bytes
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+
+	uip_udp_send(sizeof(struct dhcp_pkt) + dhcp_state.opt_ptr);
+	dhcp_state.state = DHCP_DISCOVER_SENT;
+	dhcp_state.ticks = SYS_TICK_HZ;
+	dhcp_state.dhcp_timer = 30; // Timeout for discover
+}
+
+
+void dhcp_send_request(void)
+{
+	print_string("dhcp_send_request called\n");
+	dhcp_prepare_request();
+
+	dhcp_state.opt_ptr = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_TYPE;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_TYPE_LEN;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_MESSAGE_REQUEST;
+
+	dhcp_addopt_client_id();
+	dhcp_addopt_request_ip();
+	dhcp_addopt_server_id();
+
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAMS;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 3;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_SUBNET;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_ROUTER;
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_PARAM_DNS;
+
+	DHCP_OPT[dhcp_state.opt_ptr++] = DHCP_END;
+	// Padding to 300 bytes
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+	DHCP_OPT[dhcp_state.opt_ptr++] = 0;
+
+	uip_udp_send(sizeof(struct dhcp_pkt) + dhcp_state.opt_ptr);
+	dhcp_state.state = DHCP_REQUEST_SENT;
+	dhcp_state.ticks = SYS_TICK_HZ;
+	dhcp_state.dhcp_timer = 30; // Timeout for request
+}
+
+
+void ip_opt(__xdata uint8_t * ip)
+{
+	dhcp_state.opt_ptr++;
+	uint8_t len = DHCP_OPT[dhcp_state.opt_ptr++];
+	*ip++ = DHCP_OPT[dhcp_state.opt_ptr++];
+	*ip++ = DHCP_OPT[dhcp_state.opt_ptr++];
+	*ip++ = DHCP_OPT[dhcp_state.opt_ptr++];
+	*ip++ = DHCP_OPT[dhcp_state.opt_ptr++];
+	 // There may be more than one IP option, such as 2 DNS servers advertised
+	dhcp_state.opt_ptr += len - 4;
+}
+
+
+void long_opt(void)
+{
+	dhcp_state.opt_ptr++;
+	dhcp_state.opt_ptr++;
+	long_value =  DHCP_OPT[dhcp_state.opt_ptr++];
+	long_value <<= 8;
+	long_value |= DHCP_OPT[dhcp_state.opt_ptr++];
+	long_value <<= 8;
+	long_value |= DHCP_OPT[dhcp_state.opt_ptr++];
+	long_value <<= 8;
+	long_value |= DHCP_OPT[dhcp_state.opt_ptr++];
+}
+
+
+void parse_opts(void)
+{
+	while (DHCP_OPT[dhcp_state.opt_ptr] && DHCP_OPT[dhcp_state.opt_ptr] != DHCP_END) {
+		switch(DHCP_OPT[dhcp_state.opt_ptr]) {
+		case DHCP_SUBNET_MASK:
+			ip_opt(&dhcp_state.subnet[0]);
+			break;
+		case DHCP_ROUTER:
+			ip_opt(&dhcp_state.router[0]);
+			break;
+		case DHCP_DNS:
+			ip_opt(&dhcp_state.dns[0]);
+			break;
+		case DHCP_SERVER_ID:
+			ip_opt(&dhcp_state.server[0]);
+			break;
+		case DHCP_BROADCAST:
+			ip_opt(&dhcp_state.broadcast[0]);
+			break;
+		case DHCP_LEASE:
+			long_opt();
+			dhcp_state.lease = long_value;
+			break;
+		case DHCP_REBIND:
+			long_opt();
+			dhcp_state.rebind = long_value;
+			break;
+		case DHCP_RENEWAL:
+			long_opt();
+			dhcp_state.renewal = long_value;
+			break;
+		case DHCP_END:
+			break;
+		default:
+			print_string("Unknown DHCP option: "); print_byte(DHCP_OPT[dhcp_state.opt_ptr]); write_char('\n');
+			dhcp_state.opt_ptr++;
+			dhcp_state.opt_ptr += DHCP_OPT[dhcp_state.opt_ptr];
+			dhcp_state.opt_ptr++;
+		}
+	}
+}
+
+
+void parse_dhcp(void)
+{
+	if (!DHCP_P->tid == HTONS(dhcp_state.transaction_id))
+		return;
+	if (DHCP_P->cookie[0] != 0x63 || DHCP_P->cookie[1] != 0x82 || DHCP_P->cookie[2] != 0x53 || DHCP_P->cookie[3] != 0x63)
+		return;
+
+	dhcp_state.opt_ptr = 0;
+	if (DHCP_OPT[dhcp_state.opt_ptr++] != DHCP_MESSAGE_TYPE || DHCP_OPT[dhcp_state.opt_ptr++] != DHCP_MESSAGE_TYPE_LEN)
+		return;
+	if (DHCP_OPT[dhcp_state.opt_ptr] == DHCP_MESSAGE_OFFER) {
+		dhcp_state.opt_ptr++;
+		dhcp_state.current_ip[0] = DHCP_P->your_ip[0];
+		dhcp_state.current_ip[1] = DHCP_P->your_ip[1];
+		dhcp_state.current_ip[2] = DHCP_P->your_ip[2];
+		dhcp_state.current_ip[3] = DHCP_P->your_ip[3];
+		parse_opts();
+		print_string("DHCP offer received for IP "); dhcp_print_ip(dhcp_state.current_ip);
+		write_char('\n');
+		dhcp_send_request();
+	} else if (DHCP_OPT[dhcp_state.opt_ptr++] == DHCP_MESSAGE_ACK) {
+		parse_opts();
+		print_string("DHCP ACK, our IP is "); dhcp_print_ip(dhcp_state.current_ip);
+		write_char('\n');
+		print_string("DHCP netmask "); dhcp_print_ip(dhcp_state.subnet);
+		write_char('\n');
+		print_string("DHCP gateway "); dhcp_print_ip(dhcp_state.router);
+		write_char('\n');
+		print_string("DHCP lease-time ");
+		print_long(dhcp_state.lease);
+		write_char('\n');
+		uip_ipaddr(&uip_hostaddr, dhcp_state.current_ip[0], dhcp_state.current_ip[1], dhcp_state.current_ip[2], dhcp_state.current_ip[3]);
+		uip_ipaddr(&uip_draddr, dhcp_state.router[0], dhcp_state.router[1], dhcp_state.router[2], dhcp_state.router[3]);
+		uip_ipaddr(&uip_netmask, dhcp_state.subnet[0], dhcp_state.subnet[1], dhcp_state.subnet[2], dhcp_state.subnet[3]);
+		dhcp_state.state = DHCP_LEASING;
+		dhcp_state.ticks = SYS_TICK_HZ;
+		dhcp_state.dhcp_timer = dhcp_state.renewal > 0xffff ? 0xffff : dhcp_state.renewal;
+	}
+}
+
+
+void dhcp_start(void) __banked
+{
+	uip_ipaddr(server, 255,255,255,255);
+	dhcp_state.conn = uip_udp_new(&server, HTONS(DHCPC_SERVER_PORT));
+	dhcp_state.current_ip[0] = dhcp_state.current_ip[1] = dhcp_state.current_ip[2] = dhcp_state.current_ip[3] = 0;
+	if(dhcp_state.conn) {
+		uip_udp_bind(dhcp_state.conn, HTONS(DHCPC_CLIENT_PORT));
+	} else {
+		print_string("dhcp_start failed to set up socket\n");
+		return;
+	}
+	get_random_32();
+	dhcp_state.transaction_id = SFR_DATA_U32;
+	dhcp_state.state = DHCP_START;
+	print_string("dhcp_start done\n");
+}
+
+
+void dhcp_stop(void) __banked
+{
+	print_string("dhcp_stop called\n");
+	uip_udp_remove(dhcp_state.conn);
+	dhcp_state.state = DHCP_OFF;
+}
+
+
+void dhcp_callback(uint16_t lport) __banked
+{
+	if (lport != HTONS(DHCPC_CLIENT_PORT)) // Is this call for us? If not, ignore it
+		return;
+	if (!dhcp_state.state)
+		return;
+	if (uip_closed()) {
+		print_string("Closed\n");
+		return;
+	} else if (uip_newdata()) {
+		parse_dhcp();
+	} else {
+		if (dhcp_state.state == DHCP_START) {
+			dhcp_send_discover();
+		} else if (!--dhcp_state.ticks) {
+//			print_string("Timer: "); print_short(dhcp_state.ticks); write_char(' '); print_short(dhcp_state.dhcp_timer);
+			dhcp_state.dhcp_timer--;
+			dhcp_state.ticks = SYS_TICK_HZ;
+		}
+		if (!dhcp_state.dhcp_timer) {
+			switch (dhcp_state.state) {
+			case DHCP_DISCOVER_SENT:
+				dhcp_send_discover();
+				break;
+			case DHCP_LEASING:
+			case DHCP_REQUEST_SENT:
+				dhcp_send_request();
+				break;
+			default:
+				print_string("UNKNOWN STATE\n");
+			}
+		}
+	}
+
+	// By default we do not send anything out
+	uip_len = 0;
+}
@@ -0,0 +1,43 @@
+#ifndef _DHCP_H_
+#define _DHCP_H_
+
+#include "uipopt.h"
+#include <stdint.h>
+
+#define DHCPC_SERVER_PORT	67
+#define DHCPC_CLIENT_PORT	68
+
+#define DHCP_OFF		0
+#define DHCP_START		1
+#define DHCP_DISCOVER_SENT	2
+#define DHCP_REQUEST_SENT	3
+#define DHCP_LEASING		4
+
+void dhcp_start(void) __banked;
+void dhcp_stop(void) __banked;
+// void dhcp_periodic(void) __banked;
+void dhcp_callback(uint16_t lport) __banked;
+
+
+struct dhcp_state {
+	uint8_t state;
+	uint32_t transaction_id;
+	uint16_t dhcp_timer;
+	uint8_t ticks;
+	uint16_t opt_ptr;
+	uint8_t current_ip[4];
+	uint8_t server[4];
+	uint8_t router[4];
+	uint8_t subnet[4];
+	uint8_t dns[4];
+	uint8_t broadcast[4];
+	uint32_t lease;
+	uint32_t rebind;
+	uint32_t renewal;
+
+	__xdata struct uip_udp_conn *conn;
+};
+
+typedef struct dhcp_state uip_udp_appstate_t;
+
+#endif
@@ -3,6 +3,12 @@
 The RTL827x provide a CPU Port for a NIC on the 8051 side of the SoC.

 ## Receiving packets
+In order to receive packets on the ASIC side, bit 0 of RTL837X_REG_RX_CTRL
+(0x785c) must be set. Further bits in the register enable reception of various
+kinds of Ethernet frames. They should all be set in order for the firmware
+to decide what to do with them. To drop packets with incorrect Ethernet frame CRC
+already by the ASIC, clear bit 2 of this register.
+
 Packets are received by either polling the RTL837X_REG_RX_AVAIL register
 (0x7874), which will be > 0 if data is within a ring-buffer on the ASIC side
 of the SoC. Alternatively, an interrupt can be triggered (EX1).
@@ -39,7 +45,8 @@ buffer on the ASIC side by writing 0x1 to RTL837X_REG_RX_DONE (0x784c).

 ## Transmissing packets
 Packets are transmitted by preparing a frame-header plus frame in xdata memory
-and transferring both to the ASIC side via the SFRs.
+and transferring both to the ASIC side via the SFRs. The ASIC will transmit
+packets if bit 0 of RTL837X_REG_TX_CTRL	(0x7860) is set.

 ```
 SS 07 00 00 LL LH 00 00 
@@ -0,0 +1,32 @@
+# Automation
+
+## Upload
+
+You can automate upload of the firmware via WEB with curl:
+
+1. Authorize with /login endpoint and save cookie:
+
+   ```bash
+   curl -c cookies.txt  http://${SWITCH_IP}/login -d pwd=${PASSWORD} -i
+   ```
+
+   This will save session cookie in cookies.txt
+2. Send the firmware via form:
+
+    ```bash
+    curl -b cookies.txt http://${SWITCH_IP}/upload -F "uploadedfile=@${FIRMWARE_FILE_PATH}" -i
+    ```
+
+    You can expect that server will close connection, without responding to request.
+    Wait for SWITCH_IP to be responding again.
+
+## Port status
+
+In similar way to upload, you can fetch the json status of the ports.
+
+1. Get the session cookie as for upload.
+2. Hit the `/status.json` with cookie:
+
+    ```bash
+    curl -b cookies.txt http://${SWITCH_IP}/status.json
+    ```
@@ -0,0 +1,238 @@
+# Egress and Ingress Bandwidth Control
+The RTL8372/3 allows to control the bandwidth of data transmitted (egress) and/or
+admitted (ingress) at any given port. Once admitted, packets are internally switched
+at wire-speed, since the backplane of the devices has a bandwidth of 60GBit/s.
+
+The devices schedules transmission of packets by assigning packets to 8 queues
+implemented in hardware per port, which share a total of 8Mbit of memory internal
+to the switching part of the SoCs. Packets are assigned to the respective queues
+based on the priority assigned to a packet, which can be based on various
+properties of a packet such as  IEEE 802.1P priority, DSCP value, physical port
+number, destination or source MAC, Ether-Type-based, CVID, SVID, IPv4 source or
+destination IP, IPv4/IPv6 TOS field, IPv6 Flow Label and even TCP/UDP
+source/destination port. Once in a queue, packets are scheduled for egress
+based on differnent configurable algorithms.
+
+RTLPlayground currently allows only to control the bandwidth at ingress at a port
+or just before packets leave a port. There is no control of the priority assignment
+or queue scheduling mechanisms. The bandwidth can be controlled in steps of 16Kbit/s
+from 16Kbit/s to 10Gbp/s.
+
+The bandwidth control as currently implemented allows e.g. to assign a certain
+share of bandwidth to an attached device (e.g. to share an uplink), or simulate
+connections with low bandwidth and even bad connectivity with packet drops when
+ingress is not controlled by Flow Control but by simply droping packets.
+
+## Ingress/Egress control
+The relevant registers for controlling Ingress and Egress at a port are:
+```
+#define RTL837X_IGBW_CTRL		0x4c10
+#define IGBW_INC_BYPASS_PKT		0x100
+#define IGBW_INC_IFG			0x80
+#define IGBW_ADM_DHCP			0x20
+#define IGBW_ADM_ARPREQ			0x10
+#define IGBW_ADM_RMA			0x08
+#define IGBW_ADM_BPDU			0x04
+#define IGBW_ADM_RTKPKT			0x02
+#define IGBW_ADM_IGMP			0x01
+#define RTL837X_IGBW_PORT_CTRL		0x4C18
+#define RTL837X_IGBW_PORT_FC_CTRL	0x4C8C
+#define RTL837X_EGBW_PORT_CTRL		0x1c34
+#define RTL837X_EGBW_CTRL		0x447c
+#define EGBW_INC_IFG			0x02
+#define EGBW_CPUMODE			0x01
+```
+`RTL837X_IGBW_CTRL/RTL837X_EGBW_CTRL` control the behaviour of the bandwidth control
+at ingress and egress. The flags such as `IGBW_ADM_DHCP`control whether certain types
+of packets such as DHCP are exempt from being ingress controlled. The
+`IGBW_INC_IFG/EGBW_INC_IFG` flags control whether the Inter Frame Gaps are part of
+the bandwidth being controlled. `EGBW_CPUMODE` controls whether packets generated
+by the internal CPU are subject to egress control.
+
+`RTL837X_IGBW_PORT_CTRL/RTL837X_EGBW_PORT_CTRL` configure the bandwidth for ingress
+and egress at a port.
+
+`RTL837X_IGBW_PORT_FC_CTRL` configures whether packets are bandwidth-controlled using
+Flow Control (port-bit set), or simply dropped (port-bit clear).
+
+## Ingress/Egress bandwidth API
+The code currently provides the following functions:
+```
+void bandwidth_setup(void) __banked;
+void bandwidth_ingress_set(uint8_t port, __xdata uint32_t bw) __banked;
+void bandwidth_ingress_disable(uint8_t port) __banked;
+void bandwidth_ingress_drop(uint8_t port) __banked;
+void bandwidth_egress_set(uint8_t port, __xdata uint32_t bw) __banked;
+void bandwidth_egress_disable(uint8_t port) __banked;
+void bandwidth_status(uint8_t port) __banked;
+```c
+
+`bandwidth_setup()` is called at boot-time and configures excluding all special packets
+that may be for the CPU and packets outgoing from the CPU to be excluded from bandwidth
+control. IFG is not part of the bandwidth calculation.
+
+`bandwidth_ingress_set()` enables ingress bandwidth control for a particular port given
+the specified bandwidth. This also enabled Flow Control at a port.
+
+`bandwidth_ingress_set()` enables egress bandwidth control for a particular port given
+the specified bandwidth
+
+`bandwidth_ingress_disable() / bandwidth_egress_disable()` disable ingress and egress
+bandwidth control at a given port
+
+`bandwidth_ingress_drop(port)` configures packets exceeding bandwidth limitations to
+simply be dropped
+
+`bandwidth_status(port)` shows the current bandwidth control status for a given port
+
+## Bandwidth control configuration on the Serial Console
+The following commands are provided on the serial console:
+```
+> bw [in|out|status] <port> [<hexvalue>|off|drop]
+  Configures or shows the status of bandwidth control
+```
+The bandwidth is given as the `<hexvalue>` in Kbit/s. Note that the control is only
+possible at a granularity of 16 Kbit/s and the minimum value is also 16 Kbit/s. The
+hexadecimal numbers must be given in full bytes, i.e. have an even number of digits.
+
+To enable bandwidth control of ingress for physical port 2 to be set to 256 Kbit/s
+do:
+```
+> bw in 2 0100 
+```
+
+To drop packets when the bandwidth is exceeeded at port 2 do:
+```
+> bw in 2 drop 
+```
+
+To disable bandwidth control for incoming packets on port 2 do:
+```
+> bw in 2 off
+```
+
+## Bandwidth configuration via the Web Interface
+Not implemented, yet!
+
+## A Test using iperf3
+The following is and example how to test bandwidth control with a signle Linux device using
+network namespaces to route packets between a client and a server on the same Linux device
+through an external switch.
+
+You will need 2 network intefaces on the linux device, say, 2 USB-Ethernet controllers called
+eth0 and eth1: 
+```
+$ sudo ip netns add client
+$ sudo ip netns add server
+
+$ sudo ip link set dev eth0 netns client
+$ sudo ip link set dev eth1 netns server
+
+$ sudo ip netns exec client ip link set dev eth0 up
+$ sudo ip netns exec server ip link set dev eth1 up
+
+$ sudo ip netns exec client ip addr add dev eth0 192.168.99.1/24
+$ sudo ip netns exec server ip addr add dev eth1 192.168.99.2/24
+
+$ sudo ip netns exec server iperf3 -s
+```
+This will start an iper3 server in the above shell.
+
+In a different shell you can now run the iperf3 client against your server:
+```
+$ sudo ip netns exec client iperf -c 192.168.99.2
+```
+The LEDs on your switch where your network adapters are connected should start to flicker.
+On a 1GBit connection, you should see:
+```
+$ sudo ip netns exec client iperf3 -c 192.168.99.2
+Connecting to host 192.168.99.2, port 5201
+[  5] local 192.168.99.1 port 46776 connected to 192.168.99.2 port 5201
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec   114 MBytes   952 Mbits/sec    0    339 KBytes       
+[  5]   1.00-2.00   sec   113 MBytes   946 Mbits/sec    0    356 KBytes       
+[  5]   2.00-3.00   sec   112 MBytes   937 Mbits/sec    0    390 KBytes       
+[  5]   3.00-4.00   sec   112 MBytes   942 Mbits/sec    0    390 KBytes       
+[  5]   4.00-5.00   sec   112 MBytes   943 Mbits/sec    0    390 KBytes       
+[  5]   5.00-6.00   sec   112 MBytes   944 Mbits/sec    0    390 KBytes       
+[  5]   6.00-7.00   sec   112 MBytes   938 Mbits/sec    0    390 KBytes       
+[  5]   7.00-8.00   sec   112 MBytes   942 Mbits/sec    0    410 KBytes       
+[  5]   8.00-9.00   sec   113 MBytes   947 Mbits/sec    0    410 KBytes       
+[  5]   9.00-10.00  sec   112 MBytes   940 Mbits/sec    0    410 KBytes       
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec  1.10 GBytes   943 Mbits/sec    0            sender
+[  5]   0.00-10.00  sec  1.10 GBytes   941 Mbits/sec                  receiver
+```
+
+Now, we limit ingress on port 1 (connected to eth0) to 4 MBit/s:
+```> bw in 1 1000
+bandwidth_ingress_set called, port 04
+RTL837X_IGBW_PORT_CTRL:0x00100100
+RTL837X_IGBW_PORT_FC_CTRL:0x00000010
+```
+
+We now get:
+```
+$ sudo ip netns exec client iperf3 -c 192.168.99.2
+[  5] local 192.168.99.1 port 43324 connected to 192.168.99.2 port 5201
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec  1.12 MBytes  9.43 Mbits/sec    0    160 KBytes       
+[  5]   1.00-2.00   sec   640 KBytes  5.24 Mbits/sec    0    160 KBytes       
+[  5]   2.00-3.00   sec   384 KBytes  3.15 Mbits/sec    0    160 KBytes       
+[  5]   3.00-4.00   sec   384 KBytes  3.15 Mbits/sec    0    160 KBytes       
+[  5]   4.00-5.00   sec   640 KBytes  5.24 Mbits/sec    0    160 KBytes       
+[  5]   5.00-6.00   sec   256 KBytes  2.10 Mbits/sec    0    160 KBytes       
+[  5]   6.00-7.00   sec   640 KBytes  5.24 Mbits/sec    0    160 KBytes       
+[  5]   7.00-8.00   sec   384 KBytes  3.15 Mbits/sec    0    160 KBytes       
+[  5]   8.00-9.00   sec   640 KBytes  5.24 Mbits/sec    0    160 KBytes       
+[  5]   9.00-10.00  sec   256 KBytes  2.10 Mbits/sec    0    160 KBytes       
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec  5.25 MBytes  4.40 Mbits/sec    0            sender
+[  5]   0.00-10.16  sec  4.75 MBytes  3.92 Mbits/sec                  receiver
+
+iperf Done.
+```
+Which is the 4Mbit/s we configured. There are no packet drops (retries) because
+Flow Control is used to signal the Ethernet adapter on the incoming interface
+(port 1 of the router) to slow down.
+
+We can also configure a mere 256KBit/s and packet drop to simulate a bad connection:
+```
+> bw in 1 0100
+bandwidth_ingress_set called, port 04
+RTL837X_IGBW_PORT_CTRL:0x00100010
+RTL837X_IGBW_PORT_FC_CTRL:0x00000010
+
+> bw in 1 drop
+RTL837X_IGBW_PORT_FC_CTRL:0x00000000
+```
+
+We now get:
+```
+$ sudo ip netns exec client iperf3 -c 192.168.99.2
+Connecting to host 192.168.99.2, port 5201
+[  5] local 192.168.99.1 port 46060 connected to 192.168.99.2 port 5201
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec   384 KBytes  3.14 Mbits/sec    2   1.41 KBytes       
+[  5]   1.00-2.00   sec  0.00 Bytes  0.00 bits/sec   54   1.41 KBytes       
+[  5]   2.00-3.00   sec  0.00 Bytes  0.00 bits/sec   31   29.7 KBytes       
+[  5]   3.00-4.00   sec  0.00 Bytes  0.00 bits/sec    2   1.41 KBytes       
+[  5]   4.00-5.00   sec  0.00 Bytes  0.00 bits/sec   23   1.41 KBytes       
+[  5]   5.00-6.00   sec   128 KBytes  1.05 Mbits/sec   16   14.1 KBytes       
+[  5]   6.00-7.00   sec  0.00 Bytes  0.00 bits/sec    2   1.41 KBytes       
+[  5]   7.00-8.00   sec  0.00 Bytes  0.00 bits/sec   11   1.41 KBytes       
+[  5]   8.00-9.00   sec   128 KBytes  1.05 Mbits/sec    9   8.48 KBytes       
+[  5]   9.00-10.00  sec  0.00 Bytes  0.00 bits/sec    2   1.41 KBytes       
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec   640 KBytes   524 Kbits/sec  152            sender
+[  5]   0.00-10.00  sec   256 KBytes   210 Kbits/sec                  receiver
+
+iperf Done.
+```
+Which shows a large number of retries due to dropped packets and an average number
+of received packets (the client sends the packets to the server, and they are sent
+back to the client by the server) of 210 KBit/s, the number is higher for the transmitted
+packets, because they may include dropped packets.
@@ -0,0 +1,177 @@
+### 2M-PCB23-V2.2
+
+## Brands
+| Brand    | Type            | Managed | PCB           | Flash | Chip RTL    |
+|----------|-----------------|---------|---------------|-------|-------------|
+| keepLINK | KP-9000-9XHML-X | Yes     | 2M-PCB23-V2.2 | 2M    | 8373 + 8224 |
+
+## PCB
+
+<img src="photos/2M-PCB23-V2.2-managed/2M-PCB23-V2.2-top.jpg" width="300" />
+
+## Port overview
+
+```
+┌─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
+│                                                                                                       ┌──────────┐          │
+│     ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐   │ SFP(J13) │          │
+│     │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │   │ PORT   9 │          │
+│     │  PORT 1 │ │  PORT 2 │ │  PORT 3 │ │  PORT 4 │ │  PORT 5 │ │  PORT 6 │ │  PORT 7 │ │  PORT 8 │   │ MAC    8 │ O (PWR)  │
+│  O  │  MAC  0 │ │  MAC  1 │ │  MAC  2 │ │  MAC  3 │ │  MAC  4 │ │  MAC  5 │ │  MAC  6 │ │  MAC  7 │   │ SerDes 1 │ O (SFP)  │
+│ RST └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘   └──────────┘          │
+└─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┘
+```
+
+# Connectors
+
+### J13, SFP connector
+
+| SFP Pin | Signal            | GPIO   | Notes                          |
+| ------- | ----------------- | ------ | ------------------------------ |
+| 2       | TX_FAULT          | ??     |                                |
+| 3       | TX_DISABLE        | ??     |                                |
+| 4       | MODDEF2 – SDA     | GPIO39 |                                |
+| 5       | MODDEF1 – SCL     | GPIO40 |                                |
+| 6       | MODDEF0 – PRESENT | GPIO30 | "OE Exist" reported by `fiber` |
+| 7       | RATE SEL          | ??     |                                |
+| 8       | LOS	              | GPIO37 | "OE LOS" reported by `fiber`   |
+| 9       | TO?               | ??     |                                |
+
+### T5, serial console
+
+| pin | GPIO   | Signal         |
+| --- | ------ | -------------- |
+| 1   | GPIO32 | U0RXD (Input)  |
+| 2   | GND    | Ground         |
+| 3   | GPIO31 | U0TXD (Output) |
+
+### S1, unknown connector
+
+| pin | GPIO     | Signal         |
+| --- | -------- | -------------- |
+| 1   | ???      |                |
+| x   |          |                |
+| 3   | ???      |                |
+| 4   | ???      |                |
+| 5   | ???      |                |
+
+Potentially slave interface or SMI.
+
+### U7, flash memory
+
+Flash chip is FM25Q16A.
+
+### Reset button
+
+GPIO54
+
+## Register values
+
+As probed with `regget` on stock firmware "V1.6".
+
+### Model
+
+| Name                      | Addr   | Value      |
+| ------------------------- | ------ | ---------- |
+| MODEL_NAME_INFO           | 0x0004 | 0x83730000 |
+| CHIP_MODE_INFO            | 0x0008 | 0x00008000 |
+| CHIP_INFO                 | 0x000C | 0x00300000 |
+
+### GPIO
+
+| Name                      | Addr   | Value      |
+| ------------------------- | ------ | ---------- |
+| GPIO_OUT0                 | 0x003c | 0x10000000 |
+| GPIO_OUT1                 | 0x0040 | 0x00000010 |
+| GPIO_OE0                  | 0x004c | 0x10000000 |
+| GPIO_OE1                  | 0x0050 | 0x00000010 |
+| BOND_INFO                 | 0x7f60 | 0x00000fff |
+| STRAP_INFO                | 0x7f64 | 0x0002f515 |
+| IO_DRVING_0               | 0x7f68 | 0x00000000 |
+| IO_DRVING_1               | 0x7f6c | 0x00000000 |
+| IO_DRVING_2               | 0x7f70 | 0x00000000 |
+| IO_SLEW_0                 | 0x7f74 | 0x00000000 |
+| IO_SLEW_1                 | 0x7f78 | 0x00000000 |
+| IO_SLEW_2                 | 0x7f7c | 0x00000000 |
+| IO_SMT_EN_0               | 0x7f80 | 0xffffffff |
+| IO_SMT_EN_1               | 0x7f84 | 0xffffffff |
+| IO_SMT_EN_2               | 0x7f88 | 0x0003ffff |
+| IO_MUX_SEL_0              | 0x7f8c | 0x28000000 |
+| IO_MUX_SEL_1              | 0x7f90 | 0x40000041 |
+| IO_MUX_SEL_2              | 0x7f94 | 0x00000000 |
+
+### LED
+
+| Name                      | Addr   | Value      |
+| ------------------------- | ------ | ---------- |
+| LED_GLB_CTRL              | 0x6520 | 0x0023e0f0 |
+| LED3_0_SET3_2_CTRL1       | 0x6524 | 0xff001400 |
+| LED3_0_SET1_0_CTRL1       | 0x6528 | 0x000f0000 |
+| LED3_2_SET3_CTRL0         | 0x652c | 0x007f013f |
+| LED1_0_SET3_CTRL0         | 0x6530 | 0x02000400 |
+| LED3_2_SET2_CTRL0         | 0x6534 | 0x01400141 |
+| LED1_0_SET2_CTRL0         | 0x6538 | 0x01440170 |
+| LED3_2_SET1_CTRL0         | 0x653c | 0x18000041 |
+| LED1_0_SET1_CTRL0         | 0x6540 | 0x0044017f |
+| LED3_2_SET0_CTRL0         | 0x6544 | 0x00000044 |
+| LED1_0_SET0_CTRL0         | 0x6548 | 0x00410175 |
+| LED_PORT_SET_SEL_CTRL     | 0x654c | 0x00010000 |
+| SW_LED_LOAD               | 0x6550 | 0x00000000 |
+| LED_PORT_SW_EN_CTRL[0..7] | 0x6554 | 0x00000000 |
+| LED_PORT_SW_EN_CTRL[8]    | 0x6558 | 0x00000000 |
+| LED_PORT_SW_CTRL[0]       | 0x655c | 0x00000000 |
+| LED_PORT_SW_CTRL[1]       | 0x6560 | 0x00000000 |
+| LED_PORT_SW_CTRL[2]       | 0x6564 | 0x00000000 |
+| LED_PORT_SW_CTRL[3]       | 0x6568 | 0x00000000 |
+| LED_PORT_SW_CTRL[4]       | 0x656c | 0x00000000 |
+| LED_PORT_SW_CTRL[5]       | 0x6570 | 0x00000000 |
+| LED_PORT_SW_CTRL[6]       | 0x6574 | 0x00000000 |
+| LED_PORT_SW_CTRL[7]       | 0x6578 | 0x00000000 |
+| LED_PORT_SW_CTRL[8]       | 0x657c | 0x00000000 |
+| LED_LOAD_LV1_10G          | 0x6580 | 0x000fa000 |
+| LED_LOAD_LV2_10G          | 0x6584 | 0x00271000 |
+| LED_LOAD_LV3_10G          | 0x6588 | 0x004e2000 |
+| LED_LOAD_LV1_5G           | 0x658c | 0x000fa000 |
+| LED_LOAD_LV2_5G           | 0x6590 | 0x00271000 |
+| LED_LOAD_LV3_5G           | 0x6594 | 0x004e2000 |
+| LED_LOAD_LV1_2P5G         | 0x6598 | 0x000fa000 |
+| LED_LOAD_LV2_2P5G         | 0x659c | 0x00271000 |
+| LED_LOAD_LV3_2P5G         | 0x65a0 | 0x004e2000 |
+| LED_LOAD_LV1_1G           | 0x65a4 | 0x000fa000 |
+| LED_LOAD_LV2_1G           | 0x65a8 | 0x00271000 |
+| LED_LOAD_LV3_1G           | 0x65ac | 0x004e2000 |
+| LED_LOAD_LV1_500M         | 0x65b0 | 0x0007d000 |
+| LED_LOAD_LV2_500M         | 0x65b4 | 0x00138800 |
+| LED_LOAD_LV3_500M         | 0x65b8 | 0x00271000 |
+| LED_LOAD_LV1_100M         | 0x65bc | 0x00019000 |
+| LED_LOAD_LV2_100M         | 0x65c0 | 0x0003e800 |
+| LED_LOAD_LV3_100M         | 0x65c4 | 0x0007d000 |
+| LED_LOAD_LV1_10M          | 0x65c8 | 0x00002800 |
+| LED_LOAD_LV2_10M          | 0x65cc | 0x00006400 |
+| LED_LOAD_LV3_10M          | 0x65d0 | 0x0000c800 |
+| LED_P_LOAD_CTRL           | 0x65d4 | 0x00000000 |
+| LED_GLB_ACTIVE            | 0x65d8 | 0x3ffbedff |
+| LED_GLB_IO_EN             | 0x65dc | 0x77ffffff |
+| LED_GLB_MUX_1             | 0c65e0 | 0x05102040 |
+| LED_GLB_MUX_2             | 0x65e4 | 0x0c289206 |
+| LED_GLB_MUX_3             | 0x65e8 | 0x1245038d |
+| LED_GLB_MUX_4             | 0x65ec | 0x19616554 |
+| LED_GLB_MUX_5             | 0x65f0 | 0x2079d71a |
+| LED_GLB_MUX_6             | 0x65f4 | 0x000238a1 |
+| LED_RLDP_CTRL_1           | 0x65f8 | 0x00000019 |
+| LED_RLDP_CTRL_2           | 0x65fc | 0xffffffff |
+| LED_RLDP_CTRL_3           | 0x6600 | 0x00006600 |
+| LED_DUMY_0_ADDR           | 0x6604 | 0x00000000 |
+| LED_DUMY_1_ADDR           | 0x6608 | 0x00000000 |
+
+# LEDs
+
+| Name                          | Components                  | Controlled by              |
+| ----------------------------- | --------------------------- | -------------------------- |
+| RJ45 Right Green ("LINK/ACT") |                             | RJ45 LED0                  |
+| RJ45 Left Orange ("2.5G")     |                             | RJ45 LED1                  |
+| RJ45 Left Green  ("1G")       |                             | RJ45 LED2                  |
+| "P" (PWR)                     | Top LED in "LED6" stack     | probably pulled from Vcc   |
+| SFP Link ("9")                | Bottom LED in "LED6" stack  | SFP LED0                   |
+| ??                            | D23                         | SFP LED1                   |
+| ??                            | D22                         | SFP LED2                   |
@@ -0,0 +1,161 @@
+### 2M-PCB23-V3.1
+
+## Brands
+|Brand|Type|Managed|PCB|Flash|Chip RTL|
+|---|---|---|---|---|---|
+| keepLINK | KP-9000-9XHML-X | Yes|  2M-PCB23-V3.1 | 2M| 8273N + 8224N |
+
+## PCB
+
+<img src="photos/2M-PCB23-V3.1-managed/2M-PCB23-V3.1-top.jpeg" width="300" />
+
+## Port overview
+
+```
+┌─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐
+│                                                                                                       ┌──────────┐          │
+│     ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐   │ SFP (J4) │          │
+│     │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │   │ PORT   9 │          │
+│     │  PORT 1 │ │  PORT 2 │ │  PORT 3 │ │  PORT 4 │ │  PORT 5 │ │  PORT 6 │ │  PORT 7 │ │  PORT 8 │   │ MAC    8 │ O (PWR)  │
+│  O  │  MAC  0 │ │  MAC  1 │ │  MAC  2 │ │  MAC  3 │ │  MAC  4 │ │  MAC  5 │ │  MAC  6 │ │  MAC  7 │   │ SerDes 1 │ O (SFP)  │
+│ RST └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘   └──────────┘          │
+└─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┘
+```
+
+# Connectors
+|`J4` SFP PINs | Signal | Component | GPIO | Notes |
+|---|---|---|---|---|
+|2|	TX_FAULT	        | | --- | | 
+|3|	TX_DISABLE	      | | --- | Pull down - 0R |
+|4|	MODDEF2 – SDA     |	b-r273 | GPIO39-SDA4 | |
+|5|	MODDEF1 – SCL     | b-r274 | GPIO40-SCL3 | |
+|6|	MODDEF0 – PRESENT | B-R275 | GPIO38 |  |
+|7|	RATE SEL          |	| ---    |  | 
+|8|	LOS	              | B-R276 | GPIO38 |  | 
+|9|	TO?               | | ---    |  |
+
+Note: component numbering `<L>-<REFDES>-<SIDE>`
+* L: Layer, T=Top, B=Bottom
+* REFDEES: full silkscreen like `R123`
+* SIDE: Side of the component. when the rj45 are facing towards you are you can read the silkscreen normal.
+  L = Left, R=right, B=bottom, T=top or P with a pin number.
+
+### T8, serial console
+|`T9` pin|GPIO|Signal|
+|---|---|---|
+| 1 | GPIO31 | U0TXD (Output) |
+| 2 | GND | PWR |
+| 3 | GPIO32 | U0RXD (Input) |
+| 4 | 3V3 | PWR |
+
+### T7, Slave Interface
+|`T7` pin|what|Signal|Components|
+|---|---|---|---|
+| 1 | Slave Interface | Slave SCK/SCL/MDC/EE_SCL | U7-6 |
+| 2 | GND   | | |
+| 3 | Slave Interface | Slave SDI/SDA/MDIO/EE_SDA | U7-5 |
+| 4 | 3V3   | | |
+| 5 | GPIO? | | |
+| 6 | GPIO? | | |
+
+`U7` can be a standard I2C eeprom memory, like `24LC32`.
+
+The Slave Interface allows an extenal host to controll the SOC even if the internal MCU is used.
+Depending on the `IF_SEL` bootstrap resistors, this can me `I2C`, `SPI` or `SMI`.
+On this device it is `I2C` on address `0b1011100` or `0x5c` (7-bit notation).
+
+* I2c Read:  must be a write_read opperation `<Dev-ADDR><RegAddr15:8><RegAddr7:0>` `<DevAddr><Data7:0><Data15:8><Data23:16><Data31:24>`.
+* I2c Write: `<Dev-ADDR><RegAddr15:8><RegAddr7:0><DevAddr><Data7:0><Data15:8><Data23:16><Data31:24>`.
+
+Example register `0x0004` return chip id `0x00, 0x00, 0x72, 0x83` = `0x83720000`.
+
+### T9
+|`T9` SMI | Signal | Component | GPIO | Notes |
+|---|---|---|---|---|
+|1|	MDO	| SMI-MDO | GPIO41 | | 
+|2|	GND	| PWR | | |
+|3|	MDC |	SMI-MDC | GPio40 | |
+
+### T10
+|`T10` pin|what|Signal|
+|---|---|---|
+| 1 | GPIO49 | |
+| 2 | GPIO47 | |
+| 3 | 3V3    | |
+| 4 | GPIO48 | |
+| 5 | GND    | |
+| 6 | GPIO46 | |
+
+# Reset ciruit
+
+Reset-line found at `T-D6-L`, `T-R83`, `T-R97`, `T-R94`, `T-R93` active-low.
+
+# GPIO
+
+| HEX VAL. | GPIO   | Component | What |  | GPIO | Component | What |
+| -------- | ------ |  ---- | ---- | ---- | ---- | ---- | ---- |
+| 00000001 | GPIO00 | T-R34-R, P1-LED-YL      |?      |   | GPIO32 | B-r126-r  | U0RXD |
+| 00000002 | GPIO01 | T-R99-R, P1-LED-GR      |?      |   | GPIO33 | |  |
+| 00000004 | GPIO02 |                         |?      |   | GPIO34 | B-R172, To RTL8224 | SMI-MDC0  |
+| 00000008 | GPIO03 | T-R113-R, P2-LED-GR     |?      |   | GPIO35 | B-R173, To RTL8224 | SMI-MDIO0 |
+| 00000010 | GPIO04 | T-R115-R, P3-LED-YL     |?      |   | GPIO36 | | |  |
+| 00000020 | GPIO05 | T-R117-R, P3-LED-GR     |?      |   | GPIO37 | To RTL8224 ?? | Already driver low |  |
+| 00000040 | GPIO06 |                         |?      |   | GPIO38 | sfp-6 via B-R275, sfp-8 via B-R276 | SFP-PRESENT |
+| 00000080 | GPIO07 |                         |?      |   | GPIO39 | sfp-4, b-r273, B-r143 | I2C4-SDA |
+| 00000100 | GPIO08 |                         |       |   | GPIO40 | T9-2, sfp-5 b-r274, B-r146  | I2C3-SCL |
+| 00000200 | GPIO09 |                         |LEDx[^1] | | GPIO41 | T9-1,  B-r143 | | I2C3-SDA (Unused) |
+| 00000400 | GPIO10 |                         |         | | GPIO42 | U6?8?-P6, T-R | SPI-MEMORY, CLK |
+| 00000800 | GPIO11 |                         |LEDx[^1] | | GPIO43 | U6?8?-P5, T-R | SPI-MEMORY, DI,IO0 |
+| 00001000 | GPIO12 |                         |LEDx[^1] | | GPIO44 | U6?8?-P2, T-R | SPI-MEMORY, DO,IO1 |
+| 00002000 | GPIO13 |                         |LEDx[^1] | | GPIO45 | U6?8?-P1, T-R | SPI-MEMORY, CS  |
+| 00004000 | GPIO14 |                         |LEDx[^1] | | GPIO46 | T10-6 | SPI0-SCK |
+| 00008000 | GPIO15 |                         |LEDx[^1] | | GPIO47 | T10-2 | SPI0-SDA |
+| 00010000 | GPIO16 |                         |LEDx[^1] | | GPIO48 | T10-4, J6 (BUTTON RESET) | SPI1-SCK |
+| 00020000 | GPIO17 |                         |LEDx[^1] | | GPIO49 | T10-1 | SPI1-SDA |
+| 00040000 | GPIO18 |                         |LEDx[^1] | | GPIO50 |  |  |
+| 00080000 | GPIO19 |                         |LEDx[^1] | | GPIO51 |  |  |
+| 00100000 | GPIO20 |                         |LEDx[^1] | | GPIO52 |  |  |
+| 00200000 | GPIO21 | P7-LED-GR, B-R139       |LEDx[^1] | | GPIO53 |  |  |
+| 00400000 | GPIO22 |                         |LEDx[^1] | | GPIO54 |  |  |
+| 00800000 | GPIO23 |                         |LEDx[^1] | | GPIO55 |  |  |
+| 01000000 | GPIO24 | P8-led-yellow,b-r154    |LEDx     | | GPIO56 |  |  |
+| 02000000 | GPIO25 |                         |         | | GPIO57 |  |  |
+| 04000000 | GPIO26 |                         |LEDx     | | GPIO58 |  |  |
+| 08000000 | GPIO27 |                         |?        | | GPIO59 |  |  |
+| 10000000 | GPIO28 |                         |         | | GPIO60 |  |  |
+| 20000000 | GPIO29 |                         |         | | GPIO61 |  |  |
+| 40000000 | GPIO30 | RTL8224N Reset          |RTL8224  | | GPIO62 | To RTL8224 | Already driver   |  |
+| 80000000 | GPIO31 | B-r129-r?               |U0TXD    | | GPIO63 |  |  |
+
+## GPIO Register Input value
+
+GPIO 1: 0a7ffbdd
+GPIO 0: effb6dff
+
+# LEDs
+
+| NAME | COMPONENTS | GPIO |
+| ---- | ---------- | ---- |
+| SYSTEM |  | ? | 
+| SFP |  | ? | 
+
+
+# Power supply
+
+Board has two supply rails.
+`0.95` and `3.3` volt.
+
+## `0.95` Core Voltage.
+
+Voltage is crated by a `MP2225GJ` Buck converter.
+0.95V must be within 3%.
+
+## `3.3` Voltage
+
+Voltage is crated by a `MP2225GJ` Buck converter.
+3.3V must be within 4.5%.
+Chip can deliver up to 5A and the sweetspot is at 2A.
+So higher power SFP-modules should work.
+
+
+[^1]: LEDs are found by just plugin a RJ45 connector and see with cmd `gpio` the status change. But the bit pattern for port 1,2 are diffrent from port 3,4.
@@ -0,0 +1,93 @@
+# FOXNEO FNS-1200P
+
+RTL8372-based 4×2.5G PoE+ + 2×SFP+ unmanaged switch.
+
+Using SPI clamp in-board is the only method for initial installation.
+
+### Label specifications
+
+- **Manufacturer**: FOXNEO
+- **Model**: FNS-1200P
+- **Ports**:
+  - 4 × RJ45: 10/100/1000/2500 Mbps with PoE+
+  - 2 × SFP+: 1G / 2.5G / 10G
+
+### What works
+
+- All four 2.5GBASE-T RJ45 ports at 10/100/1000/2500 Mbps (PoE+ is not configurable via RTLPlayground)
+- Both SFP+ ports supporting 1G, 2.5G and 10G modules
+- LEDs: amber (2.5G) and green (1G/100M/10M) per copper port; combined link/act on SFP ports
+
+### PCB overview
+
+**Board markings**
+- Top silkscreen: PCB-K0402W-U13-V2.0 / DIP-K0402WB-V2.0
+
+**Key components**
+- U3: SPI NOR flash, 2 MiB
+- U7: unpopulated SOP8 footprint — I2C bus (RTL8372 slave at 0x5c) is accessible from its pads, useful for register dumps
+- S1: unpopulated slide switch footprint (three through-holes used as serial console)
+
+Front panel
+
+<img src="photos/FNS-1200P/chassis-front.jpg" width="400" />
+
+Top side (PCB)
+
+<img src="photos/FNS-1200P/PCB-top.jpg" width="300" />
+
+### Port layout
+
+| Front panel position | Logical port | Physical port | Type    |
+|----------------------|--------------|---------------|---------|
+| SFP left             | 8            | 5             | SFP+    |
+| RJ45 1               | 4            | 1             | Copper  |
+| RJ45 2               | 5            | 2             | Copper  |
+| RJ45 3               | 6            | 3             | Copper  |
+| RJ45 4               | 7            | 4             | Copper  |
+| SFP right            | 3            | 6             | SFP+    |
+
+### Serial console
+
+The PCB has three unpopulated through-holes intended for a slide switch, directly connected to UART0.
+Numbered from the left (SFP port side), the pinout is:
+
+| Position (left→right) | Signal | GPIO                     |
+|-----------------------|--------|--------------------------|
+| 1 (leftmost)          | RX     | GPIO32\_UART0\_RX (32)   |
+| 2 (middle)            | GND    | GND                      |
+| 3 (rightmost)         | TX     | GPIO31\_UART0\_TX (31)   |
+
+- **Settings**: 115200 baud / 8N1 / 3.3V TTL
+- Connect a USB-TTL adapter: adapter TX → pin 1, GND → pin 2, adapter RX → pin 3
+
+### LED configuration
+
+Copper ports use LED SET0, SFP ports use LED SET1.
+
+| SET  | LED0                                             | LED2                                              |
+|------|--------------------------------------------------|---------------------------------------------------|
+| SET0 | Amber — lights on 2.5G link                      | Green — lights on 1G / 100M / 10M link            |
+| SET1 | All speeds — lights on any link with activity    | —                                                 |
+
+LED pad to physical port mapping:
+
+| GPIO pads | Port                    |
+|-----------|-------------------------|
+| GPIO8–11  | Physical port 5 (left SFP)  |
+| GPIO12–14 | Physical port 1 (RJ45 1)    |
+| GPIO15–17 | Physical port 2 (RJ45 2)    |
+| GPIO18–20 | Physical port 3 (RJ45 3)    |
+| GPIO21–23 | Physical port 4 (RJ45 4)    |
+| GPIO24–27 | Physical port 6 (right SFP) |
+
+### SFP GPIO assignments
+
+| SFP              | pin\_detect (ModAbs)        | pin\_los               | SerDes | I2C SDA              | I2C SCL                  |
+|------------------|-----------------------------|------------------------|--------|----------------------|--------------------------|
+| Left (logical 8) | GPIO30\_ACL\_BIT3\_EN       | GPIO37                 | SDS1   | GPIO39\_I2C\_SDA4    | GPIO40\_I2C\_SCL3\_MDC1  |
+| Right (logical 3)| GPIO50\_I2C\_SCL2\_UART1\_TX | GPIO51\_I2C\_SDA2\_UART1\_RX | SDS0 | GPIO41\_I2C\_SDA3\_MDIO1 | GPIO40\_I2C\_SCL3\_MDC1 |
+
+GPIO assignments were verified by observing GPIO state changes during SFP module insertion/removal
+and cross-checked against an original firmware register dump.
+`pin_tx_disable` is GPIO\_NA on both ports (original firmware keeps all GPIOs as inputs).
@@ -0,0 +1,36 @@
+# Hisource Hi-K0801WS
+
+Following is documentation for unmanaged switch marked as `Hi-K0801WS`.
+
+Using SPI clamp in-board is the only method for initial installation.
+
+### Label specifications
+
+- **Name**: 2.5G Ethernet Switch  
+- **Model**: Hi-K0801WS  
+- **Ports**:  
+  - 8 × RJ45: 10/100/1000/2500 Mbps  
+  - 1 × SFP: 1000 / 2500 / 10000 Mbps  
+
+### What works (expected from label + similar devices)
+
+- All eight 2.5GBASE-T RJ45 ports at 10/100/1000/2500 Mbps  
+- SFP port supporting 1G, 2.5G and 10G modules 
+- LEDs
+
+### PCB overview
+
+**Board markings**  
+- Top silkscreen: PCB-KO801W-V2.0 / DIP-KO801WS-V2.0  
+
+Top side
+
+<img src="photos/K0801W-V2.0-unmanaged\PCB-top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/K0801W-V2.0-unmanaged\PCB-bottom.jpg" width="300" />
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
@@ -0,0 +1,23 @@
+# K0501W V2.0
+
+This board appears for example in the Davuaz Da-K6501W switch.
+
+The general design of the board is similar to Hi-K0402WS V3.0.
+However, there are several differences:
+- One SFP port is replaced by a RTL8221B 2.5G PHY
+- Only one LED is populated for the SFP port
+- No mode switch and only one flash chip
+- Older design using RTL8372 instead of RTL8372N (which also means different GPIO and LED configuration)
+- Like earlier versions of the K0402W(S) board, there is no UART
+
+All ports and LEDs are supported.
+Installation is possible using a flash programmer.
+The BoyaMicro 25Q16BSSIG flash chip is supported by flashprog with chip name "B.25D16AS/BY25Q16BS/BY25Q16ES".
+
+## PCB pictures
+
+The board is marked `PCB-K0501W-V2.0 DIP-K0501WS-V2.0`.
+
+<img src="photos/K0501W_V2_0/pcb-top.jpg" width="300" />
+
+<img src="photos/K0501W_V2_0/pcb-bottom.jpg" width="300" />
@@ -0,0 +1,57 @@
+# Keeplink KP-9000-6XH-X2
+
+Following is documentation for unmanaged switch marked as `KP-9000-6XH-X2`.
+
+Using SPI clamp in-board is the only method for initial installation.
+
+### Label specifications
+
+- **Name**: 4X 2.5G RJ45 Port + 2 X 10G SFP+ Port  
+- **Model**: KP-9000-6XH-X2  
+- **Ports**:  
+  - 4 × RJ45: 10/100/1000/2500 Mbps  
+  - 2 × SFP+: 1000 / 2500 / 10000 Mbps  
+
+### What works
+
+- All four 2.5GBASE-T RJ45 ports at 10/100/1000/2500 Mbps
+- SFP port with 10G modules 
+- LEDs
+- untested due to missing Hardware: SFP+ ports equipped with 1G or 2.5G SFPs.
+
+### Hardware overview
+
+Front side:
+
+<img src="photos/2M-PCB43-V2.1-unmanaged/KP-9000-6XH-X2-front.jpg" width="600" />
+
+Label:
+
+<img src="photos/2M-PCB43-V2.1-unmanaged/KP-9000-6XH-X2-label.jpg" width="600" />
+
+
+
+### PCB overview
+
+**Board markings**  
+- Top silkscreen: 2M-PCB43-V2.1
+
+Top side
+
+<img src="photos/2M-PCB43-V2.1-unmanaged/2M-PCB43-V2.1-top.jpg" width="600" />
+
+Bottom
+
+<img src="photos/2M-PCB43-V2.1-unmanaged/2M-PCB43-V2.1-bottom.jpg" width="600" />
+
+## Reset Button
+
+There's an unpopulated Reset button on the front left side of the PCB.
+It can easily be soldered, you'll need an 4.5mmx4.5mm 90° button switch with a 3-pin footprint.
+I got mine here: https://de.aliexpress.com/item/1005007295346702.html
+The front case has already the hole in the metal case, you just have to punch a hole through the foil.
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
+
@@ -0,0 +1,76 @@
+# PCB-K0402WS-V3.0
+
+Following is documentation for a variety of unmanaged switch internally marked as `PCB-K0402WS-V3.0`. They are sold under many brands.
+
+Original software is running UART on 9600 baud rate.
+
+Note during opening the device: there might be a hidden 5th screw on the back
+of the device just above the big label, might be covered by a QC sticker.
+
+### Brands
+
+* Hisource Hi-K0402WS
+
+<img src="photos/PCB-K0402WS-V3.0/HiSource_HI-K0402WS.jpg" width="300" />
+
+* Ztyuav Z-QWYT0402
+
+<img src="photos/PCB-K0402WS-V3.0/Ztyuav_Z-QWYT0402.jpg" width="300" />
+
+<img src="photos/PCB-K0402WS-V3.0/Ztyuav_Z-QWYT0402_label.jpg" width="300" />
+
+### Programming
+
+Using SPI clamp in-board is the only method for initial installation.
+
+The board has two flash chips `BY25Q16BS` with 16M-bit size. The front switch, switches between the two flash chips.
+These can be programed independently by using said switch - so it is e.g. possible to run the original and new firmware in parallel.
+The switch actually controls the HOLD line of each flash chip, and toggling the switch results in a reboot.
+
+If the programming clip keeps HOLD not connected, the flashing will commence on whatever the switch selected, regardless on which chip was clipped.
+
+For the initial flash (at least with flashrom), the bin file produced by the build is much smaller than the flash chip, it is suggested to pad the file to keep flashrom happy: `truncate -s 2097152 rtlplayground-*-PCB_K0402WS_V3.bin`. Note: do not then proceed to use this resulting padded file for the web flashing (as it bricks the device), use the original unpadded .bin.
+
+### What works (expected from label + similar devices)
+
+- All four 2.5GBASE-T RJ45 ports at 10/100/1000/2500 Mbps  
+- Both SFP ports supporting 1G, 2.5G and 10G modules 
+- LEDs
+
+### PCB overview
+
+**Board markings**  
+- Top silkscreen: PCB-KO4022W-V3.0 / DIP-KO4022WS-V3.0  
+
+Top side
+
+<img src="photos/PCB-K0402WS-V3.0/PCB-top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/PCB-K0402WS-V3.0/PCB-bottom.jpg" width="300" />
+
+### T2, serial console
+
+| `J2` pin | Signal      |
+| -------- | ----------- |
+| 1        | 3V3         |
+| 2        | RX (Input) |
+| 3        | TX (Output)  |
+| 4        | GND         |
+
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
+Board has two supply rails. `0.95` and `3.3` volt.
+
+### `0.95` Core Voltage
+
+Voltage is made by a `Techcode TD1720` .
+
+### `3.3` Voltage
+
+Voltage is created by chip marked as `Techcode TD1720`.
+
+**There seems to have been a miscalculation when choosing the inductor and the device is ~25% more efficient with an 5V power supply.**
@@ -0,0 +1,43 @@
+# Steamemo IG204-V1
+
+Following is documentation for unmanaged switch marked as `IG204-V1`.
+
+Using SPI clamp in-board is the only method for initial installation.
+
+### Label specifications
+
+- **Name**: 2.5G Ethernet Switch  
+- **Model**: IG204 V1
+- **Ports**:  
+  - 4 × RJ45: 10/100/1000/2500 Mbps  
+  - 2 × SFP: 1000 / 2500 / 10000 Mbps  
+
+### What works (expected from label + similar devices)
+
+- Four 2.5GBASE-T RJ45 ports at 10/100/1000/2500 Mbps  
+- Two SFP ports supporting 1G, 2.5G and 10G modules 
+- LEDs
+
+### PCB overview
+
+**Board markings**  
+- Top silkscreen: PB-2131
+
+
+Top side
+
+<img src="photos/STEAMEMO_IG204_V1/PCB-top.jpg" width="600" />
+
+### Connectors
+### T7, serial console
+
+| `T7` pin | Signal      |
+| -------- | ----------- |
+| 1        | TX (Output) |
+| 2        | GND         |
+| 3        | RX (Input)  |
+| 4        | 3V3         |
+
+### Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
@@ -0,0 +1,54 @@
+# SWTG018AS-A V2.0
+
+The following is a documentation for the unmanaged switch marked as `SWTG018AS-A V2.0`.
+It is e.g. sold under the Ampcom brand, but no branh-markings are found on the device.
+
+The original software is running UART on 9600 baud rate. 
+
+Using a SOIC clamp in-board is the only method for initial installation.
+
+The board has a single flash chips `BS` with 4M-bit size. The front switch, switches between the two flash chips.
+These can be programed independently by using said switch - so it is e.g. possible to run the original and new firmware in parallel.
+
+### Label specifications
+
+- **Name**: 9-Ports 2.5G Ethernet Switch
+- **Ports**:
+  - 8 × RJ45: 10/100/1000/2500 Mbps
+  - 1 × SFP+: 1000 / 2500 / 10000 Mbps
+- **Power**: 12V DC, 1A barrel connector 
+
+<img src="photos/SWTG018AS_A_V_2_0/label.jpg" width="300" />
+
+### What works
+The device is fully supported:
+- All 8 2.5GBASE-T RJ45 ports work at 10/100/1000/2500 Mbps
+- The SFP+ port supports 1G, 2.5G and 10G modules 
+- LEDs work with the same indiciations as the OEM firmware
+
+### PCB overview
+
+**Board markings**
+- Top silkscreen: SWTG018AS-A-V2.0.1_19649
+
+Top side
+
+<img src="photos/SWTG018AS_A_V_2_0/pcb_top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/SWTG018AS_A_V_2_0/pcb_bottom.jpg" width="300" />
+
+### J1, serial console
+
+| `J1` pin | Signal      |
+| -------- | ----------- |
+| 1        | 3V3         |
+| 2        | GND         |
+| 3        | RX (Input) |
+| 4        | TX (Output)  |
+
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
@@ -0,0 +1,213 @@
+### SWTG024AS
+SWTG024AS has at least 4 variants that look the same.
+
+Variants are `managed` and a `unmanaged` version.
+But both have pcb version `v1.0` and `v2.0`. 
+Also the RJ45 connectors can be all plastic/non-shielded or with metal shielding.
+
+## Brands
+|Brand|Type|Managed|PCB|PCB Label|Flash|Chip RTL|
+|---|---|---|---|---|---|---|
+| LIANGUO |SWTG024AS |No|  SWTG024AS-v2.0-17452 | CM-23-11-2336 023-17453| 512 KiB | 8272 |
+| Haraco |ZX-SWTG124AS | Yes |  SWTG024AS-v2.0 | ??? | ??? | 8272 |
+| Xikestore |SKS3200M-4GPY2XF | Yes |  SWTG024AS-v1.0 | CM-23-08-2043 023-16721 | ??? | 8272 |
+| Sodola | SL-SWTG124AS-D | Yes | SWTG024AS-v2.0-17452 | ??? | 2048 KiB | 8272 |
+
+## PCB
+
+<img src="photos/SWTG024AS-v2.0-unmanaged/SWTG024AS-v2.0-top-uman.png" width="300" />
+
+# SWTG024AS-v2.0 managed vs unmanged
+Changes I found with my board vs [Managed version](https://github.com/up-n-atom/SWTG118AS/tree/main/photos/SWGT024AS-v2.0) of the PCB.
+
+### Bottom
+* R105: Installed, goes to R10-PullDown SFP2 (J2) -> TX-DISABLE
+* R85: Not Installed (Connected to K1 Reset Button)
+* R90: Not installed (System Led)
+* LED3: Not installed (System Led)
+### Top
+* K1: Not installed (Reset Button)
+* R95: Installed (SFP2 (J2) signal RX-LOS), means that the managed-version can´t use the RX-LOS function.
+* R270: Installed (SFP1 (J4) signal RX-LOS), same here as above.
+* R268: Installed (SFP2 (J2) signal TX-DISABLE, but R262 200R pull-down is to high to drive by the SOC, needs mod!)
+* U5: Flash is only 512 KiB instead of 2/4 MiB.
+
+### Notes
+* `TX-Disable`-SFP2 and Button `K1` share the same GPIO pin via `R105` and `R85`.
+  But via `R88`, `TX-Disable`-SFP2 can be mapped to `GPIO36`.
+* `TX-Disable` pull-down resistos on both SFP are to low to drive by the SOC.
+  We need to make a `Best`-BOM variant so we can use all the featues.
+
+# Connectors
+
+## Port overview
+
+```
+┌────────────────────────────────────────────────────────────────────────────────────────┐
+│                                                       ┌──────────┐        ┌──────────┐ │
+│     ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐   │ SFP (J4) │        │ SFP (J2) │ │
+│     │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │   │ PORT   5 │        │ PORT   6 │ │
+│     │  PORT 1 │ │  PORT 2 │ │  PORT 3 │ │  PORT 4 │   │ MAC    8 │        │ MAC    3 │ │
+│  O  │  MAC  4 │ │  MAC  5 │ │  MAC  6 │ │  MAC  7 │   │ SerDes 1 │        │ SerDes 0 │ │
+│ RST └─────────┘ └─────────┘ └─────────┘ └─────────┘   └──────────┘        └──────────┘ │
+└────────────────────────────────────────────────────────────────────────────────────────┘
+``` 
+
+## J4
+
+* Location: Left SFP connector `J4`.
+* Connected to: 10GMAC number 8, second SerDes.
+
+|`J4` SFP1 PINs | Signal | Component | GPIO | Notes |
+|---|---|---|---|---|
+|2|	TX_FAULT	        | B-R262	       | --- | | 
+|3|	TX_DISABLE	      | B-R263, T-R268 | GPIO38 | R262 = Pull-down 200R|
+|4|	MODDEF2 – SDA     |	B-R261, T-R266 | GPIO39 | |
+|5|	MODDEF1 – SCL     |	B-R260, T-R267 | GPIO40	| Shared with both SFP |
+|6|	MODDEF0 – PRESENT |	B-R259, T-R296 | GPIO30 | |
+|7|	RATE SEL          |	B-R257	       | ---    | |
+|8|	LOS	              | B-R258, T-R270 | GPIO37 | | 
+|9|	TO?               | B-R256	       | ---    | |
+
+## J2
+
+* Location: Right SFP connector `J2`.
+* Connected to: 10GMAC number 3, first SerDes.
+
+|`J2` SFP2 PINs | Signal | Component | GPIO | Notes |
+|---|---|---|---|---|
+|2|	TX_FAULT	        | B-R70	         | ---	  | |
+|3|	TX_DISABLE	      | B-R10, B-R105-R, T-R88-L | GPIO54	| R10 = Pull-down 200R |
+|4|	MODDEF2 – SDA     |	B-R26, T-R85   | GPIO41 | |
+|5|	MODDEF1 – SCL     |	B-R15, T-R87   | GPIO40	| Shared with both SFP |
+|6|	MODDEF0 – PRESENT |	B-R14, T-R89   | GPIO50	| |
+|7|	RATE SEL          |	B-R12	         | ---	  | | 
+|8|	LOS	              | B-R13, T-R95   | GPIO51	| | 
+|9|	TO?               | B-R11	         | ---	  | | 
+
+Note: component numbering `<L>-<REFDES>-<SIDE>`
+* L: Layer, T=Top, B=Bottom
+* REFDEES: full silkscreen like `R123`
+* SIDE: Side of the component. when the rj45 are facing towards you are you can read the silkscreen normal.
+  L = Left, R=right, B=bottom, T=top or P with a pin number.
+
+### T3, Slave Interface
+This connector goes to U4 `I2C EEPROM` and U10 `SPI FLASH`.
+Signals are based on that `U4` is likely a I2C-EEPROM, `U10` is likely other SPI-chip.
+|`T3` pin|what|Signal|
+|---|---|---|
+|1| U4-P6, 33R U10-P6 | I2C-SCL, SPI-CLK, Slave SCK/SCL/MDC/EE_SCL |
+|2| GND | --- |
+|3| U4-P5, U10-P5 | I2C-SDA, SPI-DI/DO, Slave SDI/SDA/MDIO/EE_SDA |
+|4| VCC |
+|5| 33R -> U10-P2 | SPI-DO/D1 | 
+|6| U10-P1 | SPI-CS |
+Note: 1 pin is square shaped.
+
+The Slave Interface allows an extenal host to controll the SOC even if the internal MCU is used.
+Depending on the `IF_SEL` bootstrap resistors, this can me `I2C`, `SPI` or `SMI`.
+On this device it is `I2C` on address `0b1011100` or `0x5c` (7-bit notation).
+
+* I2c Read:  must be a write_read opperation `<Dev-ADDR><RegAddr15:8><RegAddr7:0>` `<DevAddr><Data7:0><Data15:8><Data23:16><Data31:24>`.
+* I2c Write: `<Dev-ADDR><RegAddr15:8><RegAddr7:0><DevAddr><Data7:0><Data15:8><Data23:16><Data31:24>`.
+
+Example register `0x0004` return chip id `0x00, 0x00, 0x72, 0x83` = `0x83720000`.
+
+### T5, serial console
+|`T5` pin|GPIO|Signal|
+|---|---|---|
+| 1 | GPIO31 | U0TXD (Output) |
+| 2 | GND | |
+| 3 | GPIO32 | U0RXD (Input) |
+| 4 | 3V3 | |
+Note: 1 pin is square shaped.
+
+### T8
+|`T8` pin|what|Signal|
+|---|---|---|
+| 1 | GPIO46 | |
+| 2 | GND    | |
+| 3 | GPIO48 | |
+| 4 | 3V3    | |
+| 5 | GPIO47 | |
+| 6 | GPIO49 | |
+Note: 1 pin is square shaped.
+
+# Reset ciruit
+| Cmp | Function |
+|---|---|
+| T-R78  | 33k PullUp      |
+| T-D3   | Discharge Diode |
+| T-C187 | RC-Delay        |
+
+Reset-line found at `T-D3-D` active-low.
+
+# GPIO
+| HEX VAL. | GPIO   | Component | What |  | GPIO | Component | What |
+| -------- | ------ |  ---- | ---- | ---- | ---- | ---- | ---- |
+| 00000001 | GPIO00 | T-C151-T, T-R28-T, T-R29-T |?    | | GPIO32 | T-R143-R | U0RXD |
+| 00000002 | GPIO01 | T-C152-T                |?    | | GPIO33 |  |  |
+| 00000004 | GPIO02 | T-C153-T                |?    | | GPIO34 |  |  |
+| 00000008 | GPIO03 | T-R33-T                 |?    | | GPIO35 |  |  |
+| 00000010 | GPIO04 | B-C155                  |?    | | GPIO36 | T-R88-L, T-R84-B | Optional SFP2 TX-DISABLE[^2], Reset |
+| 00000020 | GPIO05 | B-C156                  |?    | | GPIO37 | SFP1-8, T-R270 | SFP-LOS |
+| 00000040 | GPIO06 | T-C157-T                |?    | | GPIO38 | SFP1-3, T-R268 | SFP1 TX-DISABLE[^2] |
+| 00000080 | GPIO07 | T-C158-T, R165          |?    | | GPIO39 | SFP1-4, T-R266 | I2C-SDA4 |
+| 00000100 | GPIO08 |                         |     |  | GPIO40 | SFP2-5, T-R87; SFP1-5, T-R267; | I2C-SCL |
+| 00000200 | GPIO09 | SFP2-LED, T-R36-T       |LED-SFP2 | | GPIO41 | SFP2-4, T-R85 | I2C-SDA |
+| 00000400 | GPIO10 |                         |     | | GPIO42 |  U8-P6, T-R124 | SPI-MEMORY, CLK |
+| 00000800 | GPIO11 |                         |LEDx[^1] | | GPIO43 | U8-P5, T-R127 | SPI-MEMORY, DI,IO0 |
+| 00001000 | GPIO12 |                         |LEDx[^1] | | GPIO44 | U8-P2, T-R128 | SPI-MEMORY, DO,IO1 |
+| 00002000 | GPIO13 | PORT1-LED-GREEN         |LEDx[^1] | | GPIO45 | U8-P1, T-R123 | SPI-MEMORY, CS  |
+| 00004000 | GPIO14 | PORT1-LED-YELLOW        |LEDx | | GPIO46 | T8-1, T-R188| ? |
+| 00008000 | GPIO15 |                         |LEDx[^1] | | GPIO47 | T8-5, T-R190 | ? |
+| 00010000 | GPIO16 | PORT2-LED-GREEN         |LEDx[^1] | | GPIO48 | T8-3, T-R189 | ? |
+| 00020000 | GPIO17 | PORT2-LED-YELLOW        |LEDx | | GPIO49 | T8-6, T-R190 | ? |
+| 00040000 | GPIO18 |                         |LEDx[^1] | | GPIO50 | SFP2-6, T-R89 | SFP-DETECT |
+| 00080000 | GPIO19 | PORT3-LED-GREEN         |LEDx[^1] | | GPIO51 | SFP2-8, T-R95 | SFP-LOS |
+| 00100000 | GPIO20 | PORT3-LED-YELLOW        |LEDx | | GPIO52 |  |  |
+| 00200000 | GPIO21 |                         |LEDx[^1] | | GPIO53 |  |  |
+| 00400000 | GPIO22 | PORT4-LED-GREEN         |LEDx[^1] | | GPIO54 | SFP2-3, T-R105-L | SFP2 TX-DISABLE[^2] or via T-R85 to RESET[^3], T-R84-T |
+| 00800000 | GPIO23 | PORT4-LED-YELLOW        |LEDx | | GPIO55 | T-R78-B | |
+| 01000000 | GPIO24 | SFP1-LED-J4, T-R35      |LED-SFP1 | | GPIO56 | | |
+| 02000000 | GPIO25 |                         |     | | GPIO57 | | |
+| 04000000 | GPIO26 | ?                       |LEDx | | GPIO58 | | |
+| 08000000 | GPIO27 | R44L                    |?    | | GPIO59 | | |
+| 10000000 | GPIO28 | LED-SYSTEM, T-R50-R     |LED-SYSTEM  | | GPIO60 | | |
+| 20000000 | GPIO29 | T-R187-R                |     | | GPIO61 | | |
+| 40000000 | GPIO30 | SFP1-6, T-R269          |SFP-DETECT | | GPIO62 | | |
+| 80000000 | GPIO31 | T-R144-R                |U0TXD| | GPIO63 | | |
+
+# LEDs
+
+| NAME | COMPONENTS | GPIO | Active |
+| ---- | ---------- | ---- | ------ |
+| SYSTEM | T-R50-R (PU-4k2), T-R49-L, T-C185-L, B-R90 | GPIO28 | Low |
+| SFP1 | T-R35-L (PU-3k9), T-R34-L, T-C179-L | GPIO24 | Low |
+| SFP2 | T-R36-T (PD-4k0) | GPIO09 | High |
+| PORT1-LED-YELLOW |  | GPIO14 | Low |
+| PORT2-LED-YELLOW |  | GPIO17 | Low |
+| PORT3-LED-YELLOW |  | GPIO20 | Low |
+| PORT4-LED-YELLOW |  | GPIO23 | Low |
+
+# Power supply
+
+Board has two supply rails.
+`0.95` and `3.3` volt.
+
+## `0.95` Core Voltage.
+
+Voltage is made by a `Richtek RT8120A` Buck converter.
+0.95V must be within 3%.
+
+## `3.3` Voltage
+
+Voltage is crated by a `TMI3244T` Buck converter.
+3.3V must be within 4.5%.
+Chip can deliver up to 4A and the sweetspot is at 1A.
+So higher power SFP-modules should work.
+
+
+[^1]: LEDs are found by just plugin a RJ45 connector and see with cmd `gpio` the status change. But the bit pattern for port 1,2 are diffrent from port 3,4.
+[^2]: Only on the unmanaged verions are `R10` and `R268` placed. But the very low pull-down resistor `R10` and `R262` prevent to SOC to drive does pins. A mod is needed.
+[^3]: GPIO54 is used for the reset-button. `T-R85` is placed.
@@ -0,0 +1,164 @@
+### ZX-SWTGW215AS
+
+## Brands
+|Brand|Type|Managed|PCB|Flash|Chip RTL|
+|---|---|---|---|---|---|
+| Lianguo | ZX-SWTGW215AS | Yes | PCB-SWTG115AS-V2.0 | FM25Q16A | 8272 |
+
+## RTLPlayground target
+
+Use machine target `MACHINE_LIANGUO_ZX_SWTGW215AS` for this device.
+
+Physical hardware verification: 5x RJ45 ports + 1x SFP port. 
+Port 5 RJ45 is interfaced through a RTL8221B IC.
+
+## PCB
+
+<img src="photos/ZX-SWTGW215AS/pcb_top.jpg" width="300" />
+
+# Connectors
+
+## Port overview
+
+```
+┌──────────────────────────────────────────────────────────────────────────────────┐
+│                                                                   ┌──────────┐   │
+│     ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐   │ SFP (J4) │   │
+│     │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │   │  PORT 6  │   │
+│     │  PORT 1 │ │  PORT 2 │ │  PORT 3 │ │  PORT 4 │ │  PORT 5 │   │  LOG  8  │   │
+│  O  │  LOG  4 │ │  LOG  5 │ │  LOG  6 │ │  LOG  7 │ │  LOG  3 │   │ SerDes 1 │   │
+│ RST └─────────┘ └─────────┘ └─────────┘ └─────────┘ └─────────┘   └──────────┘   │
+└──────────────────────────────────────────────────────────────────────────────────┘
+```
+
+| Type | RTLPlayground logical ports | Physical index | 
+|---|---|---|
+| RJ45 | 3, 4, 5, 6, 7 | 1-5 | 
+| SFP | 8 | 6 |
+
+## J4
+
+* Location: SFP connector `J4`.
+* Connected to: 10GMAC number 8, SerDes 1.
+
+|`J4` SFP PINs | Signal | GPIO | Notes |
+|---|---|---|---|
+|3|	TX_DISABLE	      | GPIO_NA | Not connected |
+|4|	MODDEF2 – SDA     | GPIO39 | I2C SDA |
+|5|	MODDEF1 – SCL     | GPIO40	| I2C SCL |
+|6|	MODDEF0 – PRESENT | GPIO30 | Detect |
+|8|	LOS	              | GPIO37 | RX Loss of Signal |
+### Notes
+* Not all signals were mapped mechanically, hence they've been left out of documentation.
+
+## T3, Slave Interface
+
+This connector goes to U4 `I2C EEPROM` and U10 `SPI FLASH` (mappings identical to SWTG024AS).
+
+For detailed Slave Interface functionality and protocol information, see [T3 documentation in SWTG024AS.md](SWTG024AS.md#t3-slave-interface).
+
+|`T3` pin|what|Signal|
+|---|---|---|
+|1| U4-P6, 33R U10-P6 | I2C-SCL, SPI-CLK, Slave SCK/SCL/MDC/EE_SCL |
+|2| GND | --- |
+|3| U4-P5, U10-P5 | I2C-SDA, SPI-DI/DO, Slave SDI/SDA/MDIO/EE_SDA |
+|4| VCC |
+|5| 33R -> U10-P2 | SPI-DO/D1 | 
+|6| U10-P1 | SPI-CS |
+### Notes
+* 1 pin is square shaped.
+
+
+## T5, Serial Console
+
+|`T5` pin|GPIO|Signal|
+|---|---|---|
+| 1 | GPIO31 | U0TXD (Output) |
+| 2 | GND | |
+| 3 | GPIO32 | U0RXD (Input) |
+| 4 | 3V3 | |
+### Notes
+* 1 pin is square shaped.
+
+## T8
+
+|`T8` pin|GPIO|Signal|
+|---|---|---|
+| 1 | GPIO46 | |
+| 2 | GND    | |
+| 3 | GPIO48 | |
+| 4 | 3V3    | |
+| 5 | GPIO47 | |
+| 6 | GPIO49 | |
+
+### Notes
+* 1 pin is square shaped.
+* Mapping unverified but assumed the same as [LIANGUO SWTG024AS](SWTG024AS.md#t8).
+
+# Reset Circuit
+| Function | GPIO |
+|---|---|
+| Reset button | GPIO54 |
+### Notes
+* Circuit is active-low
+
+# GPIO
+
+Note: T3/U4/U10-related signal annotations below are copied from [LIANGUO SWTG024AS T3 section](SWTG024AS.md#t3-slave-interface) as well as T8 port from [LIANGUO SWTG024AS T8 section](SWTG024AS.md#t8). They should be treated as assumed identical for ZX-SWTGW215AS as it has not been 100% confirmed true at the moment. 
+
+| HEX VAL. | GPIO   | Component / Purpose | Notes |  | GPIO | Component / Purpose | Notes |
+| -------- | ------ |  ---- | ---- | ---- | ---- | ---- | ---- |
+| 00000001 | GPIO00 | | |  | GPIO32 | T5-3 | U0RXD |
+| 00000002 | GPIO01 | | |  | GPIO33 |   |  |
+| 00000004 | GPIO02 | | |  | GPIO34 |   |  |
+| 00000008 | GPIO03 | | |  | GPIO35 |   |  |
+| 00000010 | GPIO04 | | |  | GPIO36 |   |  |
+| 00000020 | GPIO05 | | |  | GPIO37 | J4-8 | SFP LOS |
+| 00000040 | GPIO06 | | |  | GPIO38 |   |  |
+| 00000080 | GPIO07 | | |  | GPIO39 | J4-4 | SFP I2C SDA |
+| 00000100 | GPIO08 | | |  | GPIO40 | J4-5 | SFP I2C SCL |
+| 00000200 | GPIO09 | | |  | GPIO41 |   |  |
+| 00000400 | GPIO10 | | |  | GPIO42 | U10-P6, U4-P6, T3-1 | SPI FLASH CLK / I2C-SCL (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00000800 | GPIO11 | | |  | GPIO43 | U10-P5, U4-P5, T3-3 | SPI FLASH DI/IO0 / I2C-SDA (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00001000 | GPIO12 | | |  | GPIO44 | U10-P2, T3-5 | SPI FLASH DO/IO1 (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00002000 | GPIO13 | PORT1 LED GREEN |  |  | GPIO45 | U10-P1, T3-6 | SPI FLASH CS (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00004000 | GPIO14 | PORT1 LED ORANGE |  |  | GPIO46 | T8-1 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00008000 | GPIO15 | | |  | GPIO47 | T8-5 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00010000 | GPIO16 | PORT2 LED GREEN |  |  | GPIO48 | T8-3 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00020000 | GPIO17 | PORT2 LED ORANGE |  |  | GPIO49 | T8-6 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00040000 | GPIO18 | PORT3 LED GREEN |  |  | GPIO50 |   |  |
+| 00080000 | GPIO19 | PORT3 LED ORANGE |  |  | GPIO51 |   |  |
+| 00100000 | GPIO20 | PORT4 LED GREEN |  |  | GPIO52 |   |  |
+| 00200000 | GPIO21 | PORT4 LED ORANGE |  |  | GPIO53 |   |  |
+| 00400000 | GPIO22 | PORT5 LED GREEN |  |  | GPIO54 | Reset Button | GPIO54_ACL_BIT2_EN |
+| 00800000 | GPIO23 | PORT5 LED ORANGE |  |  | GPIO55 |   |  |
+| 01000000 | GPIO24 | SFP LED GREEN | J4 |  | GPIO56 |   |  |
+| 02000000 | GPIO25 | | |  | GPIO57 |   |  |
+| 04000000 | GPIO26 | | |  | GPIO58 |   |  |
+| 08000000 | GPIO27 | | |  | GPIO59 |   |  |
+| 10000000 | GPIO28 | LED-SYSTEM |  |  | GPIO60 |   |  |
+| 20000000 | GPIO29 | | |  | GPIO61 |   |  |
+| 40000000 | GPIO30 | J4-6 | SFP DETECT |  | GPIO62 |   |  |
+| 80000000 | GPIO31 | T5-1 | U0TXD |  | GPIO63 |   |  |
+
+# LEDs
+
+| NAME | GPIO | Port(s) | Function | Notes |
+| ---- | ---- | ---- | ---- | ---- |
+| PORT1 LED GREEN | GPIO13 |5| Activity | LEDS_2G5, LEDS_LINK, LEDS_ACT |
+| PORT1 LED ORANGE | GPIO14 | 5 | Speed | LEDS_1G, LEDS_100M, LEDS_10M, LEDS_LINK, LEDS_ACT |
+| PORT2 LED GREEN | GPIO16 | 4 | Activity | LEDS_2G5, LEDS_LINK, LEDS_ACT |
+| PORT2 LED ORANGE | GPIO17 | 4 | Speed | LEDS_1G, LEDS_100M, LEDS_10M, LEDS_LINK, LEDS_ACT |
+| PORT3 LED GREEN | GPIO18 | 3 | Activity | LEDS_2G5, LEDS_LINK, LEDS_ACT |
+| PORT3 LED ORANGE | GPIO19 | 3 | Speed | LEDS_1G, LEDS_100M, LEDS_10M, LEDS_LINK, LEDS_ACT |
+| PORT4 LED GREEN | GPIO20 | 2 | Activity | LEDS_2G5, LEDS_LINK, LEDS_ACT |
+| PORT4 LED ORANGE | GPIO21 | 2 | Speed | LEDS_1G, LEDS_100M, LEDS_10M, LEDS_LINK, LEDS_ACT |
+| PORT5 LED GREEN | GPIO22 | 1 | Activity | LEDS_2G5, LEDS_LINK, LEDS_ACT |
+| PORT5 LED ORANGE | GPIO23 | 1 | Speed | LEDS_1G, LEDS_100M, LEDS_10M, LEDS_LINK, LEDS_ACT |
+| SFP LED GREEN | GPIO24 | 6 (SFP J4) | Multi-speed | LEDS_10G, LEDS_5G, LEDS_2G5, LEDS_1G, LEDS_100M, LEDS_LINK, LEDS_ACT |
+| LED-SYSTEM | GPIO28 | --- | System status | --- |
+
+## Notes
+
+While [SWTG024AS.md](SWTG024AS.md) can be used as a general reference for hardware concepts and interface specifications, this device should not be assumed to be identical beside the difference implicitely highlighted below. Not all information has been validated for compatibility with the SWTG215AS. Consult the SWTG024AS documentation with caution and verify any critical details against this device's.
+
@@ -0,0 +1,24 @@
+### ZX-SWTGW218AS
+
+## Brands
+|Brand|Type|Managed|PCB|Flash|Chip RTL|
+|---|---|---|---|---|---|
+| Mokerlink | ZX-SWTGW218AS | Yes|  SWTG118AS-V2.0-16029 | 2MB (FM25Q16A)| 8273N + 8224N |
+| Sodola | | | | | |
+| Horaco | | | | | |
+
+
+## Photos
+
+<img src="photos/SWTGW218AS-managed/front.png" width="800" />
+
+<img src="photos/SWTGW218AS-managed/label.jpg" width="800" />
+
+## PCB
+
+See up'n'atom's Repo:
+
+https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-top.JPG
+
+https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-bottom.JPG
+
@@ -0,0 +1,174 @@
+# TrendNet TEG-S562
+
+Following is documentation for unmanaged switch marked as `TEG-S563/EU H/W: V1.0R`.
+
+Original software is running UART on 57600 baud rate. The software does not allow to
+do anything fancy via serial. There is `IP` configuration which can be printed as well.
+There might be also some flash upload procedure, but using SPI clamp in-board seems to
+be easier method.
+
+The memory chip is `Winbond W25Q16JV` with 16M-bit size.
+
+## What does work
+
+1. 2.5G ports on all advertised speeds.
+2. SFP+ communication.
+3. Serial, Web UI.
+4. All LEDs
+
+## Known issues
+
+None.
+
+## PCB
+
+Manufacturer information be found [on the product page](https://www.trendnet.com/support/support-detail.asp?prod=105_TEG-S562).
+
+Top side
+
+<img src="photos/TEG-S562/TEG-S562-v1.0R-top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/TEG-S562/TEG-S562-v1.0R-bottom.jpg" width="300" />
+
+## Connectors
+
+### Port overview
+
+```
+┌─────────────────────────────────────────────────────────────────────────────┐
+│                                                   ┌──────────┐ ┌──────────┐ │
+│ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌─────────┐   │ SFP    2 │ │ SFP    1 │ │
+│ │  RJ45   │ │  RJ45   │ │  RJ45   │ │  RJ45   │   │ PORT   5 │ │ PORT   6 │ │
+│ │  PORT 1 │ │  PORT 2 │ │  PORT 3 │ │  PORT 4 │   │ MAC    8 │ │ MAC    3 │ │
+│ │  MAC  4 │ │  MAC  5 │ │  MAC  6 │ │  MAC  7 │   │ SerDes 0 │ │ SerDes 1 │ │
+│ └─────────┘ └─────────┘ └─────────┘ └─────────┘   └──────────┘ └──────────┘ │
+└─────────────────────────────────────────────────────────────────────────────┘
+```
+
+### J2, serial console
+
+| `J2` pin | Signal      |
+| -------- | ----------- |
+| 1        | 3V3         |
+| 2        | TX (Output) |
+| 3        | RX (Input)  |
+| 4        | GND         |
+
+Note: 1 pin is square shaped, towards the power input.
+
+### J5, power pass-thru
+
+| `J5` pin | Signal |
+| -------- | ------ |
+| 1        | 12V    |
+| 2        | 12V    |
+| 3        | GND    |
+| 4        | GND    |
+
+Note: 1 pin is square shaped.
+
+### U5, I2C eeprom placeholder
+
+| `J5` pin | Signal        |
+| -------- | ------------- |
+| 1        | GND           |
+| 2        | GND           |
+| 3        | GND           |
+| 4        | GND           |
+| 5        | 3V3           |
+| 6        | ??? Logic Low |
+| 7        | SCL           |
+| 8        | SDA           |
+
+SOC I2C address is 0x5c.
+
+### SW1 GPIO switch?
+
+Not populated but looks like a switch for selecting
+GPIO level. Missing resistors in place.
+
+GPIO mapping unknown.
+
+### S2 Reset ciruit
+
+Not populated but looks like a button can be added on `S2` connector,
+requires additional `R571` resistor which will pull signal to ground.
+
+GPIO mapping unknown.
+
+### GPIO
+
+| HEX VAL. | GPIO   | When            | GPIO   | When                   |
+| -------- | ------ | ----------------| ------ | -----------------------|
+| 00000001 | GPIO00 |                 | GPIO32 |                        |
+| 00000002 | GPIO01 |                 | GPIO33 |                        |
+| 00000004 | GPIO02 |                 | GPIO34 | Random changes         |
+| 00000008 | GPIO03 |                 | GPIO35 |                        |
+| 00000010 | GPIO04 |                 | GPIO36 | SFP2 Present           |
+| 00000020 | GPIO05 |                 | GPIO37 | SFP2 RX Los            |
+| 00000040 | GPIO06 |                 | GPIO38 | SFP1 Present           |
+| 00000080 | GPIO07 |                 | GPIO39 |                        |
+| 00000100 | GPIO08 |                 | GPIO40 |                        |
+| 00000200 | GPIO09 |                 | GPIO41 |                        |
+| 00000400 | GPIO10 |                 | GPIO42 | Random changes         |
+| 00000800 | GPIO11 |                 | GPIO43 |                        |
+| 00001000 | GPIO12 | PORT1 Link      | GPIO44 |                        |
+| 00002000 | GPIO13 | PORT1-LED-GREEN | GPIO45 |                        |
+| 00004000 | GPIO14 | PORT1-LED-AMBER | GPIO46 | SFP1 I2C CLK           |
+| 00008000 | GPIO15 | PORT2 Link      | GPIO47 | SFP1 I2C SDA           |
+| 00010000 | GPIO16 | PORT2-LED-GREEN | GPIO48 | SFP2 I2C CLK           |
+| 00020000 | GPIO17 | PORT2-LED-AMBER | GPIO49 | SFP2 I2C SDA           |
+| 00040000 | GPIO18 | PORT3 Link      | GPIO50 | SFP1 Rx LOS            |
+| 00080000 | GPIO19 | PORT3-LED-GREEN | GPIO51 | SFP2 TX Disable        |
+| 00100000 | GPIO20 | PORT4-LED-AMBER | GPIO52 |                        |
+| 00200000 | GPIO21 | PORT4 Link      | GPIO53 |                        |
+| 00400000 | GPIO22 | PORT4-LED-GREEN | GPIO54 | SFP1 TX Disable        |
+| 00800000 | GPIO23 | PORT4-LED-AMBER | GPIO55 |                        |
+| 01000000 | GPIO24 |                 | GPIO56 |                        |
+| 02000000 | GPIO25 |                 | GPIO57 |                        |
+| 04000000 | GPIO26 |                 | GPIO58 |                        |
+| 08000000 | GPIO27 |                 | GPIO59 |                        |
+| 10000000 | GPIO28 |                 | GPIO60 |                        |
+| 20000000 | GPIO29 |                 | GPIO61 |                        |
+| 40000000 | GPIO30 |                 | GPIO62 |                        |
+| 80000000 | GPIO31 |                 | GPIO63 |                        |
+
+## LEDs
+
+Ports 1-4 are amber for 100M/1G links, Green for 2.5G.
+Port 5-6 are green for 10G/1G link. Both should flash on activity.
+
+| NAME             | When active    |
+| ---------------- | ---------------|
+| PWR              | 3V3            |
+| SFP1             |                |
+| SFP2             |                |
+| PORT1-LED-GREEN  | -              |
+| PORT2-LED-GREEN  | PORT2 2.5G     |
+| PORT3-LED-GREEN  | PORT3 2.5G     |
+| PORT4-LED-GREEN  | PORT4 2.5G     |
+| PORT1-LED-AMBER  | PORT1 1GB/100M |
+| PORT2-LED-AMBER  | PORT2 1GB/100M |
+| PORT3-LED-AMBER  | PORT3 1GB/100M |
+| PORT4-LED-AMBER  | PORT4 1GB/100M |
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 1A` adapter was provided.
+Board has two supply rails. `0.95` and `3.3` volt.
+
+### `0.95` Core Voltage
+
+Voltage is made by a `APW8713` (U3).
+
+### `3.3` Voltage
+
+Voltage is crated regulated by chip marked as `GoIAT` (U2).
+
+## SFP SPI
+
+There is separate clock and data lines for both SFP modules. MSDA/MSCK 0 and 1 need to be enabled.
+
+SFP1 slot is connected to SPI0. SFP2 slot is connected to SPI1.
@@ -0,0 +1,59 @@
+# ZX310S-4T2XH/
+
+The following is a documentation for the managed switch marked as `ZX310S-4T2XH`
+and sold by Horaco.
+
+The original software is running UART on 57600 baud rate. The solder holes
+of the UART header are filled in. In order to install a UART header, they
+need to be cleared first. A 1.2mm drill can be used, alternatively a
+de-soldering wick.
+The original firmware uses 57600 baud 8N1
+
+CPU: RTL8372
+Flash: 2MByte Winbond W25Q16DV (U3)
+PHY RTL8261BE
+
+### Label specifications
+
+- **Name**: 
+- **Ports**:
+  - 4 × RJ45: 10/100/1000/2500 Mbps
+  - 1 x RJ45: 10/100/1000/2500/5000/10000 Mbps
+  - 1 × SFP+: 1000 / 2500 / 10000 Mbps
+- **Power**: 12V DC, 2A barrel connector 
+
+<img src="photos/ZX310S-4T2XH/label.jpg" width="300" />
+
+### What works
+The device is fully supported:
+- All 4 2.5GBASE-T RJ45 ports work at 10/100/1000/2500 Mbps
+- The 10GBit port works. TODO: Fix EEE, speed selection
+- The SFP+ port supports 1G, 2.5G and 10G modules 
+- LEDs work with the same indiciations as the OEM firmware
+
+### PCB overview
+
+**Board markings**
+- Top silkscreen: PCB-SL310S-4T1T1X-V1.0.1-24107
+
+Top side
+
+<img src="photos/ZX310S-4T2XH/pcb_top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/ZX310S-4T2XH/pcb_bottom.jpg" width="300" />
+
+### J1, serial console
+
+| `J1` pin | Signal      |
+| -------- | ----------- |
+| 1        | TX (Output) |
+| 2        | RX (Input)  |
+| 3        | GND         |
+| 4        | 3V3         |
+
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 2A` adapter was provided.
@@ -0,0 +1,53 @@
+# ZX310S-4T2XT
+
+The following is a documentation for the managed switch marked as
+`ZX310S-4T2XT` and sold by Horaco.
+
+The original software is running UART on 57600 baud rate 8N1.
+
+CPU: RTL8372
+Flash: 2MByte Winbond W25Q16DV (U3)
+PHY 2x RTL8261BE
+
+### Label specifications
+
+- **Name**:
+- **Ports**:
+  - 4 × RJ45: 10/100/1000/2500 Mbps
+  - 2 x RJ45: 10/100/1000/2500/5000/10000 Mbps
+- **Power**: 12V DC, 2A barrel connector
+
+<img src="photos/ZX310S-4T2XT/label.jpg" width="300" />
+
+### What works
+The device is fully supported:
+- All 4 2.5GBASE-T RJ45 ports work at 10/100/1000/2500 Mbps, including EEE
+- The 10GBit ports works, including EEE.
+- LEDs work with the same indiciations as the OEM firmware
+
+### PCB overview
+
+**Board markings**
+- Top silkscreen: PCB-SL310S-4T2XT-V1.0.0-22273
+
+Top side
+
+<img src="photos/ZX310S-4T2XT/pcb_top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/ZX310S-4T2XT/pcb_bottom.jpg" width="300" />
+
+### J1, serial console
+
+| `J1` pin | Signal      |
+| -------- | ----------- |
+| 1        | TX (Output) |
+| 2        | RX (Input)  |
+| 3        | GND         |
+| 4        | 3V3         |
+
+
+## Power supply
+
+Input power is delivered via barell plug, `12V 2A` adapter was provided.
@@ -0,0 +1,41 @@
+# Understanding the image using ghidra
+Start ghidra, load file starting from offset 0x0002 into
+memory starting at 0x0000. The lengthe is 0x10000. Select generic 8051, big
+endian.
+
+After loading, the boot vector is at 0x0000, which will jump to 0x0100 for
+the boot routine.
+
+The firmware uses only bank 1 of the RTL837x since it is quite short.
+Otherwise the firmware would be organized as follows
+```
+--------------------------- 0x0000 ---------------------------------
+Boot-Vector
+ISRs
+Common Code
+Trampoline for inter-bank calls
+Inter-bank calls, calling trampoline, one for each callable function
+
+----- Bank 1 0x4000 ------   ---- Bank 2 0x4000 -----  -------- .....
+Overlay 1                    Overlay 2                 Overlay n
+
+--------- 0xffff ---------   -------- 0xffff --------  -------- 0xffff
+```
+The RTL837x firmware images are organized as follows:
+The first 2 bytes of the image give the size of the prefetched data at the
+start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which
+means that the entire shared area of the code memory in all banks,
+0x4000 bytes is read immediately into the code RAM.
+
+Common code starts at
+0x0002 in the image and has length 0x3ffd, the first bank starts at 0x4000
+in the image, is mapped to 0x4000 and has length 0xc000. The second bank
+starts at 0x10000, is mapped to 0x4000 and has length 0xc000. The third
+bank would start at 0x1c000 and would again be mapped to 0x4000.
+There are about 30 banks in use for managed switches, unmanaged ones use
+2-3, while the hardware would allow to use 0x3f banks, i.e. up to 4 MB of
+flash.
+
+The current image uses Common BANK0 and the first BANK1 via sdccs __banked
+function keyword and custom banking trampoline code for the RTL837x in
+assembler.
@@ -0,0 +1,98 @@
+
+# GPIO Pin, Function and MUX registers.
+
+These functions should bevalid for `RTL8372`, `RTL8372N`, `RTL8373`, and `RTL8373N`.
+
+`N`-version doesn't seems to have all the GPIO pins available on the outside of the package.
+
+| GPIO | Function | TYPE | MUX REG, BIT | (RTL8372) PIN# | (RTL8372N) PIN# |
+| ----- | ---- | ---- |  ---- | ---- | ---- |
+| GPIO0 | LED0 | I/OPU | IO_MUX_SEL_0, BIT 0 | G1 | 12 |
+| GPIO1 | LED1 | I/OPU | IO_MUX_SEL_0, BIT 1 | G2 | 15 |
+| GPIO2 | LED2 | I/OPU | IO_MUX_SEL_0, BIT 2 | G3 | 14 |
+| GPIO3 | LED3 | I/OPU | IO_MUX_SEL_0, BIT 3 | H1 | 16 |
+| GPIO4 | LED4 | I/OPU | IO_MUX_SEL_0, BIT 4 | H2 | 18 |
+| GPIO5 | LED5 | I/OPU | IO_MUX_SEL_0, BIT 5 | H3 | 20 |
+| GPIO6 | LED6 | I/OPU | IO_MUX_SEL_0, BIT 6 | J1 | 22 |
+| GPIO7 | LED7 | I/OPU | IO_MUX_SEL_0, BIT 7 | J2 | NoPin? |
+| GPIO8 | LED8 | I/OPU | IO_MUX_SEL_0, BIT 8 | J3 | 24 |
+| GPIO9 | LED9 | I/OPD | IO_MUX_SEL_0, BIT 9 | L1 | 23 |
+| GPIO10 | LED10 | I/OPU | IO_MUX_SEL_0, BIT 10 | L2 | 26 |
+| GPIO11 | LED11 | I/OPU | IO_MUX_SEL_0, BIT 11 | L3 | NoPin? |
+| GPIO12 | LED12 | I/OPD | IO_MUX_SEL_0, BIT 12 | M1 | 28 |
+| GPIO13 | LED13 | I/OPU | IO_MUX_SEL_0, BIT 13 | M2 | NoPin? |
+| GPIO14 | LED14 | I/OPU | IO_MUX_SEL_0, BIT 14 | M3 | NoPin? |
+| GPIO15 | LED15 | I/OPU | IO_MUX_SEL_0, BIT 15 | N1 | 25 |
+| GPIO16 | LED16 | I/OPU | IO_MUX_SEL_0, BIT 16 | N2 | NoPin? |
+| GPIO17 | LED17 | I/OPU | IO_MUX_SEL_0, BIT 17 | N3 | NoPin? |
+| GPIO18 | LED18 | I/OPD | IO_MUX_SEL_0, BIT 18 | P1 | 30 |
+| GPIO19 | LED19 | I/OPU | IO_MUX_SEL_0, BIT 19 | P2 | NoPin? |
+| GPIO20 | LED20 | I/OPU | IO_MUX_SEL_0, BIT 20 | P3 | NoPin? |
+| GPIO21 | LED21 | I/OPU | IO_MUX_SEL_0, BIT 21 | R1 | 27 |
+| GPIO22 | LED22 | I/OPU | IO_MUX_SEL_0, BIT 22 | R2 | NoPin? |
+| GPIO23 | LED23 | I/OPU | IO_MUX_SEL_0, BIT 23 | R3 | NoPin? |
+| GPIO24 | LED24 | I/OPU | IO_MUX_SEL_0, BIT 24 | N19 | 88 |
+| GPIO25 | LED25 | I/OPU | IO_MUX_SEL_0, BIT 25 | P19 | 86 |
+| GPIO26 | LED26 | I/OPU | IO_MUX_SEL_0, BIT 26 | P18 | 84 |
+| GPIO27 | LED27 | I/OPU | IO_MUX_SEL_0, BIT 27 | R19 | 82 |
+| GPIO28 | SYS_LED | I/OPU | IO_MUX_SEL_0, BIT 28 | F1 | 13 |
+| GPIO29 | GLB_RLDP_LED_EN |  | IO_MUX_SEL_0, BIT 29 |  | NoPin? |
+| GPIO30 | ACL_BIT3_EN |  | IO_MUX_SEL_2, BIT 3 | F3 | 11 |
+| GPIO31 | UART TX (OUTPUT) |  | IO_MUX_SEL_1, BIT 0 | L20 | 90 |
+| GPIO32 | UART TX (INPUT) |  | IO_MUX_SEL_1, BIT 1 | L21 |  |
+| GPIO33 | GPIO_INT |  | IO_MUX_SEL_1, BIT 2 |  |  |
+| GPIO34 | MDC0 |  | IO_MUX_SEL_1, BIT 3 |  |  |
+| GPIO35 | MDIO0 |  | IO_MUX_SEL_1, BIT 4 |  |  |
+| GPIO36 | PWM_OUT |  | IO_MUX_SEL_1, BIT 30 | B13 |  |
+| GPIO37 | --- |  |  | L18 |  |
+| GPIO38 | --- |  |  | K19 |  |
+| GPIO39 | MSDA4 |  | IO_MUX_SEL_1, BIT 29 | K20 | 95 |
+| GPIO40 | MDC1/SCL3 |  | IO_MUX_SEL_1, BIT 5 & 6 | J29 |  |
+| GPIO41 | MDIO1/MSDA3 |  | IO_MUX_SEL_1, BIT 5 & 6 | J19 |  |
+| GPIO42 | SPI-MEMORY |  | RTL8373_INI_MODE_ADDR, BIT 0 & 1 | D1 |  |
+| GPIO43 | SPI-MEMORY |  | RTL8373_INI_MODE_ADDR, BIT 0 & 1 | E1 |  |
+| GPIO44 | SPI-MEMORY |  | RTL8373_INI_MODE_ADDR, BIT 0 & 1 | D2 |  |
+| GPIO45 | SPI-MEMORY |  | RTL8373_INI_MODE_ADDR, BIT 0 & 1 | E2 |  |
+| GPIO46 | MSCK0 |  | IO_MUX_SEL_1, BIT 7 & 8 | A2 |  |
+| GPIO47 | MSDA0 |  | IO_MUX_SEL_1, BIT 9 & 10 | B2 |  |
+| GPIO48 | MSCK1 |  | IO_MUX_SEL_1, BIT 11 & 12 | A1 |  |
+| GPIO49 | MSDA1 |  | IO_MUX_SEL_1, BIT 13 & 14 | B1 |  |
+| GPIO50 | MSCL2/U1TXD |  | IO_MUX_SEL_1, BIT 15 & 16 | C1 |  |
+| GPIO51 | MSDA2/U1RXD |  | IO_MUX_SEL_1, BIT 17 & 18 | C2 |  |
+| GPIO52 | ACL_BIT0_EN |  | IO_MUX_SEL_2, BIT 0 |  |  |
+| GPIO53 | ACL_BIT1_EN |  | IO_MUX_SEL_2, BIT 1 |  |  |
+| GPIO54 | ACL_BIT2_EN |  | IO_MUX_SEL_2, BIT 2 | E5 |  |
+| GPIO55 | PTP_CLK125M_IN |  | IO_MUX_SEL_1, BIT 19 |  |  |
+| GPIO56 | PTP_CLK_OUT |  | IO_MUX_SEL_1, BIT 20 |  |  |
+| GPIO57 | PTP_TOD_OUT |  | IO_MUX_SEL_1, BIT 21 |  |  |
+| GPIO58 | PTP_PPS_OUT |  | IO_MUX_SEL_1, BIT 22 |  |  |
+| GPIO59 | PTP_TOD_IN |  | IO_MUX_SEL_1, BIT 23 |  |  |
+| GPIO60 | PTP_PPS_IN |  | IO_MUX_SEL_1, BIT 24 |  |  |
+| GPIO61 | SYNCELOCK0 |  | IO_MUX_SEL_1, BIT 27 |  |  |
+| GPIO62 | SYNCELOCK1 |  | IO_MUX_SEL_1, BIT 28 |  |  |
+| GPIO63 | GPIO_MDIO0 |  | IO_MUX_SEL_1, BIT 4 |  |  |
+
+## I2C
+
+| I2C | Function |Type  | (RTL8372) PIN# | (RTL8372N) PIN# |
+|  ---- | ---- | ---- | ---- | ---- |
+| GPIO47 | SDA0 | I/OPU |  | B1 | 142 |
+| GPIO49 | SDA1 | I/OPU |  | B2 | 144 |
+| GPIO51 | SDA2 | I/OPU |  | C2 | ??? |
+| GPIO41 | SDA3 | I/OPU |  | J20 | 98 |
+| GPIO39 | SDA4 | I/OPU |  | K20 | 95 |
+| GPIO46 | SCL0 | I/OPU |  | A2 | 138 |
+| GPIO48 | SCL1 | I/OPU |  | A1 | 140 |
+| GPIO50 | SCL2 | I/OPU |  | C1 | ??? |
+| GPIO40? | SCL3 | OPU |  | J20 |  |
+
+# Other funcitons
+
+| Function | Type | (RTL8372) PIN# | (RTL8372N) PIN# |
+|  ---- | ---- | ---- | ---- | 
+| nRESET   |      | A6  | 131 |
+| PTP_SYNC |      | B10 | 130 |
+| INT      | OPU  | B6  | 132 |
+
+
+
@@ -0,0 +1,58 @@
+#RTL8272/3 features
+
+The following hardware features of the RTL8372/3 is supported:
+- Clock generation, including different divider settings
+- Interrupt control for timer, serial, external irqs 0, 1
+- Serial console via SFRs
+- Flash operations via SFRs
+- Bank switching via SFRs
+- Access to Switch registers via SFRs
+  - LED setup
+  - Reset
+  - Some switch settings such as MAC configuration
+  - GPIO to detect SFP module insert/removal/RX-LOS (depending on device/module support)
+  - I2C to read SFP EEPROM on 1 and 2 SFP slot devices
+  - NIC setup
+  - L2 learning table access, L2 table flushing
+  - VLAN setup/configuration
+  - Port mirroring
+- Access to PHYs via MDIO (clause 45 via SFR):
+  - Internal PHYs of RTL8372 and RTL8373
+  - RTL8221 (1x2.5GBit port on devices with 5 ports)
+  - RTL8224 (4x2.5GBit ports on devices with 8 ports)
+- SerDes settings of SoC via SFR:
+  - Configure SFPs with 10Gbit/2.5Gbit/1Gbit (Ethernet and Fiber SFP(+) tested)
+  - RTL8221, RTL8224
+- NIC TX and RX of packets via SFRs
+  - send and receive Ethernet frames via SFRs and Switch registers
+  - RTL-tags and VLAN ingress-tag decoding for CPU-port
+
+Ethernet frame RX IRQ via IRQ1 is conceptually understood, but not activated. RX is
+currently done via polling, which allows ping-times of <10ms.
+
+The RTL8372/3 have 256 bytes of internal RAM (INTMEM) accessible through MOV
+instructions, which are used for the stack and important globals. Some of
+these are bit-adressable, e.g. for storing global flags.
+
+Additionally, 64kB of extended RAM (XMEM) is built in, which is accessed
+through the MOVX instruction. It is used for global variables, for most
+of the function argument passing that is not done using the 8 registers
+R0-R7 or registers A/B, and for local variables (which requires extremely
+careful planning). The flash memory is transparently accessible for code
+being executed and can be used to store configuration. Access is done through
+the MOVC instruction, possibly setting the bank register before and
+resetting it to access the entire 4MB space. Code is prefetched from flash
+and cached in a small RAM automatically by the HW.
+
+The peripherial functions are accessed through 2 different mechanisms:
+- Special Function Registers (SFRs, 0x80-0xff) for banking, timers, UART, access to
+  switch registers, MDIO, SPI (flash) and NIC transfers. Some SFRs are not
+  used for HW purposes and can be used as RAM. Some SFRs are bit-adressable,
+  allowing for very tight event wait loops (a single 2-byte instruction).
+- 0x10000 switch registers, which appear to be very similar to the registers
+  of the RTL838x, for which source code and datasheets are available. This
+  controls clock dividers, GPIO/LEDs and general  switch functionality. 
+
+The playground image shows access to the different types of memory using the
+SDCC compiler. Any support of Linux or e.g. Zephyr would require porting gcc.
+There are FreeRTOS ports to 8051 processors using sdcc, however.
@@ -0,0 +1,135 @@
+# IGMP (Internet Group Management Protocol) and MLD (Multicast Listener Discovery)
+IGMP (for IPv4) and MLD (for IPv6) are protocols that control the distribution
+of Layer-3 Multicast packets on the LAN, which otherwise would be flooded across the
+entire network. For this to work, IGMP/MLD messages are sent, in particular
+from MC consumers (e.g. the video-player that plays an IP-Multicast stream), but
+also Multicast-aware routers to control switching of the IP-MC or underlying
+L2-MC packets. The main usage in home networks is IPTV. 
+
+The RTL8372/3 SoC supports managing IPv4-MC using either Destination-IP (the IPv4
+multicast group address)/Source-IP (typically 0.0.0.0) matching or via controlling
+the switching of the underlying L2-MC packets (i.e. packets in 01:00:5e:xx:yy:zz, where
+xx:yy:zz are the LSBs of the IPv4-MC address). The DIP/SIP-based switching is
+not VLAN-aware, meaning a stream will be available in all VLANs if subscribed to.
+This is not a problem in a typical home network, however. The L2-based method
+is VLAN aware, but currently not supported in the software.
+
+Although there is hardware support for IPv6/MLD-based Multicast management (i.e. intelligent
+management by the switch), the current software does not implement managing IPv6 Multicast.
+Instead, all IPv6 Multicast pakets will be flooded to all ports, just as an unmanaged
+switch would do.
+
+The current software support works by trapping IGMP packets (only v3 supported, which
+is used in the vast majority of today's networks) to the CPU of the switch which will
+update the L3 and L2 switching tables to include switch ports in a stream or remove
+them. This trapping to the CPU is also called IGMP snooping. While there is support
+in the HW to handle IGMP/MLD packets (v3 has only limited support) entirely in hardware
+and even send out reports, it is currently not understood
+how this works, and instead IGMP is handled entirely in software, which also allows
+to fully support IGMPv3 packet which are the standard in present-day networks.
+
+## IP-MC control
+The relevant registers for controlling IP-MC switching are:
+```
+#define RTL837X_IPV4_PORT_MC_LM_ACT	0x4f78
+#define RTL837X_IPV6_PORT_MC_LM_ACT	0x4f7c
+#define RTL837X_IGMP_PORT_CFG		0x52a0
+#define IGMP_MAX_GROUP			0x00ff0000
+#define IGMP_PROTOCOL_ENABLE		0x00007c00
+#define IGMP_TRAP			0x0000002a
+#define IGMP_FLOOD			0x00000015
+#define IGMP_ASIC			0x00000000
+#define RTL837X_IGMP_ROUTER_PORT	0x529c
+#define RTL837X_IPV4_UNKN_MC_FLD_PMSK	0x5368
+#define RTL837X_IPV6_UNKN_MC_FLD_PMSK	0x536c
+#define RTL837X_IGMP_TRAP_CFG		0x50bc
+#define IGMP_TRAP_PRIORITY		0x7
+#define IGMP_CPU_PORT			0x00010000
+```
+`RTL837X_IPV4_PORT_MC_LM_ACT/RTL837X_IPV6_PORT_MC_LM_ACT` control the action when an
+IP-MC packet is encountered at a switch port and there is no rule for forwarding in
+the forwarding tables. The default action is to flood such Lookup-Miss packets to all
+ports. This is the configuration without IGMP/MLD enabled.
+
+When IGMP/MLD is turned on, the Lookup-Miss action will be changed to drop such packets
+unless a rule is found in the forwarding tables, which will need to be configured by
+IGMP packets.
+
+Switching on IGMP also configures all ports via `RTL837X_IGMP_PORT_CFG` to trap all
+incoming IGMP packets to the CPU. `RTL837X_IGMP_TRAP_CFG` then is used to configure
+priority and CPU-Port of trapped IGMP/MLD packets. 
+
+Configuration of the IP-MC-forwarding to the listening ports is done by managing the
+forwarding tables of the switch, see [L2 learning](l2.md).
+
+
+## IGMP API
+The code currently provides the following functions:
+```
+void igmp_setup(void) __banked;
+void igmp_enable(void) __banked;
+void igmp_router_port_set(uint16_t pmask) __banked;
+void igmp_packet_handler(void) __banked;
+void igmp_show(void) __banked;
+```c
+`igmp_setup()` is called at boot-time and configures flooding of all IP-MC packets by
+default, as otherwise no IP-MC would be possible in the network.
+
+`igmp_enable()`starts IGMP which cause IGMP packets to be handled by the CPU and forwarding
+of IP-MC packets to be limited to only subscribed ports.
+
+`igmp_router_port_set()`configures forwarding ports for IGMP messages.
+
+`igmp_packet_handler()` implements handling of trapped IGMP packets by the CPU.
+
+`igmp_show()` prints out the IGMP configuration on the CLI.
+
+
+## IGMP configuration on the Serial Console
+For testing the following commands are provided on the serial console:
+```
+> igmp [on/off]
+  Enables or disables IGMP
+
+> igmp show
+  Shows information on IGMP
+```
+
+## LAG configuration via the Web Interface
+Not implemented, yet!
+
+## A Test with IP-MC streaming using vlc
+The following is a simple test verifying the IGMP and IP-MC switching capabilities.
+
+You will need 2 Linux/Windows devices with a GUI plus a switch.
+
+Connect the switch to an MC-aware router (e.g. to your home network). Connect the 2 Linux/Windows
+devices to the switch. The connection to the router makes sure that Linux/Windows will send
+out IGMP messages on the ports connected to the switch, which they will only do if they are aware
+that there is a MC-aware router in the network. Make sure the 2 GUI devices are in the home network
+(e.g. via DHCP).
+
+Start streaming on one of the Linux/Windows machines:
+```
+$ vlc your_video.mp4 --sout="#std{access=udp, mux=ts, dst=239.255.0.1:8090}"
+```
+At this point you should see all switch ports flickering heavily as the MC stream is switched to all
+switch ports, including flooding your home network. If you do not see any packets arriving at the switch,
+you can force the output interface of vlc by using `--miface=<ifname>`
+
+Enable IGMP on the switch-CLI:
+```
+> igmp on
+```
+The flickering should now stop on all ports except the port where the streaming device is connected:
+the switch drops all IP-MC packets as there are no listeners.
+
+Now, on the second Linux/Windows device start listening to the stream:
+```
+$ vlc udp://@239.255.0.1:8090
+```
+You should see the port-led of the port the displaying machine is connected to, to start flickering
+and after some synchronization, the video should start playing.
+
+Stopping vlc should also switching of the IP-MC frames to the listening device, i.e. the port-leds
+should stop flickering.
@@ -32,7 +32,7 @@ cleared by the ASIC. Data then is in the output data registers
 #define RTL837x_L2_DATA_OUT_C	0x5cd4

 DATA_OUT_A   DATA_OUT_B   L2_DATA_OUT_C
-M2 M3 M4 M5  fV VV M0 M1  xx xF xx xg
+M2 M3 M4 M5  fV VV M0 M1  xx xF xx gg

 M0-M5: 6 bytes of MAC, M0 is MSB
 V: 12 bits of VLAN-ID
@@ -41,6 +41,9 @@ f: bit 5 set: Entry is valid, otherwise stale
   bit 7: bit 1 of port-number
 g: bit 0: bit 2 of port-number
   bit 1: bit 3 of port-number (MSB)
+   bit 2: bit 0 of entry-age
+   bit 3: bit 1 of entry-age
+   bit 4: bit 2 of entry-age (MSB)
 F: bit 0: entry is static(1) or learned (0)
 ```
 The next entry can be now found in RTL837x_TBL_DATA_0 (entry = RTL837x_TBL_DATA_0_bits(0-11) + 1),
@@ -0,0 +1,227 @@
+# Link Aggregation (aka Trunking)
+
+The RTL827x allows to combine multiple ports to a single logical link
+(Link Aggregation / Trunking) according to IEEE 802.3ad. LAGs allow to
+combine the individual physical links into a single link with the combined
+throughput and automatic redundancy when one of the link fails.
+Up to 4 Link Aggregation Groups (LAGs) can be defined on the switch devices.
+
+## LAG control
+Four registers `RTL837X_TRK_MBR_CTRL_BASE(lag) (0x4f38-0x4f44)` define the LAG membership
+via a port mask of the logical port numbers.
+
+A hash algorithm applied to L2, L3 and L4 properties of a packet are used to decide which
+of the links (ports) is being used to transfer the packet. The possible properties used in the
+hash are:
+```
+#define LAG_HASH_SOURCE_PORT_NUMBER	0x01
+#define LAG_HASH_L2_SMAC		0x02
+#define LAG_HASH_L2_DMAC		0x04
+#define LAG_HASH_L3_SIP			0x08
+#define LAG_HASH_L3_DIP			0x10
+#define LAG_HASH_L4_SPORT		0x20
+#define LAG_HASH_L4_DPORT		0x40
+#define LAG_HASH_DEFAULT (LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC | LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT | LAG_HASH_L4_DPORT)
+```
+The hash algorithm used to select links (exit ports) is defined for each LAG individually in
+`RTL837X_TRK_HASH_CTRL_BASE (0x4f48-0x4f54)`.
+
+## Trunking API
+The code currently provides the following functions:
+```
+/*
+ * Configure LAGs
+ * Sets the members via port bitmask of a given Link Aggregation Group
+ * The groups have numbers 0-3
+ * The bitmask represents up to 10 ports
+ * If currently no LAG has algorithm used, a default is applied
+ */
+void port_lag_members_set(__xdata uint8_t lag, __xdata uint16_t members) __banked;
+
+/*
+ * Configures the hash algorithm used for a LAG
+ * lag is the Group to configure and hash is a bitmask
+ */
+void port_lag_hash_set(__xdata uint8_t lag, __xdata uint8_t hash_bits) __banked;
+```
+
+## LAG configuration on the Serial Console
+For testing the following commands are provided on the serial console:
+```
+> lag <LAG-ID> [p1] [p2]...
+  Create or set a LAG. Trunk-ID is 1 or 2. Ports are physical ports
+  If only the LAG-ID is given but no members, the LAG is deleted
+
+> lag show
+  Shows information on all 4 lags
+
+> laghash 0 [hash1] [hash2]...
+  Uses the given packet properties when hashing the packet to select the link
+  Names for the hashes are spa, smac, dmac, sip, dip, sport, dport
+```
+When a lag is creates, by default the hash is based on smac, dmac, sip, dip, sport, dport. When you
+use your own hash settings, make sure that the hash always uses both the source and destination
+property of the packet, as otherwise pakets will not be routed symmetrically.
+
+## LAG configuration via the Web Interface
+In the web-interface select Link Aggregation in the left navigation panel. The page will look like this:
+![Alt text](images/LAG_config.png?raw=true "Link Aggregation Web-Page")
+Each of th 4 LAGs is configured separately. After the web-page has loaded, the current configuration
+can be edited by clicking on the port-images to include that port or exclude it from a LAG.
+When pressing on the Create/Update button, the LAG will be automatically created if not yet done, or
+updated. If a lage is updated to not having any members, then it is effectively deleted.
+
+All LAGs are created with the default hash-function (see above). This currently cannot be changed
+from the Web.
+
+## A Test using a single Linux Desktop
+The following is a simple test using 2 RTL 2.5 GBit switches with at least 1 SFP+-port each. You
+will also need 4 10GBit SFP+ modules (DAC or Fiber) and 2 SFP+ ports on your desktop.
+
+The following shows the network configuration
+```
+                                -----------------             -----------------
+    Linux Comuter               |                | 2.5 GBit   |                |         same Linux Computer
+            ----------  10G     |            P1  |------------| P1             |   10G    ----------
+192.168.9.1 |  SFP+  |==========| Switch 1       | 2.5 GBit   |    Switch 2    |==========|  SFP+  | 192.168.9.2
+ enp1s0f0   ----------          |            P2  |------------| P2             |          ----------  enp1s0f1
+                                |                |            |                |
+                                ------------------            -----------------
+```
+
+On _both_ switches create a LAG with ports 1 and 2 inside and the default hash algorithm which takes
+source and destination ports into account, e.g. just use the default:
+```
+> lag 0 1 2
+```
+
+
+The following shows the configuration on the desktop using a dual 10GBit card with 2 SFP+ modules:
+```
+[234690.755634] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver
+[234690.755637] ixgbe: Copyright (c) 1999-2016 Intel Corporation.
+[234690.921614] ixgbe 0000:01:00.0: Multiqueue Enabled: Rx Queue count = 12, Tx Queue count = 12 XDP Queue count = 0
+[234690.921914] ixgbe 0000:01:00.0: 32.000 Gb/s available PCIe bandwidth (5.0 GT/s PCIe x8 link)
+[234690.921999] ixgbe 0000:01:00.0: MAC: 2, PHY: 19, SFP+: 5, PBA No: FFFFFF-0FF
+[234690.922002] ixgbe 0000:01:00.0: 28:41:c6:xx:xx:aa
+[234690.924946] ixgbe 0000:01:00.0: Intel(R) 10 Gigabit Network Connection
+[234690.990024] ixgbe 0000:01:00.0 enp1s0f0: renamed from eth0
+[234691.056447] ixgbe 0000:01:00.0: registered PHC device on enp1s0f0
+[234691.089417] ixgbe 0000:01:00.1: Multiqueue Enabled: Rx Queue count = 12, Tx Queue count = 12 XDP Queue count = 0
+[234691.089706] ixgbe 0000:01:00.1: 32.000 Gb/s available PCIe bandwidth (5.0 GT/s PCIe x8 link)
+[234691.089788] ixgbe 0000:01:00.1: MAC: 2, PHY: 19, SFP+: 18, PBA No: FFFFFF-0FF
+[234691.089790] ixgbe 0000:01:00.1: 28:41:c6:xx:xx:ab
+[234691.160997] ixgbe 0000:01:00.1: Intel(R) 10 Gigabit Network Connection
+[234691.166102] ixgbe 0000:01:00.1 enp1s0f1: renamed from eth0
+[234691.231579] ixgbe 0000:01:00.1: registered PHC device on enp1s0f1
+[234691.236965] ixgbe 0000:01:00.0 enp1s0f0: detected SFP+: 5
+[234691.485031] ixgbe 0000:01:00.0 enp1s0f0: NIC Link is Up 10 Gbps, Flow Control: RX/TX
+[234691.557003] ixgbe 0000:01:00.1 enp1s0f1: detected SFP+: 18
+[234691.753061] ixgbe 0000:01:00.1 enp1s0f1: NIC Link is Up 10 Gbps, Flow Control: RX/TX
+```
+
+Now set up 2 network namespaces and put each interface inside one:
+```
+sudo ip netns add netns_eth0
+sudo ip netns add netns_eth1
+sudo ip link set enp1s0f0 netns netns_eth0
+sudo ip link set enp1s0f1 netns netns_eth1
+```
+
+Configure network interface addresses 192.168.9.2 and 192.168.9.1 in each namespace:
+```
+sudo ip netns exec netns_eth0 ifconfig enp1s0f0 192.168.9.1 netmask 255.255.255.0
+
+sudo ip netns exec netns_eth0 ip a
+1: lo: <LOOPBACK> mtu 65536 qdisc noop state DOWN group default qlen 1000
+    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
+24: enp1s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
+    link/ether 28:41:c6:xx:xx:aa brd ff:ff:ff:ff:ff:ff
+    altname enx2841c6xxxxaa
+    inet 192.168.9.1/24 scope global enp1s0f0
+       valid_lft forever preferred_lft forever
+    inet6 fe80::2a41:c6ff:fexx:xxaa/64 scope link proto kernel_ll
+       valid_lft forever preferred_lft forever
+
+sudo ip netns exec netns_eth1 ifconfig enp1s0f1 192.168.9.2 netmask 255.255.255.0
+
+sudo ip netns exec netns_eth1 ip a
+1: lo: <LOOPBACK> mtu 65536 qdisc noop state DOWN group default qlen 1000
+    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
+25: enp1s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
+    link/ether 28:41:c6:xx:xx:ab brd ff:ff:ff:ff:ff:ff
+    altname enx2841c6xxxxab
+    inet 192.168.9.2/24 scope global enp1s0f1
+       valid_lft forever preferred_lft forever
+    inet6 fe80::2a41:c6ff:fexx:xxab/64 scope link proto kernel_ll
+       valid_lft forever preferred_lft forever
+```
+Test is using ping. On both switches one of the 2.5Gbit links and all 10GBit links should show activity:
+```
+$ sudo ip netns exec netns_eth1 ping 192.168.9.1
+PING 192.168.9.1 (192.168.9.1) 56(84) bytes of data.
+64 bytes from 192.168.9.1: icmp_seq=1 ttl=64 time=0.082 ms
+64 bytes from 192.168.9.1: icmp_seq=2 ttl=64 time=0.130 ms
+^C
+--- 192.168.9.1 ping statistics ---
+2 packets transmitted, 2 received, 0% packet loss, time 1030ms
+rtt min/avg/max/mdev = 0.082/0.106/0.130/0.024 ms
+```
+You can also verify that the redundancy works by unplugging the active link, the ping should continue
+undisturbed with the other link now tranporting the pakets.
+
+In 2 shells, start 2 instances of iperf, listening on 2 different ports. You will need to make sure that
+the hash algorithm assigns different switch ports for the different port numbers. You can check this by
+running the iperf3 client against each server instance and verify that different links show activity:
+```
+sudo ip netns exec netns_eth0 iperf3 -s
+
+sudo ip netns exec netns_eth0 iperf3 -s -p 5333
+```
+
+Now you can run the clients in parallel:
+```
+$ sudo ip netns exec netns_eth1 iperf3 -c 192.168.9.1 & sudo ip netns exec netns_eth1 iperf3 -p 5333 -c 192.168.9.1
+[1] 295484
+Connecting to host 192.168.9.1, port 5201
+[  5] local 192.168.9.2 port 60996 connected to 192.168.9.1 port 5201
+Connecting to host 192.168.9.1, port 5333
+[  5] local 192.168.9.2 port 39660 connected to 192.168.9.1 port 5333
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec   283 MBytes  2.37 Gbits/sec  485    272 KBytes
+[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
+[  5]   0.00-1.00   sec   283 MBytes  2.37 Gbits/sec  479    379 KBytes
+[  5]   1.00-2.00   sec   280 MBytes  2.35 Gbits/sec  444    260 KBytes
+[  5]   1.00-2.00   sec   280 MBytes  2.35 Gbits/sec  578    267 KBytes
+[  5]   2.00-3.00   sec   281 MBytes  2.36 Gbits/sec  385    263 KBytes
+[  5]   2.00-3.00   sec   280 MBytes  2.35 Gbits/sec  373    375 KBytes
+[  5]   3.00-4.00   sec   280 MBytes  2.35 Gbits/sec  430    385 KBytes
+[  5]   3.00-4.00   sec   280 MBytes  2.35 Gbits/sec  452    273 KBytes
+[  5]   4.00-5.00   sec   281 MBytes  2.36 Gbits/sec  319    256 KBytes
+[  5]   4.00-5.00   sec   281 MBytes  2.36 Gbits/sec  425    269 KBytes
+[  5]   5.00-6.00   sec   280 MBytes  2.35 Gbits/sec  364    264 KBytes
+[  5]   5.00-6.00   sec   281 MBytes  2.36 Gbits/sec  561    264 KBytes
+[  5]   6.00-7.00   sec   281 MBytes  2.35 Gbits/sec  446    255 KBytes
+[  5]   6.00-7.00   sec   280 MBytes  2.35 Gbits/sec  582    263 KBytes
+[  5]   7.00-8.00   sec   281 MBytes  2.35 Gbits/sec  494    263 KBytes
+[  5]   7.00-8.00   sec   280 MBytes  2.35 Gbits/sec  539    181 KBytes
+[  5]   8.00-9.00   sec   281 MBytes  2.36 Gbits/sec  617    389 KBytes
+[  5]   8.00-9.00   sec   280 MBytes  2.35 Gbits/sec  490    232 KBytes
+[  5]   9.00-10.00  sec   281 MBytes  2.35 Gbits/sec  363    215 KBytes
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec  2.74 GBytes  2.36 Gbits/sec  4347            sender
+[  5]   0.00-10.00  sec  2.74 GBytes  2.35 Gbits/sec                  receiver
+
+iperf Done.
+[  5]   9.00-10.00  sec   282 MBytes  2.36 Gbits/sec  536    380 KBytes
+- - - - - - - - - - - - - - - - - - - - - - - - -
+[ ID] Interval           Transfer     Bitrate         Retr
+[  5]   0.00-10.00  sec  2.74 GBytes  2.36 Gbits/sec  5015            sender
+[  5]   0.00-10.00  sec  2.74 GBytes  2.35 Gbits/sec                  receiver
+
+iperf Done.
+[1]+  Done                    sudo ip netns exec netns_eth1 iperf3 -c 192.168.9.1
+```
+As you can see, the total throughput was 4.71 GBit/sec which is close to the
+maximum possible with a single 5GBit link.
@@ -0,0 +1,48 @@
+# Modifications
+
+## SPI-Flash Memory
+
+SPI-Flash memory can be replaced with an other type. Because the chip is defect, like #69 & #70 or you have an unmanaged-switch with a small flash size, and want to convert it to a managed-variant to run `RTLPlayground` software on it. Currently `RTLPlayground`-firmware expects `8 MBit / 1 MiB`.
+
+### Size
+
+The SOC (RTL837x network chip) used 24-bit address to access the device. This means that in theory, a memory size up to `2^24 x 8-bit = 16777216 x 8-bit = 128 MBit or 16 MiB` could be used, this is *untested*!
+
+### Speed
+
+The SOC (RTL837x network chip) is connected via an SPI-BUS to the flash memory. SPI-BUS frequency is `62.5 MHz`.
+Look in the datasheet for `AC Electrical Characteristics` and lookup symbol `Fr`. Maximum value should be equal or higher than `62.5 MHz`.
+A device that supports the highest possible clock speed is not a better device, nor is the SOC going to run faster. So pick one which have common frequency between `80 MHz` to `133 MHz`.
+Memory speed is dictated by the SPI-BUS clock frequency which is `62.5 MHz`.
+
+### SPI Operation
+
+By default, SPI-BUS uses `CLK`, `CS`, `DI` and `DO`. To increase the data throughput without increasing the bus frequency, a single command can run in `DUAL SPI operation`. This means that for a specific command `DI` and `DO` are both used to transfer the data to/from the device. So it makes the data transfer up-to twice as fast. Although the SOC datasheet doesn’t mention it, our software is making use of this mode.
+
+### Package
+
+Most use package are `SO8`-type may also called `SOIC8`-type. Which can also have different width. Like `150-mil`, `208-mil` or `300-mil`. Best to measure what you need and confirm the measurement with the device-datasheet.
+
+### Specification
+
+1. Size: At least `8 MBit / 1 MiB` (theoretic max. `128 MBit / 16 MiB`, but is not *tested*!)
+2. Speed: `62.5 MHz` or better.
+3. Support for `DUAL SPI operation`.
+   Device need support for command `BBh`, `Dual I/O Fast Read` or `Fast Read Dual I/O`.
+
+### Known Working
+
+This list is incomplete.
+
+| Brand      | Partnumber |
+| ---------- |----------- |
+| GigaDevice | GD25Q32E   |
+| Winbond    | W25Q16JV   |
+| Winbond    | W25Q32FV   |
+| Winbond    | W25Q32JV   |
+| Winbond    | W25Q16JL   |
+| Winbond    | W25Q16DV   |
+| Winbond    | W25Q80DV   |
+| Fundan     | FM25Q16A   |
+
+*NOTE*: Part numbers are incomplete. Part numbers may contain additional information such as package, temperature specifications, and even the number of devices on a reel. So always check the datasheet so that you have the right orderable partnumber.
@@ -0,0 +1,27 @@
+# Supported Hardware
+The following devices have been tested and are fully working:
+- Horaco ZX_SG4T2
+- keepLINK kp-9000-6hx-x2 (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
+- keepLINK KP-9000-6XHML-X2, same as above, but Managed
+- keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+)
+- keepLINK kp-9000-9xh-x-eu (1 x RTL8373 + RTL8224: 8x 2.5GBit + 1x 10GBit SFP+)
+- Lianguo LG-SWTGW218AS (RTL8373 + RTL8224 PHY: 8x 2.5GBit + 1x 10GBit SFP+)
+- No-Name ZX-SWTGW215AS, managed version of kp-9000-6hx-x, ordered on
+  AliExpress as keepLINK 5+1 port managed
+- TrendNet TEG-S562 (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
+- FNS-1200P (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
+
+Other device based on RTL8272/3 that may work are described here: [Up-N-Atoms 2.5 GBit RTL Switch hacking guide]
+(https://github.com/up-n-atom/SWTG118AS)
+
+Many of the RTL8272/3 devices come in versions with PoE support. The RTLPlayground usually also
+works on these, however, no support for configuring PoE is provided, simply because these
+devices usually just provide PoE on all ports without further configuration possibilitites.
+
+The following forum also discusses this type of switches: [ServeTheHome](https://forums.servethehome.com/index.php?threads/horaco-2-5gbe-managed-switch-8-x-2-5gbe-1-10gb-sfp.41571/)
+
+There are also 16-port unmanaged devices with RTL8272 SoCs, however these devices do not have
+serial consoles and use 4 independent RTL8272 SoCs. No central control is provided by RTLPlayground,
+even if it has been successfully demonstrated to install RTLPlayground to individual SoCs.
+- [GigaPlus GP-S25-1602](https://www.servethehome.com/gigaplus-gp-s25-1602-review-a-cheap-16-port-2-5gbe-and-2-port-10g-switch/)
+- [Vimin VM S251602P 16 Port 2.5G PoE Switch With 2x 10G SFP+](https://www.servethehome.com/vimin-vm-s251602p-16-port-2-5g-poe-switch-review-cyperf/vimin-vm-s251602p-16-port-2-5g-poe-switch-with-2x-10g-sfp-battery-2/)
@@ -1,25 +0,0 @@
-# Trunking
-
-The RTL827x allows to combine multiple ports to a single logical port
-(trunking). Up to 2 trunk groups can be defined.
-
-## Trunking control
-Two registers RTL837x_TRUNK_CTRL_A (0x4f38) and RTL837x_TRUNK_CTRL_B (0x4f3c)
-define the trunk groups. Each holds a bitmap of ports making up the trunk
-group.  
-
-## Trunking API
-The code currently provides the following functions:
-```
-void trunk_set(uint8_t group, uint16_t mask) __banked
-```
-
-# VLAN configuration on the Serial Console
-For testing the following commands are provided on the serial console:
-```
-trunk <TRUNK-ID> [p1] [p2]...
-  create or set a trunk group. Trunk-ID is 1 or 2. ports a physical ports
-
-trunk <VLAN-ID> d
-  deletes the trunk group
-```
@@ -33,15 +33,23 @@ An entry is deleted by adding an invalid entry (00 instead of 0x02 in
 RTL837x_TBL_DATA_IN_A).

 A port is assigned a PVID by setting the PVID-bits of the corresponding
-register of the port. 2 ports share a register. One port uses the higher
-16 bits, the other (even ports) use the lower. The base register is
+register of the port. 2 ports share a register. An odd port uses bits [23:12],
+an even port uses bits [11:0].  The base register is
 RTL837x_PVID_BASE_REG (0x4e1c) and the registers go to 0x4e2c so that also
 the CPU-Port may have a PVID.

-Register RTL837x_REG_INGRESS (0x4e10) allows to define the iingress rules of
+Register RTL837x_REG_INGRESS (0x4e10) allows to define the ingress rules of
 a port. 2 bits define a rule and bits 0-19 are being used. A value of 00
 defines no filtering, 01 (0x01) allows only tagged packets, while 10 (0x02)
-allows only untagged packets to enter a port. The default PVID is 1.
+allows only untagged packets to enter a port.
+
+Register RTL837X_VLAN_PORT_IGR_FLTR (0x4e18) enables or disables ingres VLAN
+filtering, each bit corresponds to given port (port0 -> bit0, port9 -> bit9).
+When enabled, incomming package's vlan tag is checked against VLAN membership
+on given port. When package contains VLAN not in member list, package is dropped.
+
+The default PVID on all port is 1, ingress VLAN filtering is enabled and all types of
+frames are accepted on input on all ports.

 By default, the ports transmit Ethernet frames with Realtek's proprietary
 tag format. By setting bit 6 (0x40) of the respective port configuration
@@ -51,7 +59,9 @@ registers 0x1238, 0x1338, ...
 The code currently provides the following functions:
 ```
 void port_pvid_set(uint8_t port, __xdata uint16_t pvid) __banked;
-void vlan_create(uint16_t vlan, uint16_t members, uint16_t tagged) __banked;
+uint16_t port_pvid_get(uint8_t port) __banked;
+void vlan_create(void) __banked;   // reads from global vlan_settings
+int8_t vlan_get(register uint16_t vlan) __banked;  // returns data in sfr_data
 void vlan_delete(uint16_t vlan) __banked;

 ```
@@ -66,9 +76,26 @@ vlan <VLAN-ID> p[t/u]...
 vlan <VLAN-ID> d
  deletes the VLAN

+vlan show
+  Dumps the current ingress vlan settings.
+
+vlan <VLAN-ID> mgmt
+  Restricts network access to the switch (web UI, syslog) to the given
+  VLAN. Use `vlan 0 mgmt` to disable the filter. Default is `vlan 1 mgmt`.
+  Warning: setting this to an unreachable VLAN locks out the web UI;
+  recovery requires serial console.
+
 pvid <port> <VLAN-ID>
  assigns PVID to a port. ports are numbered as on the casing

-ingress <port> [tagged|untagged|all]
-  Allows ingress only for the named packages at the given port
+ingress [p]<t|u|a>...
+  Allows ingress packages on port `p` only when `t`agged, `u`ntagged or `a`ny.
+  Multiple ports can be given at once as in vlan. When `p` is missing, all ports
+  are assigned the same mode. CPU port can not be changed.
+
+  Use `vlan show` to see current configuration.
+
+  Example:
+  `ingress 1t 2a` -> Set port 1 as tagged input only, set port 2 accepting any frames.
+  `ingress a` -> Set all ports to accept both tagged and untagged frames (default behaviour).
 ```
@@ -0,0 +1,20 @@
+<!DOCTYPE html>
+<html>
+  <script src="/main.js"></script>
+  <link rel="stylesheet" href="style.css">
+  <title>Ingress and Egress Bandwidth</title>
+  </head>
+  <body>
+    <nav id="sidebar"></nav>
+    <div style="margin-left:16%;padding:1px 16px;height:1000px;">
+    <div id="ports"></div>
+    <h1>Ingress and Egress Bandwidth</h1>
+    <table id="bwtable">
+      <tr> <th> </th> <th colspan="3"> Ingress </th> <th colspan="2">Egress</th>  <th></th></tr>
+      <tr> <th>Port</th> <th>Limit</th> <th>Bandwidth [kBit/s]</th> <th>Flow Control</th> <th>Limit</th> <th>Bandwidth [kBit/s]</th> <th>Apply</th></tr>
+    </table>
+    <script src="/bandwidth.js"></script>
+    </div>
+    <script src="/navigation.js"></script>
+  </body>
+</html>
@@ -0,0 +1,138 @@
+const iLayout = '" type="number" maxlength="10" size="10"  onfocus="inputFocus(';
+function createBW() {
+  var tbl = document.getElementById('bwtable');
+  const limit = '<input type="checkbox" id="limit_port" onchange="exec();">'
+  if (tbl.rows.length <= 2  && numPorts) {
+     console.log("CREATING TABLE ", tbl.rows.length);
+     for (let i = 2; i < 2 + numPorts; i++) {
+       const tr = tbl.insertRow();
+       let td = tr.insertCell(); td.appendChild(document.createTextNode(`Port ${i-1}`));
+       td = tr.insertCell();
+       td.innerHTML = limit.replaceAll("limit_port", "ilimit_port_" + i).replace("exec()", "iClicked(" + i + ")");
+       td = tr.insertCell();
+       td.innerHTML = 'UNLIMITED';
+       td = tr.insertCell();
+       td.innerHTML = limit.replaceAll("limit_port", "fc_port_" + i).replace("exec()", "document.getElementById('bwapply_" + i + "').disabled=false;");
+       td = tr.insertCell();
+       td.innerHTML = limit.replaceAll("limit_port", "elimit_port_" + i).replace("exec()", "eClicked(" + i + ")");
+       td = tr.insertCell();
+       td.innerHTML = 'UNLIMITED';
+       var button = '<button type="button" id="bwapply_' + i + '" style="margin: 0 0 0 24px" onclick="applyBandwidth(' + i + ');">Apply</button>';
+       td = tr.insertCell();
+       td.innerHTML = button;
+       document.getElementById("bwapply_" + i).disabled = true;
+    }
+  }
+}
+
+function iClicked(i)
+{
+  document.getElementById("bwapply_" + i).disabled=false;
+  var tbl = document.getElementById('bwtable');
+  var tr = tbl.rows[i];
+  if (!document.getElementById("ilimit_port_" + i).checked) {
+    tr.cells[2].innerHTML = "UNLIMITED";
+    document.getElementById("fc_port_" + i).disabled = true;
+    document.getElementById("fc_port_" + i).checked = true;
+  } else {
+    tr.cells[2].innerHTML = '<input id="ibw_' + i + iLayout + i + ')" value="0"/>';
+    document.getElementById("fc_port_" + i).disabled = false;
+    document.getElementById("fc_port_" + i).checked = true;
+  }
+}
+
+function eClicked(i)
+{
+  document.getElementById("bwapply_" + i).disabled=false;
+  var tbl = document.getElementById('bwtable');
+  var tr = tbl.rows[i];
+  if (!document.getElementById("elimit_port_" + i).checked) {
+    tr.cells[5].innerHTML = "UNLIMITED";
+  } else {
+    tr.cells[5].innerHTML = '<input id="ebw_' + i + iLayout + i + ')" value="0"/>';
+  }
+}
+
+function inputFocus(i)
+{
+    document.getElementById("bwapply_" + i).disabled=false;
+}
+
+async function doCMD(cmd)
+{
+  console.log("Sending >" + cmd + "<");
+  try {
+    const response = await fetch('/cmd', {
+      method: 'POST',
+      body: cmd
+    });
+    console.log('Completed!', response);
+  } catch(err) {
+    console.error(`Error: ${err}`);
+  }
+}
+
+async function applyBandwidth(i) {
+  var tbl = document.getElementById('bwtable');
+  var tr = tbl.rows[i];
+  var cmd = "bw in " + (i-1) + " off";
+  if (document.getElementById("ilimit_port_" + i).checked)
+    cmd = 'bw in ' + (i-1) + ' ' + parseInt(document.getElementById("ibw_" + i).value).toString(16).padStart(4, "0");;
+  doCMD(cmd);
+  if (document.getElementById("ilimit_port_" + i).checked) {
+    if (!document.getElementById("fc_port_" + i).checked)
+      cmd = "bw in " + (i-1) + " drop";
+    doCMD(cmd);
+  }
+  var cmd = "bw out " + (i-1) + " off";
+  if (document.getElementById("elimit_port_" + i).checked)
+    cmd = 'bw out ' + (i-1) + ' ' + parseInt(document.getElementById("ebw_" + i).value).toString(16).padStart(4, "0");;
+  doCMD(cmd);
+}
+
+function getBW() {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    console.log("IN getBW ");
+    if (this.readyState == 4 && this.status == 200) {
+      const s = JSON.parse(xhttp.responseText);
+      console.log("BW: ", JSON.stringify(s));
+      var tbl = document.getElementById('bwtable');
+      if (tbl.rows.length > 2 && numPorts) {
+        for (let i = 2; i < 2 + numPorts; i++) {
+          p = s[i-2];
+          let n = p.portNum;
+          let tr = tbl.rows[n+1];
+          if (!document.getElementById("bwapply_" + (n+1)).disabled)
+            continue;
+          console.log("Table Update row: " + i + " portNum is " + n + ", pState is " + pState[i-2] + ", row number is " + (n+1));
+          let iBW = parseInt(p.iBW,16) * 16; let eBW = parseInt(p.eBW,16) * 16;
+          document.getElementById("ilimit_port_" + (n+1)).checked = p.iLimited;
+          document.getElementById("elimit_port_" + (n+1)).checked = p.eLimited;
+          if (!p.iLimited) {
+            tr.cells[2].innerHTML = "UNLIMITED";
+          } else {
+            tr.cells[2].innerHTML = '<input id="ibw_' + (n+1) + iLayout + (n+1) + ')" value="' + iBW +'"/>';
+          }
+          if (!p.eLimited) {
+            tr.cells[5].innerHTML = "UNLIMITED";
+          } else {
+            tr.cells[5].innerHTML = '<input id="ebw_' + (n+1) + iLayout + (n+1) + ')" value="' + eBW +'"/>';
+          }
+          document.getElementById("fc_port_" + (n+1)).checked = p.iFC==1?true:false;
+          document.getElementById("fc_port_" + (n+1)).disabled = p.iLimited==1?false:true;
+        }
+      }
+    }
+  };
+  xhttp.open("GET", "/bandwidth.json", true);
+  xhttp.timeout = 1500; sendXHTTP(xhttp);
+}
+
+window.addEventListener("load", function() {
+  update( () => {
+    createBW();
+    getBW();
+    const interval = setInterval(update, 2000);
+  });
+});
@@ -0,0 +1,105 @@
+var configInterval = Number();
+var configuration = [];
+const conf_cmds = [
+  /^ip\s+(\d{1,3}\.){3}\d{1,3}$/,
+  /^ip\s+dhcp$/,
+  /^gw\s+(\d{1,3}\.){3}\d{1,3}$/,
+  /^netmask\s+(\d{1,3}\.){3}\d{1,3}$/,
+  /^syslog\s+(on|off)$/,
+  /^syslog\s+ip\s+(\d{1,3}\.){3}\d{1,3}$/,
+  /^passwd\s+\S+$/,
+  /^vlan\s+\d{1,4}\s+d$/,
+  /^vlan\s+\d{1,4}\s+mgmt$/,
+  /^vlan\s+\d{1,4}(\s+[a-zA-Z]\w*)?(\s+\d{1,2}[tu]?)+$/,
+  /^pvid\s+\d{1,2}\s+\d{1,4}$/,
+  /^ingress(\s+\d{1,2}[tua])+$/,
+  /^ingress\s+[tua]$/,
+  /^port\s+\d{1,2}\s+name\s+\S+$/,
+  /^eee(\s+\d{1,2})?\s+(on|off)$/,
+  /^mirror(\s+\d{1,2})(\s+\d{1,2}[tr]?)+$/,
+  /^lag\s+\d(\s+\d{1,2})+$/,
+  /^laghash\s+\d(\s+\w+)+$/,
+  /^isolate\s+\d{1,2}(\s+(off|\d{1,2}))+$/,
+  /^stp\s+(on|off)$/,
+  /^igmp\s+(on|off)$/,
+  /^mtu\s+\d{1,2}\s+\d+$/,
+  /^bw\s+(in|out)\s+\d{1,2}\s+\S+$/,
+];
+const conf_overwrite = [
+  /^ip\b/,
+  /^gw\b/,
+  /^netmask\b/,
+  /^syslog\s+ip\b/,
+  /^syslog\b/,
+  /^passwd\b/,
+  /^vlan\s+\d{1,4}\s+mgmt$/,
+  /^vlan\s+\d{1,4}(?!\s+mgmt\b)/,
+  /^pvid\s+\d{1,2}\b/,
+  /^ingress\b/,
+  /^port\s+\d{1,2}\s+name\b/,
+  /^eee\s+\d{1,2}\b/,
+  /^eee\b/,
+  /^mirror\b/,
+  /^lag\s+\d+\b/,
+  /^laghash\b/,
+  /^isolate\s+\d{1,2}\b/,
+  /^stp\b/,
+  /^igmp\b/,
+  /^mtu\s+\d{1,2}\b/,
+  /^bw\s+(in|out)\s+\d{1,2}\b/,
+];
+
+function parseConf(s){
+  var a = s.split(/\r\n|\n/);
+  for (var l = 0; l < a.length; l++) {
+    var line = a[l].trim().replace(/\s+/g, ' ');
+    if (!line.length) continue;
+    const deleteMatch = line.match(/^vlan\s+(\d{1,4})\s+d$/);
+    if (deleteMatch) {
+      const prefix = "vlan " + deleteMatch[1] + " ";
+      configuration = configuration.filter(c =>
+        c !== "vlan " + deleteMatch[1] && !c.startsWith(prefix));
+      continue;
+    }
+    console.log(l + ' --> ' + line);
+    var ignore = true;
+    for (const x of conf_cmds)
+      if (x.test(line)) { ignore = false; break; }
+    if (ignore) continue;
+    for (const x of conf_overwrite) {
+      if (x.test(line)) {
+        let m = line.match(x);
+        let matchStr = m[0];
+        configuration = configuration.filter(item =>
+          !(item === matchStr || item.startsWith(matchStr + " ")));
+        break;
+      }
+    }
+    configuration.push(line);
+  }
+  console.log("Configuration now:");
+  for (const x of configuration) { console.log(x); }
+}
+
+async function fetchConfig() {
+  try {
+    const response = await fetch('/config');
+    console.log("CONFIG: ", response);
+    const t = await response.text();
+    return t;
+  } catch(err) {
+    console.error("Error: ", err);
+  }
+}
+
+async function fetchCmdLog() {
+  try {
+    const response = await fetch('/cmd_log');
+    console.log("CMD-Log: ", response);
+    const t = await response.text();
+    return t;
+  } catch(err) {
+    console.error("Error: ", err);
+    return "";
+  }
+}
@@ -0,0 +1,25 @@
+<!DOCTYPE html>
+<html>
+  <script src="/main.js"></script>
+  <link rel="stylesheet" href="style.css">
+  <title>EEE Configuration</title>
+  </head>
+  <body>
+    <nav id="sidebar"></nav>
+    <div style="margin-left:16%;padding:1px 16px;height:1000px;">
+    <div id="ports"></div>
+    <h1>EEE Status</h1>
+    <table id="eeetable">
+      <tr> <th> </th> <th colspan="3"> Advertising </th> <th colspan="3">Link-Partner advertises</th>  <th></th></tr>
+      <tr> <th>Port</th> <th>2.5G</th> <th>1G</th> <th>100M</th> <th>2.5G</th> <th>1G</th> <th>100M</th>  <th>Active?</th></tr>
+    </table>
+    <div>
+      <input style="width:20%;" class="action" id="eee_enable" onclick="eeeSub(0, 1);" type="button" value="Enable EEE">
+      <input style="width:20%;" class="action" id="eee_enable" onclick="eeeSub(0, 0);" type="button" value="Disable EEE">
+    </div>
+    <script src="/eee.js"></script>
+    <script src="/eee_sub.js"></script>
+    </div>
+    <script src="/navigation.js"></script>
+  </body>
+</html>
@@ -0,0 +1,52 @@
+function createEEE() {
+  var tbl = document.getElementById('eeetable');
+   if (tbl.rows.length <= 2  && numPorts) {
+     console.log("CREATING TABLE ", tbl.rows.length);
+     for (let i = 2; i < 2 + numPorts; i++) {
+      console.log("Table row: " + i + "pState: " + pState[i-2]);
+      const tr = tbl.insertRow();
+      let td = tr.insertCell(); td.appendChild(document.createTextNode(`Port ${i-1}`));
+      for (let j = 0; j < 7; j++) {
+        td = tr.insertCell(); td.appendChild(document.createTextNode(" "));
+      }
+    }
+  }
+}
+
+function getEEE() {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    if (this.readyState == 4 && this.status == 200) {
+      const s = JSON.parse(xhttp.responseText);
+      console.log("EEE: ", JSON.stringify(s));
+      var tbl = document.getElementById('eeetable');
+      if (tbl.rows.length > 2 && numPorts) {
+        for (let i = 2; i < 2 + numPorts; i++) {
+          p = s[i-2];
+          let n = p.portNum;
+          console.log("Table Update row: " + i + " portNum is " + n + ", pState is " + pState[i-2]);
+          let tr = tbl.rows[n+1];
+          if (!p.isSFP) {
+            let eee = parseInt(p.eee,2); let lp = parseInt(p.eee_lp,2);
+            tr.cells[1].innerHTML = `${eee&4?"ON":"OFF"}`; tr.cells[2].innerHTML = `${eee&2?"ON":"OFF"}`; tr.cells[3].innerHTML = `${eee&1?"ON":"OFF"}`;
+            tr.cells[4].innerHTML = `${lp&4?"ON":"OFF"}`; tr.cells[5].innerHTML = `${lp&2?"ON":"OFF"}`; tr.cells[6].innerHTML = `${lp&1?"ON":"OFF"}`;
+            tr.cells[7].innerHTML = `${p.active}`;
+            tr.classList.toggle('disabled', pState[i-2] < 0); tr.classList.toggle('isNOK', !p.active); tr.classList.toggle('isOK', p.active);
+          }
+          tr.classList.toggle('isSFP', p.isSFP);
+        }
+      }
+    }
+  };
+  xhttp.open("GET", "/eee.json", true);
+  xhttp.timeout = 1500; sendXHTTP(xhttp);
+}
+
+window.addEventListener("load", function() {
+  update( () => {
+    createEEE();
+    getEEE();
+    const interval = setInterval(update, 2000);
+    const iCount = setInterval(getEEE, 2000);
+  });
+});
@@ -0,0 +1,18 @@
+async function eeeSub(port, enable) {
+  var cmd = "eee ";
+  if (enable)
+    cmd = cmd + "on";
+  else
+    cmd = cmd + "off";
+  console.log("eeeSub port " + port, ", value " + enable);
+  try {
+    const response = await fetch('/cmd', {
+      method: 'POST',
+      body: cmd
+    });
+    console.log('Completed!', response);
+  } catch(err) {
+    console.error(`Error: ${err}`);
+  }
+}
+
@@ -1,16 +1,31 @@
 <!DOCTYPE html>
 <html>
-  <head>
-    <title>FreeSwitchOS Main Page</title>
-  </head>
-  <body>
-    <div id="ports"> <img id="port1" width="40" height="40" src="port.svg"/> <img id="port2" width="40" height="40" src="port.svg"/>
-      <img id="port3" width="40" height="40" src="port.svg"/> <img id="port4" width="40" height="40" src="port.svg"/> <img id="sfp1" width="60" height="60" src="sfp.svg"/>
-      <img id="sfp2" width="60" height="60" src="sfp.svg"/> </div>
+  <script src="/main.js"></script>
+  <script src="/main_info.js"></script>
+  <script>
+  window.addEventListener("load", function() {
+    update( () => {
+      const interval = setInterval(update, 2000);
+    });
+  });
+  </script>
+  <link rel="stylesheet" href="style.css">
+  <title>FreeSwitchOS Main Page</title>
+</head>
+
+<body>
+  <nav id="sidebar"></nav>
+  <div style="margin-left:16%;padding:1px 16px;height:1000px;">
+    <div id="ports"></div>
    <h1>Switch Configuration</h1>
-    <table>
-      <tr> <th>Setting</th> <th></th> </tr>
-      #{html_index}
+    <table id="infoTable">
+      <tr>
+        <th colspan="2">Settings</th>
+      </tr>
+      <tbody>
+      </tbody>
    </table>
-  </body>
+  </div>
+  <script src="/navigation.js"></script>
+</body>
 </html>
@@ -0,0 +1,19 @@
+<!DOCTYPE html>
+<html>
+  <script src="/main.js"></script>
+  <link rel="stylesheet" href="style.css">
+  <title>FreeSwitchOS L2 Configuration</title>
+  </head>
+  <body>
+    <nav id="sidebar"></nav>
+    <div style="margin-left:16%;padding:1px 16px;height:1000px;">
+    <div id="ports"></div>
+    <h1>L2 Configuration</h1>
+    <table id="l2table">
+      <tr> <th>Port</th> <th>MAC</th> <th>VLAN</th> <th>Type</th> <th>Remove Entry</th></tr>
+      <script src="/l2.js"></script>
+    </table>
+    </div>
+  </body>
+  <script src="/navigation.js"></script>
+</html>
@@ -0,0 +1,143 @@
+var l2GetInterval;
+var l2Entries = [];
+var l2CurrentEntry = 0;
+
+function fillStats() {
+  var tbl = document.getElementById('statstable');
+  if (!numPorts)
+    return;
+  if (tbl.rows.length > 1) {
+    for (let i = 0; i < numPorts; i++) {
+      console.log("Table Update row: " + i + " state " + pState[i] + " is " + linkS[pState[i] +1]);
+      tbl.rows[i+1].cells[1].innerHTML = `${linkS[pState[i]+1]}`;
+      tbl.rows[i+1].cells[2].innerHTML = `${txG[i]} pkts`;
+      tbl.rows[i+1].cells[3].innerHTML = `${txB[i]} pkts`;
+      tbl.rows[i+1].cells[4].innerHTML = `${rxG[i]} pkts`;
+      tbl.rows[i+1].cells[5].innerHTML = `${rxB[i]} pkts`;
+    }
+  } else {
+    for (let i = 0; i < numPorts; i++) {
+      console.log("Table row: " + i);
+      const tr = tbl.insertRow();
+      let td = tr.insertCell(); td.appendChild(document.createTextNode(`Port ${i+1}`));
+      td = tr.insertCell(); td.appendChild(document.createTextNode(`${linkS[pState[i]+1]}`));
+      td = tr.insertCell(); td.appendChild(document.createTextNode(`${txG[i]} pkts`));
+      td = tr.insertCell();td.appendChild(document.createTextNode(`${txB[i]} pkts`));
+      td = tr.insertCell();td.appendChild(document.createTextNode(`${rxG[i]} pkts`));
+      td = tr.insertCell();td.appendChild(document.createTextNode(`${rxB[i]} pkts`));
+    }
+  }
+}
+
+function l2CMP(a, b)
+{
+  if (a.port < b.port)
+    return -1;
+  if (a.port > b.port)
+    return 1;
+  if (a.mac < b.mac)
+    return -1;
+  if (a.mac > b.mac)
+    return 1;
+  if (a.vlan < b.vlan)
+    return -1;
+  if (a.vlan > b.vlan)
+    return 1;
+  return 0;
+}
+
+function uniq(a) {
+    return a.filter(function(item, pos, ary) {
+        return !pos || item.idx != ary[pos - 1].idx;
+    });
+}
+
+function delL2(idx) {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    if (this.readyState == 4 && this.status == 200) {
+      var s = JSON.parse(xhttp.responseText);
+      console.log("Entry deletion result: ", s.result);
+    }
+  };
+  xhttp.open("GET", "/l2_del.json?idx=" + idx, true);
+  xhttp.timeout = 1500; xhttp.send();
+}
+
+function fillL2(s)
+{
+  var tbl = document.getElementById('l2table');
+  if (!s.length)
+    return;
+  s.sort(l2CMP);
+  s = uniq(s);
+  var s = s.map(function(e) { e.port = e.port != 9 ? e.port : "CPU"; return e; });
+  console.log("L2: ", JSON.stringify(s));
+  for (let i = 0; i < s.length; i++) {
+    var e = s[i];
+    console.log(i, e);
+    if (tbl.rows[i+1]) {
+      tbl.rows[i+1].cells[0].innerHTML = `${e.port}`;
+      tbl.rows[i+1].cells[1].innerHTML = `${e.mac}`;
+      tbl.rows[i+1].cells[2].innerHTML = `${e.vlan}`;
+      tbl.rows[i+1].cells[4].innerHTML = '<button type="button" onclick="delL2(' + e.idx + ');">Delete</button>';
+    } else {
+      const tr = tbl.insertRow();
+      let td = tr.insertCell(); td.innerHTML = `${e.port}`;
+      td = tr.insertCell(); td.innerHTML = `${e.mac}`;
+      td = tr.insertCell(); td.innerHTML = `${e.vlan}`;
+      td = tr.insertCell(); td.innerHTML = `${e.type}`;
+      td = tr.insertCell(); td.innerHTML = '<button type="button" onclick="delL2(' + e.idx + ');">Delete</button>';
+    }
+  }
+  for (let i = tbl.rows.length - 1; i > s.length; i--)
+    tbl.deleteRow(i);
+  l2Entries = [];
+}
+
+function getL2() {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    if (this.readyState == 4 && this.status == 200) {
+      var s = JSON.parse(xhttp.responseText);
+      var s = s.map(function(e) { 
+        e.vlan = parseInt(e.vlan, 16);
+        e.idx = parseInt(e.idx, 16);
+        e.type = e.type == "s" ? "static" : "learned";
+        e.port = e.port == 9 ? 9 : logToPhysPort[e.port];
+      return e;
+    });
+      l2Entries.push(...s);
+      if (l2Entries >= 4096) {
+        l2Entries = [];
+        l2CurrentEntry = 0;
+        clearInterval(l2GetInterval);
+        return;
+      }
+      var w = 0;
+      for (var i = l2Entries.length-1; i > 0; i--) {
+        if (l2Entries[0].idx == l2Entries[i].idx) {
+          w = 1;
+          break;
+        }
+      }
+      if (w) {
+        l2CurrentEntry = 0; 
+        fillL2(l2Entries);
+      } else {
+        l2CurrentEntry = s[s.length-1].idx + 1;
+      }
+    }
+  };
+  xhttp.open("GET", "/l2.json?idx=" + l2CurrentEntry, true);
+  xhttp.timeout = 1500; sendXHTTP(xhttp);
+}
+
+window.addEventListener("load", function() {
+  update( () => {
+    getL2();
+    const interval = setInterval(update, 2000);
+    l2GetInterval = setInterval(getL2, 1000);
+  });;
+});
+
@@ -0,0 +1,27 @@
+<!DOCTYPE html>
+<html>
+  <script src="/main.js"></script>
+  <link rel="stylesheet" href="style.css">
+  <title>Link Aggregation Configuration</title>
+  </head>
+  <body>
+    <nav id="sidebar"></nav>
+    <div style="margin-left:16%;padding:1px 16px;height:1000px;">
+    <div id="ports"></div>
+    <h1>Link Aggregation Groups Configuration</h1>
+    <h2>LAG 1 <input style="width:15%;margin-left: 3em;" class="action" id="l_sub0" onclick="lagSub(0);" type="button" value="Update / Create"></h2>
+    <div id="mLAG0"></div>
+    <br />
+    <h2>LAG 2 <input style="width:15%;margin-left: 3em;" class="action" id="l_sub1" onclick="lagSub(1);" type="button" value="Update / Create"></h2>
+    <div id="mLAG1"></div>
+    <br />
+    <h2>LAG 3 <input style="width:15%;margin-left: 3em;" class="action" id="l_sub2" onclick="lagSub(2);" type="button" value="Update / Create"></h2>
+    <div id="mLAG2"></div>
+    <br />
+    <h2>LAG 4 <input style="width:15%;margin-left: 3em;" class="action" id="l_sub3" onclick="lagSub(3);" type="button" value="Update / Create"></h2>
+    <div id="mLAG3"></div>
+    <script src="/lag.js"></script>
+    </div>
+    <script src="/navigation.js"></script>
+  </body>
+</html>
@@ -0,0 +1,81 @@
+var lagInterval = Number();
+
+function lagForm() {
+  if (!numPorts)
+    return;
+  for (let j=0; j < 4; j++) {
+    var lag = "mLAG" + j
+    console.log("Adding LAG " + lag)
+    var m = document.getElementById(lag);
+    for (let i = 1; i <= numPorts; i++) {
+      const d = document.createElement("div");
+      d.classList.add("cbgroup");
+      const l = document.createElement("label");
+      l.innerHTML = "" + i;
+      l.classList.add("cbgroup");
+      const inp = document.createElement("input");
+      inp.type = "checkbox"; inp.setAttribute("class","psel");
+      inp.id = "p_" + lag + "_" + i;
+      const o = document.createElement("img");
+      if (pIsSFP[i - 1]) {
+        o.src = "sfp.svg"; o.width ="60"; o.height ="60";
+      } else {
+        o.src = "port.svg"; o.width = "40"; o.height = "40";
+      }
+      l.appendChild(inp); l.appendChild(o);
+      d.appendChild(l)
+      m.appendChild(d);
+    }
+  }
+  fetchLag();
+}
+
+function setL(p, c){
+  console.log("LAG setting: ", p, " to ", c);
+  document.getElementById(p).checked=c;
+}
+
+function fetchLag() {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    if (this.readyState == 4 && this.status == 200) {
+      const s = JSON.parse(xhttp.responseText);
+      console.log("LAG: ", JSON.stringify(s));
+      for (let l = 0; l < 4; l++) {
+        let members = parseInt(s[l].members, 2);
+        let hash = parseInt(s[l].hash, 16);
+        for (let i = 1; i <= numPorts; i++) {
+          let p = i - 1;
+          if (numPorts < 9)
+            p = physToLogPort[p];            
+          setL("p_mLAG"+l+"_"+i, members & (1<<p));
+        }
+      }
+    }
+  };
+  xhttp.open("GET", `/lag.json`, true);
+  sendXHTTP(xhttp);
+}
+async function lagSub(l) {
+  var cmd = "lag " + l;
+  for (let i = 1; i <= numPorts; i++) {
+    if (document.getElementById("p_mLAG"+l+"_"+i).checked)
+      cmd = cmd + ` ${i}`;
+  }
+  try {
+    const response = await fetch('/cmd', {
+      method: 'POST',
+      body: cmd
+    });
+    console.log('Completed!', response);
+  } catch(err) {
+    console.error(`Error: ${err}`);
+  }
+}
+
+window.addEventListener("load", function() {
+  update( () => {
+    lagForm();
+    const interval = setInterval(update, 2000);
+  });
+});
@@ -0,0 +1,30 @@
+<!DOCTYPE html>
+<html>
+  <title>RTL Switch Login</title>
+  <link rel="stylesheet" href="style.css">
+  <script>
+    function removeNote() {
+      document.getElementById("incorrect").innerHTML = "";
+    }
+    window.addEventListener("load", function() {
+      if (document.referrer.endsWith("login.html"))
+      document.getElementById("incorrect").innerHTML = "Wrong password!";
+    });
+    </script>
+</head>
+
+<body class="login_page">
+  <div class = "center">
+  <h1> RTL Switch Login</h1>
+  <form method="post" action="login">
+  <div class="txt_field">
+    <input name="pwd" type="password" onclick="removeNote()" required />
+    <span></span>
+    <label>Password</label>
+  </div>
+  <input type="submit" value="Login"/>
+  <h3 id="incorrect" style="margin-top: 5em;"></h3>
+  </form>
+</body>
+</html>
+
@@ -0,0 +1,286 @@
+var txG = new BigInt64Array(10);
+var txB = new BigInt64Array(10);
+var rxG = new BigInt64Array(10);
+var rxB = new BigInt64Array(10);
+const linkS = ["Disabled", "Down", "10M", "100M", "1000M", "500M", "10G", "2.5G", "5G"];
+var pState = new Int8Array(10);
+var pIsSFP = new Int8Array(10);
+var pAdvertised = new Int8Array(10);
+var numPorts = 0;
+var logToPhysPort = new Int8Array(10);
+var physToLogPort = new Int8Array(10);
+var portNames = new Array(10);
+var currentRequests = [];
+var currentCallback;
+function drawPorts() {
+  var f = document.getElementById('ports');
+  console.log("DRAWING PORTS: ", numPorts);
+  for (let i = 0; i < numPorts; i++) {
+    console.log("DRAWING isSFP: ", pIsSFP[i]);
+    const d = document.createElement("div");
+    d.classList.add('tooltip');
+    const s = document.createElement("span");
+    s.classList.add("tooltiptext");
+    s.innerHTML = "Tooltip text";
+    s.id="tt_" + (i+1);
+    const l = document.createElement("object");
+    d.appendChild(l);
+    d.appendChild(s);
+    l.type = "image/svg+xml";
+    if (!pIsSFP[i]) {
+      l.data = "port.svg";
+      l.width ="40";
+      l.height ="40";
+    } else {
+      l.data = "sfp.svg";
+      l.width = "60";
+      l.height = "60";
+    }
+    l.id="port" + (i+1);
+    f.appendChild(d);
+  }
+}
+
+function parseUint16(val) {
+  return parseInt(val, 16) & 0xffff;
+}
+
+function parseInt16(val) {
+  let valInt = parseInt(val, 16);
+  let num = valInt & 0x7fff;
+  if (valInt & 0x8000) {
+    return num - 0x8000;
+  }
+  return num;
+}
+
+function applyCalibrationSlopeOffset(val, cal) {
+  if (typeof cal !== 'string') {
+    return val;
+  }
+  if (cal.startsWith("0x")) {
+    cal = cal.substring(2);
+  }
+  if (cal.length != 8) {
+    return val;
+  }
+  let slope = parseUint16(cal.substring(0, 4)) / 256;
+  let offset = parseInt16(cal.substring(4, 8));
+  return slope * val + offset;
+}
+
+function applyRxPowerCalibration(val, cal) {
+  if (typeof cal !== 'string') {
+    return val;
+  }
+  if (cal.startsWith("0x")) {
+    cal = cal.substring(2);
+  }
+  if (cal.length != 40) {
+    return val;
+  }
+  let bytes = cal.match(/.{1,2}/g).map(function (x) { return parseInt(x, 16); });
+  let view = new DataView(new Uint8Array(bytes).buffer);
+  return view.getFloat32(0) * Math.pow(val, 4)
+    + view.getFloat32(4) * Math.pow(val, 3)
+    + view.getFloat32(8) * Math.pow(val, 2)
+    + view.getFloat32(12) * val
+    + view.getFloat32(16);
+}
+
+function decodeSfpTemp(val, cal) {
+  let temp = parseInt16(val);
+  return applyCalibrationSlopeOffset(temp, cal) / 256;
+}
+
+function decodeSfpVcc(val, cal) {
+  let vcc = parseUint16(val);
+  return applyCalibrationSlopeOffset(vcc, cal) / 10000;
+}
+
+function decodeSfpTxBias(val, cal) {
+  let bias = parseUint16(val);
+  return applyCalibrationSlopeOffset(bias, cal) / 500;
+}
+
+function decodeSfpTxPower(val, cal) {
+  let txPower = parseUint16(val);
+  return applyCalibrationSlopeOffset(txPower, cal) / 10000;
+}
+
+function decodeSfpRxPower(val, cal) {
+  let rxPower = parseUint16(val);
+  return applyRxPowerCalibration(rxPower, cal) / 10000;
+}
+
+function convertPowerTodBm(val) {
+  return 10 * Math.log10(val);
+}
+
+function update(callback) {
+  var xhttp = new XMLHttpRequest();
+  xhttp.onreadystatechange = function() {
+    console.log("IN UPDATE ");
+    if (this.readyState == 4 && this.status == 401)
+	    document.location = "/login.html"
+    if (this.readyState == 4 && this.status == 200) {
+      const s = JSON.parse(xhttp.responseText);
+      if (!numPorts) {
+	numPorts = s.length;
+	for (let i = 0; i < s.length; i++)
+	  pIsSFP[s[i].portNum-1] = s[i].isSFP;
+	drawPorts();
+      }
+      console.log("RES:", JSON.stringify(s));
+      for (let i = 0; i < s.length; i++) {
+	p = s[i];
+	let n = p.portNum;
+	logToPhysPort[p.logPort] = n;
+	physToLogPort[n-1] = p.logPort;
+	portNames[p.logPort] = p.name;
+	let pid = "port" + n;
+	let ttid = "tt_" + n;
+	n--;
+	txG[n] = BigInt(p.txG); txB[n] = BigInt(p.txB); rxG[n] = BigInt(p.rxG); rxB[n] = BigInt(p.rxB);
+	var psvg = document.getElementById(pid);
+	var tt = document.getElementById(ttid);
+	if (psvg == null || !psvg.contentDocument)
+	  continue;
+	var bgs = psvg.contentDocument.getElementsByClassName("bg");
+	var leds = psvg.contentDocument.getElementsByClassName("led");
+        if (leds[0] == null || leds[0].style == null)
+          continue;
+	const portName = p.name || portNames[p.logPort] || '';
+	var iHTML = "<table border=\"0\" class=\"tt_table\">";
+	if (portName) iHTML += "<tr><td align=\"left\">Name</td><td>:</td><td>" + portName + "</td></tr>";
+	if (p.enabled == 0) {
+	  pState[n] = -1;
+	  bgs[0].style.fill = "red";
+	  leds[0].style.fill = "black"; leds[1].style.fill = "black";
+	  psvg.style.opacity = 0.4;
+	  iHTML += "<tr><td align=\"left\">Status</td><td>:</td><td>Not enabled.</td></tr>";
+	  iHTML += "</table>";
+	  tt.innerHTML = iHTML;
+	} else {
+	  psvg.style.opacity = 1.0;
+	  pState[n] = p.link;
+	  if (p.link == 5 || p.link == 7) {
+	    leds[0].style.fill = "green"; leds[1].style.fill = "blue";
+	  } else if (p.link == 4 || p.link == 6) {
+	    leds[0].style.fill = "green"; leds[1].style.fill = "orange";
+	  } else if (p.link == 1 || p.link == 2 || p.link == 3) {
+	    leds[0].style.fill = "green"; leds[1].style.fill = "green";
+	  } else {
+	    leds[0].style.fill = "black"; leds[1].style.fill = "black";
+	    psvg.style.opacity = 0.4
+	  }
+	  iHTML += "<tr><td align=\"left\">Link speed</td><td>:</td><td>" + linkS[p.link + 1] + "</td></tr>";
+	  if (p.isSFP) {
+	    pAdvertised[n] = 0;
+	    const hasExtendedStatus = p.sfp_options & 0x40;
+	    iHTML += "<tr><td>Vendor</td><td>:</td><td>" + p.sfp_vendor + "</td></tr>";
+	    iHTML += "<tr><td>Model</td><td>:</td><td>" + p.sfp_model + "</td></tr>";
+	    iHTML += "<tr><td>Serial</td><td>:</td><td>" + p.sfp_serial + "</td></tr>";
+	    if (hasExtendedStatus) {
+	      let txPower = decodeSfpTxPower(p.sfp_txpower, p.sfp_txpower_cal);
+	      let txPowerdBm = convertPowerTodBm(txPower);
+	      let rxPower = decodeSfpRxPower(p.sfp_rxpower, p.sfp_rxpower_cal);
+	      let rxPowerdBm = convertPowerTodBm(rxPower);
+	      iHTML += "<tr><td>Temp</td><td>:</td><td>" + decodeSfpTemp(p.sfp_temp, p.sfp_temp_cal).toFixed(2) + "&#8239;&#8451;</td></tr>";
+	      iHTML += "<tr><td>Vcc</td><td>:</td><td>" + decodeSfpVcc(p.sfp_vcc, p.sfp_vcc_cal).toFixed(2) + "&#8239;V</td></tr>";
+	      iHTML += "<tr><td>TX-Fault</td><td>:</td><td>" + (Boolean(Number(p.sfp_state) & 0x4)) + "</td></tr>";
+	      iHTML += "<tr><td>TX-Disabled</td><td>:</td><td>" + (Boolean(Number(p.sfp_state) & 0x80)) + "</td></tr>";
+	      iHTML += "<tr><td>TX-Bias</td><td>:</td><td>" + decodeSfpTxBias(p.sfp_txbias, p.sfp_txbias_cal).toFixed(1) + "&#8239;mA</td></tr>";
+	      iHTML += "<tr><td>TX-Power</td><td>:</td><td>" + txPower.toFixed(3) + "&#8239;mW / " + txPowerdBm.toFixed(2) + "&#8239;dBm</td></tr>";
+	      iHTML += "<tr><td>RX-Power</td><td>:</td><td>" + rxPower.toFixed(3) + "&#8239;mW / " + rxPowerdBm.toFixed(2) + "&#8239;dBm</td></tr>";
+	    }
+	    // Not all devices & modules have LOS pin...
+	    const rx_los_pin = p.sfp_los !== null ? Boolean(Number(p.sfp_los)) : null;
+	    const rx_los_module = hasExtendedStatus ? Boolean(Number(p.sfp_state) & 0x2) : null;
+	    if (rx_los_module !== null || rx_los_pin !== null) {
+	      iHTML += `<tr><td>RX-LOS</td><td>:</td><td>${rxLosHTML(rx_los_pin, rx_los_module)}</td></tr>`;
+	    }
+	  } else {
+	    pAdvertised[n] = parseInt(p.adv, 2);
+	  };
+	  iHTML += "</table>";
+	  tt.innerHTML = iHTML;
+	}}
+	if (callback)
+	  callback();
+	}};
+	xhttp.open("GET", "/status.json", true);
+	xhttp.timeout = 5000;
+	sendXHTTP(xhttp);
+}
+
+function rxLosHTML(pinStatus, moduleStatus) {
+  if (moduleStatus !== null && pinStatus !== null && moduleStatus !== pinStatus) {
+    return `pin=${pinStatus}<br/>mod=${moduleStatus}<br/>❗❗❗❗`;
+  }
+
+	// Returns first non null value
+  return moduleStatus ?? pinStatus;
+}
+
+function callbackXHTTP()
+{
+  x = currentRequests.shift();
+  x.onreadystatechange = currentCallback;
+  x.onreadystatechange();
+  if (currentRequests.length === 0)
+    return;
+  x = currentRequests[0];
+  currentCallback = x.onreadystatechange;
+  x.onreadystatechange = callbackXHTTP;
+  var retries = 10;
+  while (retries) {
+    try {
+      setTimeout(() => {
+              x.send();
+              console.log("B1");
+      }, 20);
+    } catch (error) {
+      retries--;
+      setTimeout(() => {
+        console.log(`Retry ${retries}/${maxRetries} failed: ${error.message}`);
+      }, 200);
+      if (retries < 1) {
+        throw error;
+      }
+    }
+    console.log("B2");
+    return;
+  }
+}
+
+function sendXHTTP(x)
+{
+  console.log("sendXHTTP ", x);
+  if (currentRequests.length === 0) {
+    currentRequests.push(x);
+    currentCallback = x.onreadystatechange;
+    x.onreadystatechange = callbackXHTTP;
+    var retries = 10;
+    while (retries) {
+      try {
+        x.send();
+        console.log("A1");
+      } catch (error) {
+        retries--;
+        setTimeout(() => {
+          console.log(`Retry ${retries}/${maxRetries} failed: ${error.message}`);
+        }, 200);
+        if (retries < 1) {
+          throw error;
+        }
+      }
+      console.log("A2");
+      return;
+    }
+    console.log("A3");
+    return;
+  }
+  currentRequests.push(x);
+}
+
--- a/Show More
+++ b/Show More