mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Fix: Serial Timer1: GATE bit should be off.
Fixes PR#66, commitc5c6b97and4e8eb6d. The GATE-bit should not be used. Timer1 must always be activated to generate the baudrate clock for serial 0.
This commit is contained in:
@@ -111,7 +111,7 @@ void setup_serial_timer1(void)
|
||||
{
|
||||
// Timer 1: Mode 2: automatic reload
|
||||
TMOD &= 0x0F;
|
||||
TMOD |= 0xA0; // Timer1: GATE, Mode2: Timer, 8-bit with auto-reload
|
||||
TMOD |= 0x20; // Timer1: Mode2: Timer, 8-bit with auto-reload
|
||||
CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
|
||||
|
||||
PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.
|
||||
|
||||
+1
-1
@@ -1693,7 +1693,7 @@ void setup_serial_timer1(void)
|
||||
{
|
||||
// Timer 1: Mode 2: automatic reload
|
||||
TMOD &= 0x0F;
|
||||
TMOD |= 0xA0; // Timer1: GATE, Mode2: Timer, 8-bit with auto-reload
|
||||
TMOD |= 0x20; // Timer1: Mode2: Timer, 8-bit with auto-reload
|
||||
CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
|
||||
|
||||
PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.
|
||||
|
||||
Reference in New Issue
Block a user