Both macros expand to a run of statements joined by backslashes with
nothing around them, so as the unbraced body of an if or a for only the
first assignment belongs to that body. The other three and the
reg_write() call sit after it and run once, unconditionally, with
whatever the loop counter ended on. Wrapping each macro into a single
statement is what every call site already assumes it to be.
This hands the compiler no new room around the SFR writes, which is worth
showing rather than asserting. Building the whole image before and after
and comparing the generated assembly module by module, with label
numbering, block scope suffixes and the version string normalised away,
three modules differ: rtl837x_igmp, rtl837x_port and rtl837x_leds. Ten
modules call these macros, so the other seven come out identical, and so
does everything else in the image.
Those three differ because they hold the five unbraced uses. Two of them
want a fix rather than only the brace, and that is left to the commits
that follow.
Six bytes of BANK1 on SWTGW218AS, nothing anywhere else.
Register RTL8373_EEE_CTRL_BASE did not actually exist at 0x606c,
instead RTL837X_EEE_STATUS is actually not only a status, but also
a control register for EEE enable/disable at the MAC.
The defines are not actually register bits, but port EEE settings,
so move them to rtl837x_port.h while adding 5G/10G flags.
We use the SoC's UUID to generate a fixed MAC for a particular
switch device. The MAC generated uses a Realtek prefix and then
is followed by 3 bytes genertaed from the first 3 bytes of the
UUID xored with the last byte in order to prevent being able
to deduce the UUID from the public MAC.
Without this fix N-type SOC devices like RTL8372N, RTL8383N and also the
4-port PHY RTL8224N, don't have a functional Serdes. Although the SOC
sees a link, there is no packet flow on both SFP-port nor RTL8224 ports.
Added helper functions to read/write to the RTL8224.
RTL8224 has the same register layout so we can use the same register
defines as for the main SOC.
Detect the SOC type and variant. RTL8372 vs RTL8373 and also is it as
non-N/N variant of the SOC.
Even if the machine profile is wrong the hardware will be initilised on
the detected type.
This adds an implementation for trapping IGMP packets to the CPU
which will identify IGMPv1/2/3 packets, but handle only v3.
The implementation then inserts/updates/deletes L3 MC entries
in the L3 lookup table. The entries consist of an Ipv4
Destination IP (the IPv4 MC address), a Source IP (0.0.0.0) and
a Portmask. Note that this implementation is not VLAN aware,
as there is no hardware support in the device.
An alternative strategy is to control switching of the L2-MC packets
in which the IPv4-MC packets are transported (dst-MaC is
01:00:5e:xx:yy:zz, with xx:yy:zz corresponding to bits in the Ipv4-MC
address). This will allow to use VLAN-aware packet switching. While
code support is there for table insert/update/deletes, some further
L2 configuration is missing.
There is no support for IPv6 MC, yet.
This fixes handling of the SFP ports in the stat command.
The output of the command now is for physical ports, which however are
not shown in sequence.
Compiler
rtl837x_port.c:466: warning 116: right shifting more than size of object changed to zero
provided value is a uint16. So shifting it more then 16 cause this error.
Solution: cast the value to uint32_t.
Each register holds the STP port state for one Forwarding ID (FID),
of which there 16 can be used by the RTL8372. The mapping between
FID and VLAN is done in the VLAN table. This allows the SoC
to maintain 16 different MSTP states.
In the register 2 bits per port are used to designate the following
(R)STP states
00 disable, 01 blocking, 10 learning, 11 forwarding
The STP listening state is not available.
d00f
logicog
TylerDurden-23
chriz
René van Dorst
feelfree69
logicog