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https://github.com/logicog/RTLPlayground.git
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269 lines
7.2 KiB
C
269 lines
7.2 KiB
C
/*
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* This is a driver implementation for the Internal PHYs and RTL8221/RTL8224 PHYs
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* for the RTL827x platform
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* This code is in the Public Domain
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*/
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#define REGDBG
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#include <stdint.h>
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#include "rtl837x_common.h"
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#include "rtl837x_sfr.h"
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#include "rtl837x_regs.h"
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#include "rtl837x_phy.h"
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#pragma codeseg BANK1
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extern __code uint16_t bit_mask[16];
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__code uint16_t rtl8224_ca[42] = {
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0x4480, 0xc842,
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0x0400, 0xc9c2,
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0x6d02, 0xcc42,
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0x424e, 0xcdc2,
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0x0002, 0xcec2,
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0x1390, 0xce6c,
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0x003f, 0xca6c,
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0x0200, 0xc86c,
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0x0080, 0xc25c,
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0x0408, 0xc35c,
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0x020d, 0xc3dc,
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0x0601, 0xc4dc,
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0x222c, 0xc5dc,
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0xa217, 0xc65c,
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0xfe40, 0xc6dc,
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0xf5c1, 0xcadc,
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0x0443, 0xcb5c,
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0xabb0, 0xcedc,
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0x5078, 0xc90c,
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0xc45c, 0xc18c,
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0, 0
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};
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__code uint16_t rtl8224_cb[60] = {
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0xc45c, 0xc18c, 0x8040,
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0x0030, 0xc040, 0x8040,
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0x0010, 0xc040, 0x8040,
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0x0050, 0xc040, 0x8040,
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0x00d0, 0xc040, 0x8040,
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0x0cd0, 0xc040, 0x8040,
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0x04d0, 0xc040, 0x8040,
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0x04d0, 0xc040, 0x8040,
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0x0cd0, 0xc040, 0x8040,
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0x00d0, 0xc040, 0x8040,
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0x00d0, 0xc040, 0x8040,
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0x0050, 0xc040, 0x8040,
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0x0010, 0xc040, 0x8040,
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0x0010, 0xc040, 0x8040,
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0x0030, 0xc040, 0x8040,
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0x0000, 0xc040, 0x803e,
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0x000b, 0xc03e, 0x803e,
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0x0000, 0xc03e, 0x8042,
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0x4906, 0xc042, 0x82ec,
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0xffff,0,0
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};
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void rtl8224_phy_enable(void) __banked
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{
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// p001e.0a90:00f3 R02f8-000000f3 R02f4-000000fc P000001.1e000a90:00fc
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print_string("\r\nrtl8224_phy_enable called\r\n");
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phy_read(0, 0x1e, 0xa90);
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uint16_t pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0;
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// PHY Initialization:
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REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
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pval &= 0xfff0;
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pval |= 0x0c;
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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phy_write(0x1, 0x1e, 0xa90, pval);
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phy_read(0, 0x1e, 0xa90);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0;
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delay(50);
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print_string("\r\nrtl8224_phy_enable done\r\n");
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}
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void phy_config(uint8_t phy) __banked
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{
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uint16_t pval;
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print_string("\r\nphy_config: ");
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write_char('0' + phy);
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delay(20);
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// PHY configuration: External 8221B?
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// p081e.75f3:ffff P000100.1e0075f3:fffe
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phy_read(phy, 0x1e, 0x75f3);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 & 0xfe;
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phy_write(bit_mask[phy], 0x1e, 0x75f3, pval);
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delay(20);
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// p081e.697a:ffff P000100.1e00697a:ffc1 / p031e.697a:0003 P000008.1e00697a:0001
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// SERDES OPTION 1 Register (MMD 30.0x6) bits 0-5: 0x01: Set HiSGMII+SGMII
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phy_read(phy, 0x1e, 0x697a);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 & 0xc0 | 0x01;
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phy_write(bit_mask[phy], 0x1e, 0x697a, pval);
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delay(20);
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// p031f.a432:0811 P000008.1f00a432:0831
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// PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE
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phy_read(phy, 0x1f, 0xa432);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 | 0x20;
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phy_write(bit_mask[phy], 0x1f, 0xa432, pval);
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// p0307.003e:0000 P000008.0700003e:0001
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// EEE avertisment 2 register MMMD 7.0x003e, set bit 0: 2.5G has EEE capability
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phy_read(phy, 0x7, 0x3e);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 | 0x1;
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phy_write(bit_mask[phy], 0x7, 0x3e, pval);
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delay(20);
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// p031f.a442:043c P000008.1f00a442:0430
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// Unknown, but clear bits 2/3
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phy_read(phy, 0x1f, 0xa442);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 & 0xf3;
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phy_write(bit_mask[phy], 0x1f, 0xa442, pval);
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delay(20);
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// P000100.1e0075b5:e084
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phy_write(bit_mask[phy], 0x1e, 0x75b5, 0xe084);
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delay(20);
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// p031e.75b2:0000 P000008.1e0075b2:0060
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// set bits 5/6
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phy_read(phy, 0x1e, 0x75b2);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0 | 0x60;
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phy_write(bit_mask[phy], 0x1e, 0x75b2, pval);
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delay(20);
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// p081f.d040:ffff P000100.1f00d040:feff
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// LCR6 (LED Control Register 6, MMD 31.D040), set bits 8/9 to 0b10
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phy_read(phy, 0x1e, 0xd040);
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pval = (SFR_DATA_8 & 0xfc) | 0x02;
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pval <<= 8;
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pval |= SFR_DATA_0;
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phy_write(bit_mask[phy], 0x1e, 0xd040, pval);
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delay(20);
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// p081f.a400:ffff P000100.1f00a400:ffff, then: p081f.a400:ffff P000100.1f00a400:bfff
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// p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040
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// FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400)
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// Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved
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phy_read(phy, 0x1f, 0xa400);
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pval = SFR_DATA_8 | 0x40;
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pval <<= 8;
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pval |= SFR_DATA_0;
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phy_write(bit_mask[phy], 0x1f, 0xa400, pval);
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delay(20);
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phy_read(phy, 0x1f, 0xa400);
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pval = SFR_DATA_8 & 0xbf;
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pval <<= 8;
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pval |= SFR_DATA_0;
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phy_write(bit_mask[phy], 0x1f, 0xa400, pval);
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delay(20);
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print_string("\r\n phy config done\r\n");
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}
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void phy_config_8224(void) __banked
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{
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// p001e.7b20:0bff R02f8-00000bff R02f4-00000bed P000001.1e007b20:0bed
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uint16_t pval;
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print_string("\r\nphy_config_8224 called\r\n");
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phy_read(0, 0x1e, 0x7b20);
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pval = SFR_DATA_8;
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pval <<= 8;
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pval |= SFR_DATA_0;
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REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
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pval &= 0x0fe0;
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pval |= 0x000d;
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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phy_write(0x01, 0x1e, 0x7b20, pval);
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uint8_t i = 0;
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while (rtl8224_ca[i]) {
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phy_write(0x1, 0x1e, 0x400, rtl8224_ca[i]);
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i++;
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phy_write(0x1, 0x1e, 0x3f8, rtl8224_ca[i]);
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i++;
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do {
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phy_read(0, 0x1e, 0x3f8);
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} while (SFR_DATA_8 & 0x80);
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}
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print_string("\r\nphy_config_8224 done\r\n");
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}
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/*
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* Set Speed, duplex and flow control mode of a PHY
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* See e.g. RTL8221B datasheet
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*/
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void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t duplex) __banked
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{
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uint16_t v;
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phy_read(port, 0x1f, 0xa610);
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v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0;
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if (speed == PHY_OFF) {
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phy_write(bit_mask[port], 0x1f, 0xa610, v | 0x0800);
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return;
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}
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// Port is on, make sure of it:
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if (v & 0x0800)
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phy_write(bit_mask[port], 0x1f, 0xa610, v & 0xf7ff);
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if (speed == PHY_SPEED_AUTO) {
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// AN Advertisement Register (MMD 7.0x0010)
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phy_write(bit_mask[port], 0x07, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used
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// Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020)
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phy_write(bit_mask[port], 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed
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phy_write(bit_mask[port], 0x07, 0x00, 0x3200); // Restart AN
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} else {
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// AN Control Register (MMD 7.0x0000)
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phy_write(bit_mask[port], 0x07, 0x00, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13)
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// AN Advertisement Register (MMD 7.0x0010)
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phy_write(bit_mask[port], 0x07, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used
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if (speed == PHY_SPEED_1G) {
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// Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020)
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phy_write(bit_mask[port], 0x07, 0x20, 0x6001); // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed
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// GBCR (1000Base-T Control Register, MMD 31.0xA412)
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phy_read(port, 0x1f, 0xa412);
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v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0;
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phy_write(bit_mask[port], 0x1f, 0xa412, v | 0x0200);
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} else if (speed == PHY_SPEED_2G5) {
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// Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020)
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phy_write(bit_mask[port], 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed
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// GBCR (1000Base-T Control Register, MMD 31.0xA412)
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phy_read(port, 0x1f, 0xa412);
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v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0;
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phy_write(bit_mask[port], 0x1f, 0xa412, v & 0xfdff);
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}
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phy_write(bit_mask[port], 0x07, 0x00, 0x3200); // Enable AN
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}
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}
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