logicog
984831620c
Use multiple concurrent TCP connections
...
This uses multiple concurrent TCP connections by making the state
of the connection including the output buffer a part of the application
data. This leads to the buffer, to be sent length of data and the already
sent data to be part of that state and must be handed over to functions
that generate data. At this point this leads to an overuse of OSEG and DSEG
memory space so further work needs to be done on tuning the code.
Putting it into a branch for now.
2025-08-06 17:00:14 +02:00
logicog
fff09a0521
Add support for dynamically regenerated web-pages. Limit to 1 concurrent TCP connection for now.
2025-08-06 11:24:36 +02:00
logicog
3841eea919
Fine tunig of Ethernet port and SFP images
2025-08-06 11:22:57 +02:00
logicog
c9a82b550a
Fix for issue #3 reported by airjinkela: wrong register ID exceeding 16bit
2025-08-06 08:22:19 +02:00
logicog
0fb4fafdb2
strtox now returns copied length
2025-08-05 09:34:44 +02:00
logicog
f8eb55d587
Adding code for dynamic html page functions
2025-08-05 09:33:42 +02:00
logicog
49a25f0b27
Adding warning about generated header file
2025-08-05 09:32:25 +02:00
logicog
2e6cf7b7d0
Add functionallity to find a mark in the flash buffer for dynamic HTML pages
2025-08-05 09:29:46 +02:00
logicog
5533676e52
Add initial web-pages and hand-crafted svg icons
2025-08-05 09:27:58 +02:00
logicog
05c9d43f2e
Add mime-type of files and fix a bug with a terminating 0 for a file
2025-08-04 09:00:26 +02:00
logicog
498d34e72f
Add replacing API calls for dynamic pages
2025-08-01 23:34:58 +02:00
logicog
42c8f05afe
Add code generation for indexing files in flash
...
Fix
2025-07-31 19:31:29 +02:00
logicog
99344a2d99
New feature: Add all files in a directory
2025-07-30 09:39:33 +02:00
logicog
5aff1f9cf7
Add tools directory
2025-07-29 12:16:55 +02:00
logicog
f36235f411
Add a tool to place data into the image an resize it
2025-07-29 12:08:32 +02:00
logicog
d60a3786bb
Fix typo
2025-07-29 11:18:41 +02:00
logicog
8b1b4aff68
Fix parsing of mirror command, fix parsing of serial buffer beyond wrap arond, add bulk reading of flash and start of config file parser
2025-07-28 23:04:08 +02:00
logicog
7481c88ace
Improve debugging
2025-07-28 23:01:50 +02:00
logicog
417dfe2345
Fix serial buffer length to fit signed char
2025-07-28 23:00:15 +02:00
logicog
2eaea39e18
Fix SFR address of trampoline return
2025-07-28 22:59:23 +02:00
logicog
2e5f3169b3
Fix typo
2025-07-28 22:58:17 +02:00
logicog
a5d156a645
Fix dropping of RTL VLAN tag for 802.1Q Tag, add L2 configuration
2025-07-25 22:51:18 +02:00
logicog
fcd1f85eb6
Add trunking support and initial L2 setup
2025-07-25 22:50:27 +02:00
logicog
891ee08243
Add support for non-linear mapping of physical ports to logical ports. Add support for trunking
2025-07-25 22:49:51 +02:00
logicog
2998b4a791
Fix links in SFP doc
2025-07-23 09:17:07 +02:00
logicog
55e851ef5e
Adding SFP documentation
2025-07-23 09:14:04 +02:00
logicog
0b30019769
Use names for I2C-controller registers
2025-07-23 08:34:26 +02:00
logicog
96a108e891
Use common SDS configuration code also for RTL8224
2025-07-23 08:01:33 +02:00
logicog
e7bffb4a34
Update on features: RTL8224 supported and others
2025-07-22 20:57:20 +02:00
logicog
bcc58d2965
Make RTL8224 work
2025-07-22 19:05:27 +02:00
logicog
8fee855da2
Separate code for rtl8272 from rtl8373 for readability and stability against accidental changes
2025-07-22 09:42:56 +02:00
logicog
995deb313c
Cleanup of unused code
2025-07-22 09:41:44 +02:00
logicog
066edd672e
Add off-state for SDS
2025-07-22 09:34:40 +02:00
logicog
6be1124ecf
Fixed shift arithmetic bug reported by airjinkela
2025-07-21 21:59:20 +02:00
logicog
fa4a80c291
Cleanup of printouts
2025-07-21 11:11:52 +02:00
logicog
ccd8bf1633
Cleanup
2025-07-17 23:29:20 +02:00
logicog
b6d92b10fa
Latest status
2025-07-17 15:17:33 +02:00
logicog
b0a41a5af6
Add support for RTL8372-devices with 2 SFP+ ports
2025-07-17 13:25:07 +02:00
logicog
ec69299a7b
Clarification that flashing can always be done via patch-clamp
2025-07-14 08:06:56 +02:00
logicog
a6e933fde6
L2 table access feature added
2025-07-14 08:01:59 +02:00
logicog
9b5cfb0e1b
Mirroring and VLAN explained
2025-07-14 08:00:48 +02:00
logicog
84b84f5c32
Cleanup of L2 and mirroring features
2025-07-14 07:59:31 +02:00
logicog
20b5c7b833
Latest update on features
2025-07-14 07:58:55 +02:00
logicog
38cc74d1fa
Add documentation for mirroring
2025-07-13 23:34:03 +02:00
logicog
ba1b03dd63
More documentation on the L2 table
2025-07-13 23:15:51 +02:00
logicog
e3bb76ec1b
Initial description of L2 table
2025-07-13 20:48:37 +02:00
logicog
1ae617c38b
Initial description of L2 table
2025-07-13 20:48:05 +02:00
logicog
d66931acdf
Adding initial http daemon implementation
2025-07-13 12:03:40 +02:00
logicog
e2716da6c8
Typo fixed
2025-07-13 11:53:23 +02:00
logicog
4edc826c39
Accidentally checked in
2025-07-13 11:52:57 +02:00
logicog
8d4b102e97
More porting to RTL837x architecture of psock
2025-07-12 16:11:51 +02:00
logicog
b192a87cab
Cleaning up printouts for debugging of uIP
2025-07-11 16:36:16 +02:00
logicog
a2af2f9151
Empty application for testing
2025-07-11 15:50:55 +02:00
logicog
37cee7692a
Use lc-switch, becasue labels as values is not supported by sdcc
2025-07-11 15:17:38 +02:00
logicog
8b761cfcc8
Add UIP stack. Still lots of debug output on packets...
2025-07-11 14:54:57 +02:00
logicog
e486c04186
Add initial port of uip TCP/IP stack
2025-07-11 14:16:08 +02:00
logicog
f0701295db
Add description of checksum offload bits
2025-07-11 14:14:00 +02:00
logicog
f25cc47c5f
Adding uip lib support
2025-07-06 09:55:12 +02:00
logicog
062c5576de
Fixing banked call
2025-07-05 23:46:09 +02:00
logicog
2d8c0efabd
Add 802.1Q VLAN and PVID support. Support VLAN tag at CPU-port
2025-07-04 09:17:10 +02:00
logicog
997d85ba02
Add basic VLAN configuration
2025-07-02 11:57:15 +02:00
logicog
6f90e1db53
Add support for changing Ethernet speeds
2025-06-29 20:06:53 +02:00
logicog
b59f51b3ca
Cleanup of initialitation, make debug code conditional
2025-06-29 11:10:29 +02:00
logicog
669ebdc616
Access to sfp register reading in common
2025-06-29 11:09:41 +02:00
logicog
fd48ae80c1
Feature updates
2025-06-29 11:09:01 +02:00
logicog
4f799f3677
Adding port module
2025-06-29 11:08:37 +02:00
logicog
5a87d81b8c
Adding port statistics
2025-06-29 11:07:54 +02:00
logicog
5faf31cdb8
Moving PHY code to BANK1
2025-06-25 15:30:50 +02:00
logicog
73a0a7d137
Add banking support
2025-06-25 13:20:06 +02:00
logicog
f543b58490
More on checksum offloading
2025-06-25 13:19:44 +02:00
logicog
797ae23865
Banking support
2025-06-24 06:06:49 +02:00
logicog
178e3d2550
More doc on TX
2025-06-23 19:43:33 +02:00
logicog
08d6c27605
More documentation
2025-06-23 19:41:26 +02:00
logicog
b8352f9430
Implement ARP broadcast and make ping work
2025-06-23 17:57:54 +02:00
logicog
2776df9ca8
Make RX of packets work
2025-06-21 16:18:19 +02:00
logicog
dd039494c2
Add more RTL8224 config
2025-06-21 05:58:55 +02:00
logicog
869db02865
Emable RTL8224 PHY. Better implementation of sleep/delay timer
2025-06-17 18:21:15 +02:00
logicog
e4d477938d
Detect RTL8373 and name registers for GPIO. Enable RTL8224
2025-06-16 06:55:47 +02:00
logicog
85cb2a52a5
Cleanup
2025-06-15 18:26:27 +02:00
logicog
b49f2aa16f
Add initial support for RTL8373
2025-06-15 18:24:23 +02:00
logicog
88067d3a3e
Add command byte macros and NIC SFRs
2025-06-15 18:19:43 +02:00
logicog
c435feee45
Add REG_SET macro
2025-06-15 18:18:36 +02:00
logicog
9a69fac07a
Adding support for 2.5Gbit Ethernet modules
2025-06-14 09:52:15 +02:00
logicog
37ca55392a
Add support for 10G Fiber
2025-06-14 09:12:24 +02:00
logicog
7eb7057787
use uint types
2025-06-14 09:12:07 +02:00
logicog
d78e28cbdb
New features: SFP EEProm reading and SFP configuration
2025-06-13 20:39:18 +02:00
logicog
0485c21da0
Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
2025-06-13 20:36:49 +02:00
logicog
c00c908579
Keep up with features: SerDes configuration for port 5
2025-06-12 20:36:59 +02:00
logicog
b41410ce6b
Cleanup
2025-06-12 20:33:35 +02:00
logicog
8c8b92ed65
Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit
2025-06-12 20:32:36 +02:00
logicog
86aebcbf08
Add rtl837x_regs.h register header
2025-06-12 20:31:53 +02:00
logicog
c7965d048e
An injector of .hex files from as31 into .bin images
2025-06-11 06:44:35 +02:00
logicog
8302b0d0d2
Update on console
2025-06-10 18:14:37 +02:00
logicog
fdec0ad80c
Status update
2025-06-10 18:11:29 +02:00
logicog
8243a454de
Adding support for link status display
2025-06-10 17:57:28 +02:00
logicog
2ae0b5caba
Moving registers to dedicated header so they can be better documented
2025-06-10 17:56:42 +02:00
logicog
c54227f057
Fix SFR_DATA access, make internal switch work
2025-06-09 11:22:52 +02:00
logicog
c5d7628ea0
Adding support for the ASIC second counter register and sleeping
2025-06-06 20:49:15 +02:00
logicog
a0a5328ecd
Document default baud of 115200
2025-06-05 20:16:24 +02:00
logicog
9f22c49af7
Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud
2025-06-05 20:15:42 +02:00
logicog