Add assmebler injection script

doc: Add HOWTO for using firmware tracing to figure LED configuration
This adds a howto for figuring out LED configuration via tracing of functions in the originam firmware image. The method also provides information on PHY and SDS configuration, including PHY patches.
2026-10-29 17:54:14 +08:00 · 2026-10-15 06:53:23 +02:00 · 2026-10-11 22:31:33 +02:00 · 2026-10-10 09:17:00 +00:00 · 2026-10-10 09:51:50 +01:00 · 2026-10-10 09:51:33 +01:00
30 changed files with 1670 additions and 151 deletions
@@ -79,10 +79,12 @@ SRCS += \
 	rtl837x_igmp.c \
 	rtl837x_init.c \
 	rtl837x_leds.c \
+	rtl837x_leds_dump.c \
 	rtl837x_phy.c \
 	rtl837x_pins.c\
 	rtl837x_port.c \
 	rtl837x_stp.c \
+	rtl837x_lldp.c \
 	rtl837x_storm.c
 SRCS += \
 	httpd/httpd.c \
@@ -16,6 +16,7 @@
 #include "rtl837x_stp.h"
 #include "rtl837x_igmp.h"
 #include "rtl837x_bandwidth.h"
+#include "rtl837x_lldp.h"
 #include "rtl837x_storm.h"
 #include "sfp.h"
 #include "dhcp.h"
@@ -24,6 +25,7 @@
 #include "version.h"

 #include "machine.h"
+#include "rtl837x_leds.h"
 #include "phy.h"

 #pragma codeseg BANK2
@@ -32,6 +34,7 @@
 extern __code const struct machine machine;
 extern __xdata bool stp_enabled;
 extern __code const uint8_t log_to_phys_port[9];
+extern __xdata bool lldp_enabled;

 extern volatile __xdata uint32_t ticks;
 extern volatile __xdata uint8_t sfr_data[4];
@@ -879,6 +882,7 @@ void parse_port(void)
 		cmd_error("\nUsage:" \
 					 "\nport <port> [show|on|off]" \
 					 "\nport <port> [10m|100m|1g|2g5|duplex] [half|full]" \
+					 "\nport <port> lldp [block|permit]" \
 					 "\nport <port> name [custom port name]\n");
 		return;
 	}
@@ -911,6 +915,14 @@ void parse_port(void)
 		print_string("\nName set to: \"");
 		print_string_x(port_names[phy_settings.port]);
 		print_string("\"\n");
+	} else if (cmd_compare(2, "lldp")) {
+		if (cmd_compare(3, "block")){
+			lldp_logical_port_status &= ~((uint16_t)1 << phy_settings.port);
+		} else if (cmd_compare(3, "permit")) {
+			lldp_logical_port_status |= (uint16_t)1 << phy_settings.port;
+		} else {
+			print_string ("Unknown port <port> lldp [block|permit] command\n");
+		}
 	} else if (machine.is_sfp[phy_settings.port]) {
 		print_string(" is SFP no PHY information available.\n");
 	} else if (cmd_compare(2, "10m")) {
@@ -1976,6 +1988,8 @@ void cmd_parser(void) __banked
 			write_char('\n');
 		} else if (cmd_compare(0, "gpio")) {
 			print_gpio_status();
+		} else if (cmd_compare(0, "leds")) {
+			leds_dump();
 		} else if (cmd_compare(0, "regget")) {
 			parse_regget();
 		} else if (cmd_compare(0, "regset")) {
@@ -2024,6 +2038,14 @@ void cmd_parser(void) __banked
 			parse_ingress();
 		} else if (cmd_compare(0, "session")) {
 			parse_session();
+		} else if (cmd_compare(0, "lldp")) {
+			if (cmd_compare(1, "on")) {
+				print_string("LLDP enabled\n");
+				lldp_enabled = 1;
+			} else {
+				print_string("LLDP disabled\n");
+				lldp_enabled = 0;
+			}
 		}
 		else {
 			cmd_error("Unknown command\n");
@@ -20,6 +20,7 @@ extern __xdata uint8_t err_status;
 #define HEALTH_PH_STP	4
 #define HEALTH_PH_CMD	5
 #define HEALTH_PHASES	6
+#define HEALTH_LLDP     7

 extern __xdata uint16_t health_rx_frames;
 #define health_rx_frame()	health_rx_frames++
@@ -0,0 +1,122 @@
+# ONT-S207CW-62TS-SE / Binardat 2G06-04210GSM / Binardat 2G06-04210GS
+
+## Overview
+
+ONT-S207CW-62TS-SE, Binardat 2G06-04210GSM (managed), and Binardat 2G06-04210GS (unmanaged) are **switches with identical hardware**:
+- **CPU:** RTL8372N (confirmed via serial: "Detecting CPU: RTL8372N")
+- **Flash:** GD25Q128E (16MB)
+- **Ports:** 4x 2.5G RJ45 + 2x 10G SFP+
+- **Console:** 115200 baud (RTLPlayground firmware) / 9600 baud (stock firmware)
+
+**Note:** These devices are **RTL8372N-based** with **LAN ports mounted upside-down on the PCB**, requiring a custom configuration. The `MACHINE_ONT_S207CW_62TS_SE` definition uses a **custom configuration** with:
+- Corrected port mapping (physical ports 1-4 = RJ45, 5-6 = SFP)
+- Optimized LED sets for different port wiring (RJ45 Ports 1-2 have reversed LED wiring)
+- Custom LED mux configuration
+
+## Device Photos
+
+### Binardat 2G06-04210GSM
+
+**Front View:**
+<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-front.jpg" width="400" />
+
+**Back View:**
+<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-back.jpg" width="400" />
+
+**PCB View:**
+<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-pcb.jpg" width="400" />
+
+*Photos courtesy of [andreas5232](https://github.com/andreas5232) from [emesix/ONT-S207CW-62TS-SE#1](https://github.com/emesix/ONT-S207CW-62TS-SE/issues/1)*
+
+## Hardware Specification
+
+| Feature | Value |
+|---|---|
+| **CPU** | RTL8372N |
+| **Flash** | GD25Q128E (16MB) |
+| **RAM** | Integrated in RTL8372N |
+| **RJ45 Ports** | 4x 2.5GBase-T (Ports 1-4) |
+| **SFP+ Ports** | 2x 10G (Ports 5-6) |
+| **Console** | UART (115200 baud for RTLPlayground, 9600 baud for stock) |
+| **Stock Web UI IP** | 192.168.2.1 |
+| **Loader Mode IP** | 192.168.10.247 |
+
+## Port Layout
+
+```
+┌─────────────────────────────────────────────┐
+│  ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐   ┌─────┐ ┌─────┐  │
+│  │RJ45 │ │RJ45 │ │RJ45 │ │RJ45 │   │SFP+ │ │SFP+ │  │
+│  │  1  │ │  2  │ │  3  │ │  4  │   │  5  │ │  6  │  │
+│  └─────┘ └─────┘ └─────┘ └─────┘   └─────┘ └─────┘  │
+│                                                     │
+│  [System LEDs]                                      │
+└─────────────────────────────────────────────┘
+```
+
+## LED Behavior
+
+### RJ45 Ports (Physical 1-4)
+
+| LED Color | Speed |
+|---|---|
+| **Green** | 2.5G |
+| **Orange** | 1G / 100M / 10M |
+| **Off** | No link |
+
+### SFP+ Ports (Physical 5-6)
+
+| LED Color | Speed |
+|---|---|
+| **Green** | 10G |
+| **Orange** | 2.5G / 1G |
+| **Off** | No link / No SFP module |
+
+## Port to Logical Mapping
+
+Custom mapping for ONT-S207CW-62TS-SE:
+
+| Physical Port | Logical Port | Type | LED Set |
+|---|---|---|---|
+| 1 | 7 | RJ45 | 2 |
+| 2 | 6 | RJ45 | 2 |
+| 3 | 5 | RJ45 | 0 |
+| 4 | 4 | RJ45 | 0 |
+| 5 | 3 | SFP+ (SDS0) | 3 |
+| 6 | 8 | SFP+ (SDS1) | 3 |
+
+**Note:** Ports 1-2 (RJ45) have reversed LED wiring and use LED-Set 2. SFP Ports 5-6 use LED-Set 3 to account for wiring differences.
+
+## Flashing Instructions
+
+See the [README.md](../../README.md) for general flashing instructions.
+
+## Stock Firmware Information
+
+| Property | Value |
+|---|---|
+| **Default IP** | 192.168.2.1 (ONT) / 192.168.10.247 (Loader Mode) |
+| **Default Login** | admin/admin (may vary by OEM) |
+| **Console Baud** | 9600 (stock) / 115200 (RTLPlayground) |
+| **CPU String** | "RTL8372N" |
+| **Loader Mode IP** | 192.168.10.247 |
+
+## Configuration Details
+
+- **CPU:** RTL8372N
+- **SFP:** SDS0 on logical port 3 (GPIO37), SDS1 on logical port 8 (GPIO38)
+- **Port Mapping:** Physical 1-4 → Logical 7-4, Physical 5-6 → Logical 3,8
+- **LED Wiring:** RJ45 Ports 1-2 and SFP Port 6 have reversed LED pins (orange/green swapped)
+- **LED Sets:** Set 0 for RJ45 Ports 3-4, Set 1 unused, Set 2 for RJ45 Ports 1-2, Set 3 for SFP Ports 5-6
+
+## Notes
+
+- ONT-S207CW-62TS-SE, Binardat 2G06-04210GSM (managed), and Binardat 2G06-04210GS (unmanaged) are **RTL8372N-based** with **LAN ports mounted upside-down on the PCB**
+- Web UI shows correct physical port order (1-2-3-4 for RJ45, 5-6 for SFP)
+- Loader Mode always remains accessible at `192.168.10.247` for recovery
+- Serial console: 9600 baud (stock) → 115200 baud (RTLPlayground)
+
+## References
+
+- [GitHub Issue: emesix/ONT-S207CW-62TS-SE#1](https://github.com/emesix/ONT-S207CW-62TS-SE/issues/1) - Original photos and discussion
+- [PR: logicog/RTLPlayground#465](https://github.com/logicog/RTLPlayground/pull/465) - Feedback and improvements
@@ -0,0 +1,572 @@
+# LEDs HOWTO using firmware function tracing
+
+This is a tutorial to show how to figure out the LED configuration for
+unmanaged switches (on managed ones one can just print out the registers
+from the command line) without using an I2C port on the device together
+an I2C-capable microcontroller. You will only need to have a SOIC clamp
+and will have to run ghidra to do a bit of reversing.
+
+The additional advantage of this method is that it not only gives the LED
+configuration but also the full PHY configuration and SDS configuration e.g.
+in case of additional PHYs being used on the device.
+
+We will use the ZoeRax HG0402XG V1.1 as an example device.
+
+The first step is to read out the flash with a SOIC clamp.
+Save the image as
+`zoerax_hg0402xg.bin`
+
+The next step is to use a decompiler such as ghidra to identify the
+functions used to write or read registers, SDS or to the PHY.
+
+<img src="images/ghidra_open.png" width="300" />
+
+First, load the code in BANK0 into ghidra. The type of code is
+8051 default big-endian. The code starts at offset 0x0002 in the file
+and has length 0x3ffd
+
+<img src="images/ghidra_add_block.png" width="300" />
+Add BANK1 into ghidra by using File->Add to program...
+and add the code starting at 0x4000 in `zoerax_hg0402xg.bin` with length
+0xc000. Repeat for BANK2 (starts at 0x10000) and BANK3 (starts at 0x1c0000).
+They both have length 0xc000.
+
+<img src="images/ghidra_search_read_reg.png" width="300" />
+
+Now, find the read_reg function. An example of the read-register function
+is given below. Note the critical bit, namely the execution of the
+read-function of an ASIC register via an SFR: 
+```
+CODE1::4dc9 75 a0 01           MOV        SFR_EXEC_GO,#0x1
+```
+
+This sequence of bytes is very specific. Replace 0x01 with 0x03 and you have
+the regster write SFR, 0x05 reads the SerDes, 0x07 writes it. 0x09 reads
+from the PHY and 0x0b writes to it.
+
+
+```
+                             **************************************************************
+                             *                          FUNCTION                          *
+                             **************************************************************
+                             undefined reg_read()
+             undefined         <UNASSIGNED>   <RETURN>
+                             reg_read
+     CODE1::4da9 ab 07              MOV        R3,BANK0_R7                                      = ??
+     CODE1::4dab aa 06              MOV        R2,BANK0_R6                                      = ??
+     CODE1::4dad e4                 CLR        A
+     CODE1::4dae ff                 MOV        R7,A
+     CODE1::4daf fe                 MOV        R6,A
+     CODE1::4db0 fd                 MOV        R5,A
+     CODE1::4db1 fc                 MOV        R4,A
+     CODE1::4db2 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4db5 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4db8 e4                 CLR        A
+     CODE1::4db9 ff                 MOV        R7,A
+     CODE1::4dba fe                 MOV        R6,A
+     CODE1::4dbb fd                 MOV        R5,A
+     CODE1::4dbc fc                 MOV        R4,A
+     CODE1::4dbd 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4dc0 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4dc3 ea                 MOV        A,R2
+     CODE1::4dc4 f5 a2              MOV        SFR_A_ADDRH,A                                    = ??
+     CODE1::4dc6 eb                 MOV        A,R3
+     CODE1::4dc7 f5 a3              MOV        SFR_A_ADDRL,A                                    = ??
+     CODE1::4dc9 75 a0 01           MOV        SFR_EXEC_GO,#0x1 <<<<<<<< Executes READ REG
+                             LAB_CODE1__4dcc                                 XREF[1]:     CODE1::4dcf(j)  
+     CODE1::4dcc af a1              MOV        R7,SFR_EXEC_STATUS                               = ??
+     CODE1::4dce ef                 MOV        A,R7
+     CODE1::4dcf 70 fb              JNZ        LAB_CODE1__4dcc
+     CODE1::4dd1 af a4              MOV        R7,DAT_SFR_a4                                    = ??
+     CODE1::4dd3 fc                 MOV        R4,A
+     CODE1::4dd4 fd                 MOV        R5,A
+     CODE1::4dd5 fe                 MOV        R6,A
+     CODE1::4dd6 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4dd9 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4ddc 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4ddf 12 05 f9           LCALL      FUN_CODE_05f9                                    undefined FUN_CODE_05f9()
+     CODE1::4de2 c0 00              PUSH       BANK0_R0
+     CODE1::4de4 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4de7 12 05 dd           LCALL      read_xmem_32_b                                   undefined read_xmem_32_b()
+     CODE1::4dea 78 18              MOV        R0,#0x18
+     CODE1::4dec 12 05 86           LCALL      FUN_CODE_0586                                    undefined FUN_CODE_0586()
+     CODE1::4def d0 00              POP        BANK0_R0
+     CODE1::4df1 12 05 48           LCALL      FUN_CODE_0548                                    undefined FUN_CODE_0548()
+     CODE1::4df4 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4df7 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4dfa af a5              MOV        R7,DAT_SFR_a5                                    = ??
+     CODE1::4dfc e4                 CLR        A
+     CODE1::4dfd fc                 MOV        R4,A
+     CODE1::4dfe fd                 MOV        R5,A
+     CODE1::4dff fe                 MOV        R6,A
+     CODE1::4e00 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e03 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e06 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e09 12 05 f9           LCALL      FUN_CODE_05f9                                    undefined FUN_CODE_05f9()
+     CODE1::4e0c c0 00              PUSH       BANK0_R0
+     CODE1::4e0e 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e11 12 05 dd           LCALL      read_xmem_32_b                                   undefined read_xmem_32_b()
+     CODE1::4e14 78 10              MOV        R0,#0x10
+     CODE1::4e16 12 05 86           LCALL      FUN_CODE_0586                                    undefined FUN_CODE_0586()
+     CODE1::4e19 d0 00              POP        BANK0_R0
+     CODE1::4e1b 12 05 48           LCALL      FUN_CODE_0548                                    undefined FUN_CODE_0548()
+     CODE1::4e1e 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e21 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e24 af a6              MOV        R7,DAT_SFR_a6                                    = ??
+     CODE1::4e26 e4                 CLR        A
+     CODE1::4e27 fc                 MOV        R4,A
+     CODE1::4e28 fd                 MOV        R5,A
+     CODE1::4e29 fe                 MOV        R6,A
+     CODE1::4e2a 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e2d 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e30 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e33 12 05 f9           LCALL      FUN_CODE_05f9                                    undefined FUN_CODE_05f9()
+     CODE1::4e36 c0 00              PUSH       BANK0_R0
+     CODE1::4e38 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e3b 12 05 dd           LCALL      read_xmem_32_b                                   undefined read_xmem_32_b()
+     CODE1::4e3e 78 08              MOV        R0,#0x8
+     CODE1::4e40 12 05 86           LCALL      FUN_CODE_0586                                    undefined FUN_CODE_0586()
+     CODE1::4e43 d0 00              POP        BANK0_R0
+     CODE1::4e45 12 05 48           LCALL      FUN_CODE_0548                                    undefined FUN_CODE_0548()
+     CODE1::4e48 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e4b 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e4e af a7              MOV        R7,DAT_SFR_a7                                    = ??
+     CODE1::4e50 e4                 CLR        A
+     CODE1::4e51 fc                 MOV        R4,A
+     CODE1::4e52 fd                 MOV        R5,A
+     CODE1::4e53 fe                 MOV        R6,A
+     CODE1::4e54 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e57 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e5a 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e5d 12 05 dd           LCALL      read_xmem_32_b                                   undefined read_xmem_32_b()
+     CODE1::4e60 90 00 c9           MOV        DPTR,#0xc9
+     CODE1::4e63 12 05 f9           LCALL      FUN_CODE_05f9                                    undefined FUN_CODE_05f9()
+     CODE1::4e66 12 05 48           LCALL      FUN_CODE_0548                                    undefined FUN_CODE_0548()
+     CODE1::4e69 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e6c 12 06 15           LCALL      FUN_CODE_0615                                    undefined FUN_CODE_0615()
+     CODE1::4e6f 90 00 c5           MOV        DPTR,#0xc5
+     CODE1::4e72 02 05 dd           LJMP       read_xmem_32_b                                   undefined read_xmem_32_b()
+                             -- Flow Override: CALL_RETURN (CALL_TERMINATOR)
+
+```
+
+INSERT ghidra_search_read_reg.png
+
+Identify all the read and write function to the HW of the SoC using the find
+in memory function.
+
+The next task is to adapt the intercept routines in a special assembler
+file. Don't worry, you do not need to understand assembler to do this.
+
+```
+; Assembler file to intercept register writes/reads and PHY writes/reads
+; assemble with as31
+; Compile with
+; as31 -Fbyte -Orwintercept_zoerax_hg0402xg.hex rwintercept_zoerax_hg0402xg.asm
+; ./injector zoerax_hg0402xg.bin RTLPlayground/rwintercept_zoerax_hg0402xg.hex zoerax_hg0402xg_patched.bin
+; Start at 0x3b00, where there is always some space in BANK 0
+	.equ	valptr, 0x199
+
+
+	.equ	SFR_DATA_0, 0xa7
+	.equ	SFR_DATA_8, 0xa6
+	.equ	SFR_DATA_16, 0xa5
+	.equ	SFR_DATA_24, 0xa4
+
+; Intercept Register Write
+	.org 0x4d62
+	lcall	reg_write
+	nop
+
+; Intercept Register Read
+	.org 0x4dad
+	lcall	reg_read_head
+	.org 0x4e6f
+	lcall	reg_read_tail
+
+; Intercept PHY write
+	.org 0x522c
+	lcall	phy_write
+
+; Intercept PHY read
+	.org 0x526f
+	lcall	phy_read_head
+	.org 0x5295
+	ljmp	phy_read_tail
+
+; Intercept SDS write
+	.org 0x503c
+	lcall	sds_write
+	nop
+
+; Intercept SDS read
+	.org 0x5061
+	lcall	sds_read_head
+	nop
+	.org 0x507b
+	ljmp	sds_read_tail
+
+;
+; BEGIN actual code at unused end of BANK0
+;
+	.org 0x3b00
+
+;
+; print the address of a register write. The address is in R6/R7. A and r4 can be scratched
+;
+reg_write:	
+	mov	a, #'R'
+	acall	putc
+
+	mov	a, r6
+	acall	wbyte
+
+	mov	a, r7
+	acall	wbyte
+
+	mov	a, #'-'
+	acall	putc
+
+	mov	dptr, #valptr
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 1
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 2
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 3
+	movx	a, @dptr
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	a, r7
+	mov	r5, a
+	mov	a, r6
+	mov	r4, a
+	ret
+[...]
+```
+
+The full assembler file can be found here: XXXXXXXXXX
+
+
+Once you have assembled the code, inject the bytes into the existing image,
+creating a patched version:
+```
+$ as31 -Fbyte -Orwintercept_zoerax_hg0402xg.hex rwintercept_zoerax_hg0402xg.asm
+Begin Pass #1
+Begin Pass #2
+./injector zoerax_hg0402xg.bin rwintercept_zoerax_hg0402xg.hex zoerax_hg0402xg_patched.bin
+Input file size: 1048576
+Bytes read:: 1048576
+Patched 417 bytes.
+```
+
+Now flash `zoerax_hg0402xg_patched.bin` onto device.
+
+Connect a serial adapter and plug in power. You will see:
+
+```
+$ picocom -b 9600 /dev/ttyUSB0 
+picocom v3.1
+
+port is        : /dev/ttyUSB0
+flowcontrol    : none
+baudrate is    : 9600
+parity is      : none
+databits are   : 8
+stopbits are   : 1
+escape is      : C-a
+local echo is  : no
+noinit is      : no
+noreset is     : no
+hangup is      : no
+nolock is      : no
+send_cmd is    : sz -vv
+receive_cmd is : rz -vv -E
+imap is        : 
+omap is        : 
+emap is        : crcrlf,delbs,
+logfile is     : none
+initstring     : none
+exit_after is  : not set
+exit is        : no
+
+Type [C-a] [C-h] to see available commands
+Terminal ready
+[The printout only starts once the serial peripherial has been set up. Initially its timing is off:]
+�.Ӛ�҂���������30-00005555 r6330:00005555 R6330-00005515 [RTL837X_REG_SMI_MAC_TYPE]
+[RTL837X_REG_SMI_PORT_POLLING: ]
+r6334:00000000 R6334-000000f0
+r6454:00000000 R6454-00007000
+
+[Read SoC-Revision]
+r000c:00200000 R000c-002a0000 r000c:202a6818 r000c:202a6818 R000c-20206818
+p001e.000d:ffff R02f8-0000ffff R02f4-0000fffa P000001.1e00000d:fffa p001e.000d:ffff p001e.000d:ffff
+R02f8-0000ffff R02f4-0000fff0 P000001.1e00000d:fff0
+
+[RTL837X_REG_LED_MODE being configured:]
+r6520:0021fdb0 R6520-0021e7b0 r6520:0021e7b0 R6520-0021e6b0
+
+[RLDP Leds configured via RTL837X_REG_LED_RLDP_X:]
+r65f8:00000018 R65f8-0000001b R65fc-fffff000 r6600:00000000 R6600-0000000f
+
+[RTL837X_REG_LED_GLB_IO_EN: ]
+r65dc:5fffff00 R65dc-7fffff00 r65dc:7fffff00 R65dc-77ffff00
+
+[RTL837X_PIN_MUX_0, makes serial go out of sync:]
+r7f8c:30000000 R7f8c-30000000 r7f8c:300��.Ӛ�҂���������30-00005555
+
+r6330:00005555 R6330-00005515 r6334:00000000 R6334-000000f0
+
+r6454:00000000 R6454-00007000
+
+[Read SoC-Revision (again)]
+r000c:00200000 R000c-002a0000 r000c:202a6818 r000c:202a6818 R000c-20206818
+p001e.000d:ffff R02f8-0000ffff R02f4-0000fffa P000001.1e00000d:fffa p001e.000d:ffff p001e.000d:ffff
+R02f8-0000ffff R02f4-0000fff0
+P000001.1e00000d:fff0
+
+#### LED configuration ########
+[RTL837X_REG_LED_MODE being configured (final):]
+r6520:0021fdb0 R6520-0021e7b0 r6520:0021e7b0 R6520-0021e6b0
+
+[More RTL837X_REG_LED_RLDP]
+r65f8:00000018 R65f8-0000001b R65fc-fffff000 r6600:00000000 R6600-0000000f
+
+[RTL837X_REG_LED_GLB_IO_EN]
+r65dc:5fffff00 R65dc-7fffff00 r65dc:7fffff00 R65dc-77ffff00
+
+[RTL837X_PIN_MUX_0
+r7f8c:30000000 R7f8c-30000000 r7f8c:30000000 R7f8c-38000000
+
+[RTL837X_LED_PORT_SET_SEL]
+r654c:00000000 R654c-00010000
+
+[RTL837X_REG_LED1_0_SET0]
+R6548-00000141
+
+[RTL837X_REG_LED3_2_SET0]
+r6544:01411000 R6544-01410174
+
+[RTL837X_REG_LED1_0_SET1]
+r6540:00440070 R6540-0044017f
+
+[RTL837X_REG_LED3_0_SET1]
+r6528:00000000 R6528-000f0000
+
+[SDS 0 being configure:]
+r7b20:00000bff R7b20-000003ff r7b20:000003ff R7b20-000003fa r7b20:000003fa R7b20-000003fa
+Q002110:4480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 
+Q003614:003f Q003610:0200 Q002e04:0080 Q002e06:0408 Q002e07:020d Q002e09:0601 
+Q002e0b:222c Q002e0c:a217 Q002e0d:fe40 Q002e15:f5c1 Q002e16:0443 Q002e1d:abb0 
+Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 
+Q000603:c45c Q00061f:2100 q001f0b:0003 Q001f0b:000f q002000:0000 Q002000:0030 
+q002000:0030 Q002000:0010 q002000:0010 Q002000:0050 q002000:0050 Q002000:00d0 
+q002000:00d0 Q002000:0cd0 q002000:0cd0 Q002000:04d0 q002000:04d0 Q002000:04d0 
+q002000:04d0 Q002000:0cd0 q002000:0cd0 Q002000:00d0 q002000:00d0 Q002000:00d0 
+q002000:00d0 Q002000:0050 q002000:0050 Q002000:0010 q002000:0010 Q002000:0010 
+q002000:0010 Q002000:0030 q002000:0030 Q002000:0000 q001f00:0000 Q001f00:000b 
+q001f00:000b Q001f00:0000
+
+[SDS 1 being configured]
+r7b20:000003fa R7b20-000003fa r7b20:000003fa R7b20-0000035a r7b20:0000035a R7b20-0000035a
+Q012110:4480 Q012113:0400 Q012118:6d02 Q01211b:424e Q01211d:0002 Q01361c:1390 
+Q013614:003f Q013610:0200 Q012e04:0080 Q012e06:0408 Q012e07:020d Q012e09:0601 
+Q012e0b:222c Q012e0c:a217 Q012e0d:fe40 Q012e15:f5c1 Q012e16:0443 Q012e1d:abb0 
+Q010612:5078 Q010706:9401 Q010708:9401 Q01070a:9401 Q01070c:9401 Q011f0b:0003 
+Q010603:c45c Q01061f:2100 q011f0b:0003 Q011f0b:000f q012000:0000 Q012000:0030 
+q012000:0030 Q012000:0010 q012000:0010 Q012000:0050 q012000:0050 Q012000:00d0 
+q012000:00d0 Q012000:0cd0 q012000:0cd0 Q012000:04d0 q012000:04d0 Q012000:04d0 
+q012000:04d0 Q012000:0cd0 q012000:0cd0 Q012000:00d0 q012000:00d0 Q012000:00d0 
+q012000:00d0 Q012000:0050 q012000:0050 Q012000:0010 q012000:0010 Q012000:0010 
+q012000:0010 Q012000:0030 q012000:0030 Q012000:0000 q011f00:0000 Q011f00:000b 
+q011f00:000b Q011f00:0000 q012100:4902 Q012100:4906 q013605:0000 Q013605:4000 
+Q011f02:001f q011f15:0096 q002100:4902 Q002100:4906 q003605:0000 Q003605:4000 
+Q001f02:001f q001f15:00a6
+
+r0a90:000000f3 R0a90-000000fc P0000f0.1f00a610:2858 r5fd4:0002914a 
+R5fd4-001a914a r1538:00000e33 R1538-00000e37 r1538:00000e37 R1538-00000e37 
+r1538:00000e37 R1538-00000f37 r1638:00000e33 R1638-00000e37 r1638:00000e37 
+R1638-00000e37 r1638:00000e37 R1638-00000f37 r1738:00000e33 R1738-00000e37 
+r1738:00000e37 R1738-00000e37 r1738:00000e37 R1738-00000f37 r1838:00000e33 
+R1838-00000e37 r1838:00000e37 R1838-00000e37 r1838:00000e37 R1838-00000f37 
+r1938:00000e33 R1938-00000e37 r1938:00000e37 R1938-00000e37 r1938:00000e37 
+R1938-00000f37 r1a38:00000e33 R1a38-00000e37 r1a38:00000e37 R1a38-00000e37 
+r1a38:00000e37 R1a38-00000f37 r0b7c:000000d8 R0b7c-000000f8 R7124-00001050 
+R7128-00001050 R712c-00001050 R7130-00001050 R7134-00001050 R7138-00001050 
+R713c-00001050 R7140-00001050 R7144-00001050 R7148-00001050 r6040:00000030 
+R6040-00000031 p041f.a436:8195 P000010.1f00a436:0005 p041f.a438:02d4 
+P000010.1f00a436:801e p041f.a438:0000 p041f.b820:0000 P000010.1f00b820:0010 
+p041f.b800:00c0 p041f.a436:801e P000010.1f00a436:8023 p041f.a438:0000 
+P000010.1f00a438:1802 p041f.a436:8025 
+
+[PHY with ID 5 being patched] P000010.1f00a436:b82e p041f.a438:0000 
+P000010.1f00a438:0001 p041f.b820:0010 P000010.1f00b820:0090 
+P000010.1f00a436:a016 P000010.1f00a438:0000 P000010.1f00a436:a012 
+P000010.1f00a438:0000 P000010.1f00a436:a014 P000010.1f00a438:1800 
+P000010.1f00a438:8010 P000010.1f00a438:1800 P000010.1f00a438:8013 
+P000010.1f00a438:1800 P000010.1f00a438:8026 P000010.1f00a438:1800 
+P000010.1f00a438:802a P000010.1f00a438:1800 P000010.1f00a438:802e 
+P000010.1f00a438:1800 P000010.1f00a438:802e P000010.1f00a438:1800 
+P000010.1f00a438:802e P000010.1f00a438:1800 P000010.1f00a438:802e 
+...
+```
+Where:
+```
+r: read-reg
+R: write-reg
+q: read SDS
+Q: write SDS
+p: read PHY
+P: write SDS
+```
+
+The LED configuration has been marked above. We now write exactly those registers
+into the registers of `rtlplayground.c` on startup:
+
+```
+[...]
+	set_sys_led_state(SYS_LED_ON);
+
+	// [RTL837X_REG_LED_MODE being configured (final):]
+	// r6520:0021fdb0 R6520-0021e7b0 r6520:0021e7b0 R6520-0021e6b0
+	REG_SET(RTL837X_REG_LED_MODE, 0x0021e6b0);
+
+	// [More RTL837X_REG_LED_RLDP]
+	// r65f8:00000018 R65f8-0000001b R65fc-fffff000 r6600:00000000 R6600-0000000f
+	REG_SET(0x65f8, 0x0000001b);
+	REG_SET(0x65fc, 0xfffff000);
+	REG_SET(0x6600, 0x0000000f);
+
+	// [RTL837X_REG_LED_GLB_IO_EN]
+	// r65dc:5fffff00 R65dc-7fffff00 r65dc:7fffff00 R65dc-77ffff00
+	REG_SET(0x65dc, 0x77ffff00);
+
+	// [RTL837X_PIN_MUX_0
+	// r7f8c:30000000 R7f8c-30000000 r7f8c:30000000 R7f8c-38000000
+	REG_SET(0x7f8c, 0x38000000);
+
+	// [RTL837X_LED_PORT_SET_SEL]
+	// r654c:00000000 R654c-00010000
+	REG_SET(0x654c, 0x00010040);
+
+	// [RTL837X_REG_LED1_0_SET0]
+	// R6548-00000141
+	REG_SET(0x6548, 0x00000141);
+
+	// [RTL837X_REG_LED3_2_SET0]
+	// r6544:01411000 R6544-01410174
+	REG_SET(0x6544, 0x01410174);
+
+	// [RTL837X_REG_LED1_0_SET1]
+	// r6540:00440070 R6540-0044017f
+	REG_SET(0x6540, 0x0044017f);
+
+	// [RTL837X_REG_LED3_0_SET1]
+	// r6528:00000000 R6528-000f0000
+	REG_SET(0x6528, 0x000f0000);
+
+	cmd_editor_init();
+[...]
+```
+
+Create an initial configuraiton for your device by copying over an existing one
+for the same device type, i.e. same port-configuraiton and same SoC,
+give it a new name. Make sure that the led_mux_custom and led_mux fields are not
+used, because our device does not customize the LED muxes.
+
+Compile and flash onto your device.
+
+Now, boot the switch and issue the `leds`command, which will print out:
+```
+RTL837X_PIN_MUX_0: 0x38000000
+RTL837X_REG_LED_GLB_IO_EN: 0x77ffff00
+RTL837X_REG_LED1_0_SET0: 0x00000141
+RTL837X_REG_LED3_2_SET0: 0x01410174
+RTL837X_REG_LED1_0_SET1: 0x0044017f
+RTL837X_REG_LED3_2_SET1: 0x18000040
+RTL837X_REG_LED1_0_SET2: 0x00000000
+RTL837X_REG_LED3_2_SET2: 0x00000000
+RTL837X_REG_LED1_0_SET3: 0x00000000
+RTL837X_REG_LED3_2_SET3: 0x00000000
+RTL837X_REG_LED3_0_SET1: 0x000f0000
+RTL837X_REG_LED3_0_SET3: 0x00000000
+RTL837X_LED_PORT_SET_SEL: 0x00010040
+RTL837X_REG_LED_GLB_MUX_1: 0x3fffffff
+RTL837X_REG_LED_GLB_MUX_2: 0x0c3fffff
+RTL837X_REG_LED_GLB_MUX_3: 0x1245038d
+RTL837X_REG_LED_GLB_MUX_4: 0x19616554
+RTL837X_REG_LED_GLB_MUX_5: 0x2079d71a
+RTL837X_REG_LED_GLB_MUX_6: 0x000238a1
+RTL837X_REG_LED_GLB_ACTIVE: 0x3ffbedff
+RTL837X_REG_LED_MODE: 0x0021e6b0
+LED pad Configuration:
+00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 
+3f 3f 3f 3f 3f 3f 3f 3f 0f 0c 0d 0e 10 11 12 14 15 16 18 19 1a 1c 1d 1e 20 21 22 23 
+LED-set Configuration:
+LED-ID          0               1               2               3
+SET 0:     000141          000000          000174          000141
+SET 1:     0f017f          000044          000040          001800
+SET 2:     000000          000000          000000          000000
+SET 3:     000000          000000          000000          000000
+Port 3: SET 1: ( 2G5 TWO_1G 1G 500M 100M 10M LINK ACT 10G TWO_5G 5G TWO_2G5), ( 1G LINK), ( LINK), ( COL DUPLEX), 
+Port 4: SET 0: ( 2G5 LINK ACT), (), ( 1G 100M 10M LINK ACT), ( 2G5 LINK ACT), 
+Port 5: SET 0: ( 2G5 LINK ACT), (), ( 1G 100M 10M LINK ACT), ( 2G5 LINK ACT), 
+Port 6: SET 0: ( 2G5 LINK ACT), (), ( 1G 100M 10M LINK ACT), ( 2G5 LINK ACT), 
+Port 7: SET 0: ( 2G5 LINK ACT), (), ( 1G 100M 10M LINK ACT), ( 2G5 LINK ACT), 
+Port 8: SET 1: ( 2G5 TWO_1G 1G 500M 100M 10M LINK ACT 10G TWO_5G 5G TWO_2G5), ( 1G LINK), ( LINK), ( COL DUPLEX), 
+
+```
+Together with the GPIO information, this will give you the following machine configuration:
+```
+_code const struct machine machine = {
+	.machine_name = "ZOERAX HG0402XG",
+	.isRTL8373 = 0,
+	.min_port = 3,
+	.max_port = 8,
+	.n_sfp = 2,
+	.log_to_phys_port = {0, 0, 0, 5, 1, 2, 3, 4, 6},
+	.phys_to_log_port = {4, 5, 6, 7, 3, 8, 0, 0, 0},
+	.is_sfp = {0, 0, 0, 1, 0, 0, 0, 0, 2},
+	// Left SFP port (5)
+	.sfp_port[0].pin_detect = GPIO30_ACL_BIT3_EN,
+	.sfp_port[0].pin_los = GPIO_NA,
+	.sfp_port[0].pin_tx_disable = GPIO_NA,
+	.sfp_port[0].sds = 1,
+	.sfp_port[0].i2c = I2CBUS( GPIO39_I2C_SDA4, GPIO40_I2C_SCL3_MDC1 ),
+	// Right SFP port (6)
+	.sfp_port[1].pin_detect = GPIO50_I2C_SCL2_UART1_TX,
+	.sfp_port[1].pin_los = GPIO_NA,
+	.sfp_port[1].pin_tx_disable = GPIO_NA,
+	.sfp_port[1].sds = 0,
+	.sfp_port[1].i2c = I2CBUS( GPIO41_I2C_SDA3_MDIO1, GPIO40_I2C_SCL3_MDC1 ),
+	.reset_pin = GPIO_NA,
+	.high_leds = { .mux = LED_27 | LED_29, .enable = LED_28_SYS | LED_29 },
+	.port_led_set = { 0, 0, 0, 1, 0, 0, 0, 0, 1},
+	/* On Ethernet: Left led is orange, right green
+	 * 100M and 1G give right led green with activity
+	 * 2.5GBit adds solid left orange LED
+	 * LEDs for the SFP-ports are the same as for the Ethernet ports
+	*/
+	.led_sets = { { LEDS_2G5 | LEDS_LINK | LEDS_ACT,
+			0,
+			LEDS_1G | LEDS_100M | LEDS_10M | LEDS_LINK | LEDS_ACT,
+			LEDS_2G5 | LEDS_LINK | LEDS_ACT
+		      },
+		      { LEDS_2G5 | LEDS_TWO_PAIR_1G | LEDS_1G | LEDS_500M | LEDS_100M | LEDS_10M |
+			LEDS_LINK | LEDS_ACT | LEDS_10G | LEDS_TWO_PAIR_5G | LEDS_5G | LEDS_TWO_PAIR_2G5,
+			LEDS_1G | LEDS_LINK,
+			LEDS_LINK,
+			LEDS_COL | LEDS_DUPLEX
+		      } 
+		    }
+		    
+};
+```
+
+
@@ -29,6 +29,8 @@ The following devices have been tested and are fully working:
 | Mokerlink| 2G040210GSM     | Yes     | [2M-PCB43-V1.1](devices/2M-PCB43-V1.1.md)                                 |       | 4 + 2 |
 | Mokerlink| ZX-SWTGW218AS   | Yes     | [SWTG118AS-V2.0-16029](devices/SWTGW218AS.md)                             | 2M    | 8 + 1 |
 | MokerLink| POE-2G080110GS  | No      | [2M-PCB51-ML-V1.1](devices/2M-PCB51-ML-V1_1.md)                           | 4M    | 8 + 1 |
+| Binardat | 2G06-04210GSM    | No      | [PCB-SWTG024AS-A-2.0.1](devices/ONT-S207CW-62TS-SE.md)                 | 0.5M  | 4 + 2 |
+| ONT      | ONT-S207CW-62TS-SE | No   | [PCB-SWTG024AS-A-2.0.1](devices/ONT-S207CW-62TS-SE.md)                 | 0.5M  | 4 + 2 |
 | Netcore  | GS9             | No      | [PB-2132](devices/PB-2132.md)                                             | 4M    | 8 + 1 |
 | Ruiying  | RY-4GT-2SX      | No      | [FG-4GT-2SX_V2.0](devices/FG-4GT-2SX_V2.0.md)                             | 4M    | 4 + 2 |
 | Ruiying  | RY-8GT-1SX      | No      | [FG-8GT-1SX](devices/FG-8GT-1SX.md)                                       | 1M    | 8 + 1 |
@@ -3,7 +3,7 @@ var LANG={
 en:{
 nav_dash:"Dashboard",nav_ports:"Ports",nav_stp:"Spanning tree",nav_stats:"Statistics",
 nav_vlan:"VLANs",nav_l2:"MAC table",nav_mirror:"Mirroring",nav_isolate:"Isolation",nav_lag:"LAG",nav_eee:"EEE",
-nav_bw:"Bandwidth",nav_system:"System",nav_fw:"Firmware",
+nav_bw:"Bandwidth",nav_system:"System",nav_fw:"Firmware",nav_lldp:"LLDP",
 hdr_dirty:"unsaved changes",hdr_dirty_t:"Running config differs from startup config",
 hdr_save:"Save to flash",hdr_save_t:"Persist running configuration to flash",
 th_auto:"System",th_auto_sel:"System (Selenized)",sy_display:"Display",sy_theme:"Theme",sy_display_note:"Stored in this browser only.",th_light:"Light",th_dark:"Dark",
@@ -40,6 +40,7 @@ stp_en_q:"Enable spanning tree?",
 stp_en_d:"Ports start blocked and take up to twice the forward delay to reach forwarding; edge ports recover immediately.",
 stp_dis_q:"Disable spanning tree?",stp_dis_d:"All ports go straight to forwarding; loop protection is lost.",
 stp_cost_err:"Path cost must be 0-200000000",
+lldp_enabled: "LLDP Enabled",lldp_title:"Service Status",lldp_portname:"Name",lldp_enable:"Send Frames",
 st_title:"Port statistics",st_h:"totals since boot",st_txg:"TX good",st_txb:"TX bad",st_rxg:"RX good",
 st_rxb:"RX bad",st_details:"Details",st_counters:"MIB counters",st_nonzero:"non-zero only",
 st_autoref:"auto-refresh",st_counter:"Counter",st_value:"Value",st_fail:"failed to load counters",
@@ -788,6 +789,7 @@ var CONF_CMDS=[
  /^ingress(\s+\d{1,2}[tua])+$/,/^ingress\s+[tua]$/,
  /^port\s+\d{1,2}\s+(10m|100m|1g|2g5|5g|10g|auto|on|off)(\s+(half|full))?$/,
  /^port\s+\d{1,2}\s+name\s+\S+$/,
+  /^port\s+\d{1,2}\s+lldp\s+(permit|block)+$/,
  /^eee\s+(on|off)(\s+\d{1,2})?(\s+(100m|1g|2g5))?$/,
  /^mirror(\s+\d{1,2})(\s+\d{1,2}[tr]?)+$/,/^mirror\s+off$/,
  /^lag\s+[1-4](\s+\d{1,2})+$/,/^lag\s+[1-4]\s+d$/,/^laghash\s+[1-4](\s+\w+)+$/,
@@ -798,7 +800,7 @@ var CONF_CMDS=[
  /^stp\s+(port\s+\d{1,2}|lag\s+[1-4])\s+cost\s+\d{1,9}$/,/^stp\s+(port\s+\d{1,2}|lag\s+[1-4])\s+prio\s+\d{1,3}$/,
  /^stp\s+(port\s+\d{1,2}|lag\s+[1-4])\s+guard\s+(none|bpdu|root)$/,/^stp\s+(port\s+\d{1,2}|lag\s+[1-4])\s+filter\s+(on|off)$/,
  /^stp\s+(port\s+\d{1,2}|lag\s+[1-4])\s+p2p\s+(auto|on|off)$/,
-  /^igmp\s+(on|off)$/,/^mtu\s+\d{1,2}\s+\d+$/,
+  /^igmp\s+(on|off)$/,/^mtu\s+\d{1,2}\s+\d+$/,/^lldp\s+(on|off)$/,
  /^bw\s+(in|out)\s+\d{1,2}\s+\S+$/,
  /^storm\s+\d{1,2}\s+(bcast|mcast|ucast|umcast)\s+(off|\d{1,8}\s+(pps|kbps))$/,
 ];
@@ -860,6 +862,7 @@ var TABS=[
  {id:"mirror",icon:"M12 3v18M7 8l-4 4 4 4M17 8l4 4-4 4"},
  {id:"isolate",icon:"M4 4h6v6H4zM14 14h6v6h-6zM14 4h6v6h-6zM4 14h6v6H4z"},
  {id:"lag",   icon:"M7 8a4 4 0 100 8h3M17 8a4 4 0 110 8h-3M9 12h6"},
+  {id:"lldp",  icon:"M11 12a1 1 0 002 0 1 1 0 00-2 0M8.5 8.5a5 5 0 000 7M15.5 8.5a5 5 0 010 7M5.6 5.6a9 9 0 000 12.8M18.4 5.6a9 9 0 010 12.8"},
  {id:"eee",   icon:"M13 2L4 14h6l-1 8 9-12h-6z"},
  {id:"bw",    icon:"M4 18a8 8 0 0116 0M12 18l4-6"},
  {id:"system",icon:"M12 8a4 4 0 100 8 4 4 0 000-8zM4 12h2M18 12h2M12 4v2M12 18v2M6 6l1.5 1.5M16.5 16.5L18 18M18 6l-1.5 1.5M7.5 16.5L6 18"},
@@ -1835,6 +1838,32 @@ function lagApply(g){
 }
 tabHooks.lag={enter:function(){needPorts(function(){buildLag();lagLoad().catch(function(){})})}};

+
+function lldpLoad(){
+  return getJSON("/lldp.json").then(function(s){
+    $("lldp_en").checked=s.on;
+    var tb=$("lldp_table").tBodies[0];tb.innerHTML="";
+    byPort(s.portStatus).forEach(function(p){
+      var tr=tb.insertRow();
+      tr.insertCell().textContent=p.portNum;
+      tr.insertCell().textContent=p.name;
+      var sw=h("label",{class:"switch"},[
+        h("input",{type:"checkbox",onchange:function(){
+          postCmd("port "+p.portNum+" lldp "+(this.checked?"permit":"block"))
+            .then(function(){setTimeout(lldpLoad,300)}).catch(function(){});
+        }}),h("i")]);
+      sw.firstChild.checked=p.permitted;
+      tr.insertCell().appendChild(sw);
+    });
+  });
+}
+
+$("lldp_en").addEventListener("change",function(){
+  var el=this;
+  postCmd("lldp "+(el.checked?"on":"off")).catch(function(){el.checked=!el.checked});
+});
+tabHooks.lldp={enter:lldpLoad};
+
 function eeeFlags(bits){
  var b=parseInt(bits,2);
  return["100M","1G","2.5G"].map(function(s,i){
@@ -331,6 +331,17 @@ button.danger{background:var(--bad);color:#fff;border-color:transparent}
      </div>
    </section>

+    <section class="tab" id="tab-lldp">
+      <div class="card"><h2 data-i18n="lldp_title">LLDP</h2>
+        <label class="row"><span class="lb" data-i18n="lldp_enabled">Enabled</span>
+          <span class="switch"><input type="checkbox" id="lldp_en"><i></i></span>
+        </label>
+        <div class="scrollx"><table class="t" id="lldp_table">
+          <thead><tr><th data-i18n="c_port">Port Number</th><th data-i18n="lldp_portname">Name</th><th data-i18n="lldp_enable">Send Frames</th></tr></thead>
+          <tbody></tbody></table></div>
+      </div>
+    </section>
+
    <section class="tab" id="tab-isolate">
      <div class="card"><h2 data-i18n="iso_title">Port isolation</h2>
        <p class="small mut" style="margin-bottom:10px" data-i18n="iso_intro">A frame entering a port may only leave through the ports ticked in its row.</p>
@@ -1034,6 +1034,8 @@ void httpd_appcall(void)
 				send_lag();
 			} else if (is_word(q, "/stp.json")) {
 				send_stp();
+			} else if (is_word(q, "/lldp.json")) {
+				send_lldp();
 			} else if (is_word(q, "/vlanlist")) {
 				send_vlanlist();
 			} else if (is_word(q, "/config")) {
@@ -49,6 +49,9 @@ extern __xdata char sfp_module_model[2][17];
 extern __xdata char sfp_module_serial[2][17];
 extern __xdata uint8_t sfp_options[2];

+extern __xdata uint16_t lldp_logical_port_status;
+extern __xdata bool lldp_enabled;
+
 __code const uint8_t * __code const HTTP_RESPONCE_JSON = "HTTP/1.1 200 OK\r\nConnection: close\r\nContent-Type: application/json\r\n\r\n";
 __code const uint8_t * __code const HTTP_RESPONCE_TXT = "HTTP/1.1 200 OK\r\nConnection: close\r\nContent-Type: text/plain\r\n\r\n";

@@ -619,7 +622,6 @@ static void bridge_to_html(void)
 		byte_to_html(pi_mac[i]);
 }

-
 void send_stp(void)
 {
 	uint8_t i, j, st, dsg;
@@ -734,8 +736,37 @@ void send_stp(void)
 	slen += strtox(outbuf + slen, "]}");
 }

+void send_lldp(void)
+{
+	dbg_string("send_lldp called\n");
+	slen = strtox(outbuf, HTTP_RESPONCE_JSON);

+	slen += strtox(outbuf + slen, "{\"on\":");
+	bool_to_html(lldp_enabled);
+	slen += strtox(outbuf + slen, ",\"portStatus\":[");

+	for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
+		slen += strtox(outbuf + slen, "{\"portNum\":");
+		itoa_html(machine.log_to_phys_port[i]);
+
+		slen += strtox(outbuf + slen, ",\"logPort\":");
+		itoa_html(i);
+		slen += strtox(outbuf + slen, ",\"name\":\"");
+		for (uint8_t j = 0; j < PORT_NAME_SIZE && port_names[i][j]; j++) {
+			json_char_to_html(port_names[i][j]);
+		}
+
+		slen += strtox(outbuf + slen, "\",\"permitted\":");
+		bool_to_html(1 & (lldp_logical_port_status >> i));
+		slen += strtox(outbuf + slen, "}");
+
+		if (i < machine.max_port)
+			char_to_html(',');
+		else
+			char_to_html(']');
+	}
+	char_to_html('}');
+}

 void send_eee(void)
 {
@@ -23,6 +23,7 @@ void send_config(void);
 void send_cmd_log(void);
 void send_lag(void);
 void send_stp(void);
+void send_lldp(void);
 void send_vlanlist(void);

 /*  Convert only the lower nibble to ascii HEX char.
@@ -935,6 +935,68 @@ __code const struct machine machine = {
            },
    };

+#elif defined MACHINE_ONT_S207CW_62TS_SE
+
+__code const struct machine machine = {
+    .machine_name = "ONT-S207CW-62TS-SE / Binardat 2G06-04210GSM / Binardat 2G06-04210GS",
+    .isRTL8373 = 0,
+    .min_port = 3,
+    .max_port = 8,
+    .n_sfp = 2,
+    .log_to_phys_port = {0, 0, 0, 5, 4, 3, 2, 1, 6},
+    .phys_to_log_port = {7, 6, 5, 4, 3, 8, 0, 0, 0},
+    .is_sfp = {0, 0, 0, 1, 0, 0, 0, 0, 2},
+
+    // SFP port on SDS0 / logical port 3
+    .sfp_port[0].pin_detect = GPIO37,
+    .sfp_port[0].pin_los = GPIO_NA,
+    .sfp_port[0].pin_tx_disable = GPIO_NA,
+    .sfp_port[0].sds = 0,
+    .sfp_port[0].i2c = I2CBUS( GPIO41_I2C_SDA3_MDIO1, GPIO40_I2C_SCL3_MDC1 ),
+
+    // SFP port on SDS1 / logical port 8
+    .sfp_port[1].pin_detect = GPIO38,
+    .sfp_port[1].pin_los = GPIO_NA,
+    .sfp_port[1].pin_tx_disable = GPIO_NA,
+    .sfp_port[1].sds = 1,
+    .sfp_port[1].i2c = I2CBUS( GPIO39_I2C_SDA4, GPIO40_I2C_SCL3_MDC1 ),
+
+    .reset_pin = GPIO_NA,
+    .high_leds = { .mux =  LED_28_SYS | LED_29, .enable = LED_27 | LED_28_SYS | LED_29 },
+    .port_led_set = { 0, 0, 0, 3, 0, 0, 2, 2, 3},
+    .mac_flash_offset = 0x1FC000,
+    .led_sets = {
+        { // RJ45 Ports 3-4 (normal wiring)
+            LEDS_1G | LEDS_100M | LEDS_10M | LEDS_LINK | LEDS_ACT,
+            LEDS_2G5 | LEDS_LINK | LEDS_ACT,
+            0,
+            0
+        },
+        { // Unused
+            0,
+            0,
+            0,
+            0
+        },
+        { // RJ45 Ports 1-2 (reversed wiring)
+            LEDS_2G5 | LEDS_LINK | LEDS_ACT,
+            LEDS_1G | LEDS_100M | LEDS_10M | LEDS_LINK | LEDS_ACT,
+            0,
+            0
+        },
+        { // SFP Ports 5-6
+            LEDS_10G | LEDS_LINK | LEDS_ACT,
+            LEDS_2G5 | LEDS_1G | LEDS_LINK | LEDS_ACT,
+            0,
+            0
+        },
+    },
+    .led_mux_custom = 1,
+    .led_mux = {
+        0x00,0x01,0x04,0x05,0x08,0x09,0x0c,0x3f,0x0d,0x10,0x11,0x0e,0x14,0x11,0x12,0x15,0x15,0x16,0x18,0x19,0x1a,0x19,0x1d,0x1e,0x1c,0x1d,0x20,0x21
+    },
+};
+
 #elif defined MACHINE_SWTG024AS_A_2_0_1_5C_1SFP
 __code const struct machine machine = {
    .machine_name = "SWTG024AS-A-V2.0.1-5C-1SFP",
@@ -41,6 +41,7 @@
 // #define MACHINE_HI_K0801WS
 // #define MACHINE_FNS1200P
 // #define MACHINE_PCB_SWTG024AS_A_2_0_1
+// #define MACHINE_ONT_S207CW_62TS_SE
 // #define MACHINE_SWTG024AS_A_2_0_1_5C_1SFP
 // #define MACHINE_SWTG024AS_V2_0
 // #define MACHINE_FG_4GT_2SX_V2_0
@@ -131,6 +131,7 @@ struct flash_region_t {
 };

 extern __xdata char port_names[9][PORT_NAME_SIZE];
+extern __xdata uint16_t lldp_logical_port_status;

 extern __xdata bool stp_enabled;

@@ -24,149 +24,6 @@ extern __code const struct machine machine;

 extern __xdata uint8_t sfr_data[4];

-void leds_dump(void) __banked
-{
-	print_string("RTL837X_PIN_MUX_0: "); print_reg(RTL837X_PIN_MUX_0); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_IO_EN: "); print_reg(RTL837X_REG_LED_GLB_IO_EN); write_char('\n');
-	print_string("RTL837X_REG_LED1_0_SET0: "); print_reg(RTL837X_REG_LED1_0_SET0); write_char('\n');
-	print_string("RTL837X_REG_LED3_2_SET0: "); print_reg(RTL837X_REG_LED3_2_SET0); write_char('\n');
-	print_string("RTL837X_REG_LED1_0_SET1: "); print_reg(RTL837X_REG_LED1_0_SET1); write_char('\n');
-	print_string("RTL837X_REG_LED3_2_SET1: "); print_reg(RTL837X_REG_LED3_2_SET1); write_char('\n');
-	print_string("RTL837X_REG_LED1_0_SET2: "); print_reg(RTL837X_REG_LED1_0_SET2); write_char('\n');
-	print_string("RTL837X_REG_LED3_2_SET2: "); print_reg(RTL837X_REG_LED3_2_SET2); write_char('\n');
-	print_string("RTL837X_REG_LED1_0_SET3: "); print_reg(RTL837X_REG_LED1_0_SET3); write_char('\n');
-	print_string("RTL837X_REG_LED3_2_SET3: "); print_reg(RTL837X_REG_LED3_2_SET3); write_char('\n');
-	print_string("RTL837X_REG_LED3_0_SET1: "); print_reg(RTL837X_REG_LED3_0_SET1); write_char('\n');
-	print_string("RTL837X_REG_LED3_0_SET3: "); print_reg(RTL837X_REG_LED3_0_SET3); write_char('\n');
-	print_string("RTL837X_LED_PORT_SET_SEL: "); print_reg(RTL837X_LED_PORT_SET_SEL); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_1: "); print_reg(RTL837X_REG_LED_GLB_MUX_1); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_2: "); print_reg(RTL837X_REG_LED_GLB_MUX_2); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_3: "); print_reg(RTL837X_REG_LED_GLB_MUX_3); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_4: "); print_reg(RTL837X_REG_LED_GLB_MUX_4); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_5: "); print_reg(RTL837X_REG_LED_GLB_MUX_5); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_MUX_6: "); print_reg(RTL837X_REG_LED_GLB_MUX_6); write_char('\n');
-	print_string("RTL837X_REG_LED_GLB_ACTIVE: "); print_reg(RTL837X_REG_LED_GLB_ACTIVE); write_char('\n');
-	print_string("RTL837X_REG_LED_MODE: "); print_reg(RTL837X_REG_LED_MODE); write_char('\n');
-	print_string("LED pad Configuration:\n");
-	for (uint8_t i = 0; i < 28; i++) {
-		print_byte(i);
-		write_char(' ');
-	}
-	write_char('\n');
-	for (uint8_t i = 0; i < 28; i++) {
-		switch (i % 5) {
-		case 0:  // 0
-			reg_read_m(RTL837X_REG_LED_GLB_MUX_1 + (i / 5) * 4);
-			print_byte(sfr_data[3] & 0x3f);
-			break;
-		case 1:  // 6
-			print_byte(((sfr_data[3] >> 6) | (sfr_data[2] << 2)) & 0x3f);
-			break;
-		case 2:  // 12
-			print_byte(((sfr_data[1] << 4) | (sfr_data[2] >> 4)) & 0x3f);
-			break;
-		case 3:  // 18
-			print_byte((sfr_data[1] >> 2) & 0x3f);
-			break;
-		case 4:  // 24
-			print_byte(sfr_data[0] & 0x3f);
-			break;
-		}
-		write_char(' ');
-	}
-	write_char('\n');
-	print_string("LED-set Configuration:\n");
-	print_string("LED-ID\t\t0\t\t1\t\t2\t\t3\n");
-	for (__xdata uint8_t set = 0; set < 4; set++) {
-		print_string("SET "); write_char('0' + set); write_char(':');
-		for (__xdata uint8_t ledid = 0; ledid < 4; ledid++) {
-			print_string("\t   ");
-			uint8_t b;
-			if (set < 2) {
-				reg_read_m(RTL837X_REG_LED3_0_SET1);
-				b = sfr_data[3-((set << 1) + (ledid >> 1))];
-				print_byte(ledid & 1 ? b >> 4 : b & 0xf);
-			} else {
-				reg_read_m(RTL837X_REG_LED3_0_SET3);
-				b = sfr_data[3-(((set-2) << 1) + (ledid >> 1))];
-				print_byte(ledid & 1 ? b >> 4 : b & 0xf);
-			}
-			reg_read_m(RTL837X_REG_LED1_0_SET0 - set * 8 - ((ledid >> 1) * 4));
-			if (! (ledid & 1)) { // LEDID 0, 2
-				print_byte(sfr_data[2]); print_byte(sfr_data[3]);
-			} else {
-				print_byte(sfr_data[0]); print_byte(sfr_data[1]);
-			}
-		}
-		write_char('\n');
-	}
-	for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
-		reg_read_m(RTL837X_LED_PORT_SET_SEL);
-		__xdata uint8_t set = sfr_data[3 - (i >> 2)];
-		set = (set >> ((i & 3) << 1));
-		print_string("Port "); write_char('0' + i); print_string(": SET ");
-		write_char('0' + set);
-		print_string(": ");
-		for (__xdata uint8_t ledid = 0; ledid < 4; ledid++) {
-			write_char('(');
-			reg_read_m(RTL837X_REG_LED1_0_SET0 - set * 8 - ((ledid >> 1) * 4));
-			if (ledid & 1) {  // LEDID 1, 3
-				sfr_data[2] = sfr_data[0];
-				sfr_data[3] = sfr_data[1];
-			}
-			if (sfr_data[3] & 0x01)
-				print_string(" 2G5");
-			if (sfr_data[3] & 0x02)
-				print_string(" TWO_1G");
-			if (sfr_data[3] & 0x04)
-				print_string(" 1G");
-			if (sfr_data[3] & 0x08)
-				print_string(" 500M");
-			if (sfr_data[3] & 0x10)
-				print_string(" 100M");
-			if (sfr_data[3] & 0x20)
-				print_string(" 10M");
-			if (sfr_data[3] & 0x40)
-				print_string(" LINK");
-			if (sfr_data[3] & 0x80)
-				print_string(" LINK_FLASH");
-			if (sfr_data[2] & 0x01)
-				print_string(" ACT");
-			if (sfr_data[2] & 0x02)
-				print_string(" RX");
-			if (sfr_data[2] & 0x04)
-				print_string(" TX");
-			if (sfr_data[2] & 0x08)
-				print_string(" COL");
-			if (sfr_data[2] & 0x10)
-				print_string(" DUPLEX");
-			if (sfr_data[2] & 0x20)
-				print_string(" TRAINING");
-			if (sfr_data[2] & 0x40)
-				print_string(" MASTER");
-			__xdata uint8_t b;
-			if (set < 2) {
-				reg_read_m(RTL837X_REG_LED3_0_SET1);
-				b = sfr_data[3-((set << 1) + (ledid >> 1))];
-			} else {
-				reg_read_m(RTL837X_REG_LED3_0_SET3);
-				b = sfr_data[3-(((set-2) << 1) + (ledid >> 1))];
-			}
-			b = ledid & 1 ? b >> 4 : b & 0xf;
-			if (b & 0x1)
-				print_string(" 10G");
-			if (b & 0x2)
-				print_string(" TWO_5G");
-			if (b & 0x4)
-				print_string(" 5G");
-			if (b & 0x8)
-				print_string(" TWO_2G5");
-			print_string("), ");
-		}
-		write_char('\n');
-	}
-}
-

 void leds_setup(void) __banked
 {
@@ -0,0 +1,155 @@
+#include <stdint.h>
+#include "rtl837x_common.h"
+#include "rtl837x_sfr.h"
+#include "rtl837x_regs.h"
+#include "rtl837x_leds.h"
+#include "machine.h"
+
+#pragma codeseg BANK3
+#pragma constseg BANK3
+
+extern __code const struct machine machine;
+extern __xdata uint8_t sfr_data[4];
+
+void leds_dump(void) __banked
+{
+	print_string("RTL837X_PIN_MUX_0: "); print_reg(RTL837X_PIN_MUX_0); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_IO_EN: "); print_reg(RTL837X_REG_LED_GLB_IO_EN); write_char('\n');
+	print_string("RTL837X_REG_LED1_0_SET0: "); print_reg(RTL837X_REG_LED1_0_SET0); write_char('\n');
+	print_string("RTL837X_REG_LED3_2_SET0: "); print_reg(RTL837X_REG_LED3_2_SET0); write_char('\n');
+	print_string("RTL837X_REG_LED1_0_SET1: "); print_reg(RTL837X_REG_LED1_0_SET1); write_char('\n');
+	print_string("RTL837X_REG_LED3_2_SET1: "); print_reg(RTL837X_REG_LED3_2_SET1); write_char('\n');
+	print_string("RTL837X_REG_LED1_0_SET2: "); print_reg(RTL837X_REG_LED1_0_SET2); write_char('\n');
+	print_string("RTL837X_REG_LED3_2_SET2: "); print_reg(RTL837X_REG_LED3_2_SET2); write_char('\n');
+	print_string("RTL837X_REG_LED1_0_SET3: "); print_reg(RTL837X_REG_LED1_0_SET3); write_char('\n');
+	print_string("RTL837X_REG_LED3_2_SET3: "); print_reg(RTL837X_REG_LED3_2_SET3); write_char('\n');
+	print_string("RTL837X_REG_LED3_0_SET1: "); print_reg(RTL837X_REG_LED3_0_SET1); write_char('\n');
+	print_string("RTL837X_REG_LED3_0_SET3: "); print_reg(RTL837X_REG_LED3_0_SET3); write_char('\n');
+	print_string("RTL837X_LED_PORT_SET_SEL: "); print_reg(RTL837X_LED_PORT_SET_SEL); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_1: "); print_reg(RTL837X_REG_LED_GLB_MUX_1); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_2: "); print_reg(RTL837X_REG_LED_GLB_MUX_2); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_3: "); print_reg(RTL837X_REG_LED_GLB_MUX_3); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_4: "); print_reg(RTL837X_REG_LED_GLB_MUX_4); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_5: "); print_reg(RTL837X_REG_LED_GLB_MUX_5); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_MUX_6: "); print_reg(RTL837X_REG_LED_GLB_MUX_6); write_char('\n');
+	print_string("RTL837X_REG_LED_GLB_ACTIVE: "); print_reg(RTL837X_REG_LED_GLB_ACTIVE); write_char('\n');
+	print_string("RTL837X_REG_LED_MODE: "); print_reg(RTL837X_REG_LED_MODE); write_char('\n');
+	print_string("LED pad Configuration:\n");
+	for (uint8_t i = 0; i < 28; i++) {
+		print_byte(i);
+		write_char(' ');
+	}
+	write_char('\n');
+	for (uint8_t i = 0; i < 28; i++) {
+		switch (i % 5) {
+		case 0:  // 0
+			reg_read_m(RTL837X_REG_LED_GLB_MUX_1 + (i / 5) * 4);
+			print_byte(sfr_data[3] & 0x3f);
+			break;
+		case 1:  // 6
+			print_byte(((sfr_data[3] >> 6) | (sfr_data[2] << 2)) & 0x3f);
+			break;
+		case 2:  // 12
+			print_byte(((sfr_data[1] << 4) | (sfr_data[2] >> 4)) & 0x3f);
+			break;
+		case 3:  // 18
+			print_byte((sfr_data[1] >> 2) & 0x3f);
+			break;
+		case 4:  // 24
+			print_byte(sfr_data[0] & 0x3f);
+			break;
+		}
+		write_char(' ');
+	}
+	write_char('\n');
+	print_string("LED-set Configuration:\n");
+	print_string("LED-ID\t\t0\t\t1\t\t2\t\t3\n");
+	for (__xdata uint8_t set = 0; set < 4; set++) {
+		print_string("SET "); write_char('0' + set); write_char(':');
+		for (__xdata uint8_t ledid = 0; ledid < 4; ledid++) {
+			print_string("\t   ");
+			uint8_t b;
+			if (set < 2) {
+				reg_read_m(RTL837X_REG_LED3_0_SET1);
+				b = sfr_data[3-((set << 1) + (ledid >> 1))];
+				print_byte(ledid & 1 ? b >> 4 : b & 0xf);
+			} else {
+				reg_read_m(RTL837X_REG_LED3_0_SET3);
+				b = sfr_data[3-(((set-2) << 1) + (ledid >> 1))];
+				print_byte(ledid & 1 ? b >> 4 : b & 0xf);
+			}
+			reg_read_m(RTL837X_REG_LED1_0_SET0 - set * 8 - ((ledid >> 1) * 4));
+			if (! (ledid & 1)) { // LEDID 0, 2
+				print_byte(sfr_data[2]); print_byte(sfr_data[3]);
+			} else {
+				print_byte(sfr_data[0]); print_byte(sfr_data[1]);
+			}
+		}
+		write_char('\n');
+	}
+	for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
+		reg_read_m(RTL837X_LED_PORT_SET_SEL);
+		__xdata uint8_t set = sfr_data[3 - (i >> 2)];
+		set = (set >> ((i & 3) << 1));
+		print_string("Port "); write_char('0' + i); print_string(": SET ");
+		write_char('0' + set);
+		print_string(": ");
+		for (__xdata uint8_t ledid = 0; ledid < 4; ledid++) {
+			write_char('(');
+			reg_read_m(RTL837X_REG_LED1_0_SET0 - set * 8 - ((ledid >> 1) * 4));
+			if (ledid & 1) {  // LEDID 1, 3
+				sfr_data[2] = sfr_data[0];
+				sfr_data[3] = sfr_data[1];
+			}
+			if (sfr_data[3] & 0x01)
+				print_string(" 2G5");
+			if (sfr_data[3] & 0x02)
+				print_string(" TWO_1G");
+			if (sfr_data[3] & 0x04)
+				print_string(" 1G");
+			if (sfr_data[3] & 0x08)
+				print_string(" 500M");
+			if (sfr_data[3] & 0x10)
+				print_string(" 100M");
+			if (sfr_data[3] & 0x20)
+				print_string(" 10M");
+			if (sfr_data[3] & 0x40)
+				print_string(" LINK");
+			if (sfr_data[3] & 0x80)
+				print_string(" LINK_FLASH");
+			if (sfr_data[2] & 0x01)
+				print_string(" ACT");
+			if (sfr_data[2] & 0x02)
+				print_string(" RX");
+			if (sfr_data[2] & 0x04)
+				print_string(" TX");
+			if (sfr_data[2] & 0x08)
+				print_string(" COL");
+			if (sfr_data[2] & 0x10)
+				print_string(" DUPLEX");
+			if (sfr_data[2] & 0x20)
+				print_string(" TRAINING");
+			if (sfr_data[2] & 0x40)
+				print_string(" MASTER");
+			__xdata uint8_t b;
+			if (set < 2) {
+				reg_read_m(RTL837X_REG_LED3_0_SET1);
+				b = sfr_data[3-((set << 1) + (ledid >> 1))];
+			} else {
+				reg_read_m(RTL837X_REG_LED3_0_SET3);
+				b = sfr_data[3-(((set-2) << 1) + (ledid >> 1))];
+			}
+			b = ledid & 1 ? b >> 4 : b & 0xf;
+			if (b & 0x1)
+				print_string(" 10G");
+			if (b & 0x2)
+				print_string(" TWO_5G");
+			if (b & 0x4)
+				print_string(" 5G");
+			if (b & 0x8)
+				print_string(" TWO_2G5");
+			print_string("), ");
+		}
+		write_char('\n');
+	}
+}
@@ -0,0 +1,161 @@
+#pragma codeseg BANK3
+#pragma constseg BANK3
+
+#include "rtl837x_common.h"
+#include "rtl837x_lldp.h"
+#include "rtl837x_sfr.h"
+#include "rtl837x_common.h"
+#include "dhcp.h"
+#include "uip.h"
+#include "uip/uip.h"
+#include "machine.h"
+
+extern __xdata bool lldp_enabled;
+extern __code const struct machine machine;
+
+__xdata uint16_t lldp_ticks;
+__xdata uint16_t lldp_logical_port_status = 0xffff;
+
+void lldp_init(void) __banked
+{
+    lldp_ticks = 0;
+}
+
+void lldp_tick(void) __banked
+{
+    lldp_ticks++;
+
+    if (lldp_ticks < LLDP_TX_INTERVAL_TICKS)
+        return;
+
+    lldp_ticks = 0;
+
+    if(lldp_enabled == 1)
+        lldp_send();
+}
+
+//Outgoing LLDP packet.
+
+struct lldp_pkt {
+    struct uip_eth_addr dst;
+    struct uip_eth_addr src;
+    struct rtl_tag rtl_tag;
+    uint16_t ether_type;
+
+    uint8_t payload[64];
+};
+
+#define LLDP_O ((__xdata struct lldp_pkt *)&uip_buf[RTL_FRAME_DESC_SIZE])
+
+// The type is 7 bits and the length is 9 bits
+// we can represent this as the 7 most significant
+// bits of the type bit and leave the least significant
+// bit as 0 always as we're not going to need 2^9 for
+// the length at any point
+#define LLDP_TYPE(value) (value << 1)
+
+void lldp_send(void) __banked __reentrant
+{
+    __xdata uint8_t *p;
+    uint8_t port_position;
+
+    lldp_set_addresses();
+    lldp_set_rtl_wrapper();
+
+    p = LLDP_O->payload;
+
+    //Chassis ID
+    *p++ = LLDP_TYPE(LLDP_CHASSIS_ID_TLV_TYPE);
+    *p++ = LLDP_CHASSIS_ID_TLV_LENGTH;
+    *p++ = LLDP_CHASSIS_ID_TLV_SUBTYPE;
+
+    memcpy(p, uip_ethaddr.addr, MAC_ADDR_LEN);
+    p += MAC_ADDR_LEN;
+
+    //Port ID
+    *p++ = LLDP_TYPE(LLDP_PORT_ID_TLV_TYPE);
+    *p++ = LLDP_PORT_ID_TLV_LENGTH;
+    *p++ = LLDP_PORT_ID_TLV_SUBTYPE;
+    port_position = (p-LLDP_O->payload);
+	*p++ = '0';       // filled in per port below
+
+    //TTL
+    *p++ = LLDP_TYPE(LLDP_TTL_TLV_TYPE);
+    *p++ = LLDP_TTL_TLV_LENGTH;
+    *p++ = 0x00; //padding
+    *p++ = LLDP_TTL_TTL_SECONDS;
+
+    p += lldp_sysname(p);
+    p += lldp_sysdesc(p);
+
+    // End of LLDPDU TLV
+    *p++ = 0x00; //padding
+    *p++ = 0x00; //padding
+
+    while (p < (LLDP_O->payload + LLDP_MIN_ETHERNET_PAYLOAD_LENGTH))
+        *p++ = 0x00;
+
+    /*
+     * uip_len is the Ethernet frame length excluding FCS.
+     *
+     * The frame consists of:
+     *
+     *     dst mac
+     *     src mac
+     *     rtl_tag  sizeof(struct rtl_tag)
+     *     EtherType (2 bytes)
+     *     payload (how far we've moved p pointer)
+     */
+    uip_len = MAC_ADDR_LEN + MAC_ADDR_LEN + sizeof(struct rtl_tag) + LLDP_ETHERTYPE_LENGTH + (p - LLDP_O->payload);
+
+    for (uint8_t port = machine.min_port; port <= machine.max_port; port++) {
+
+        if ((1 << port) & lldp_logical_port_status) {
+            LLDP_O->payload[port_position] = '0' + machine.log_to_phys_port[port];
+            LLDP_O->rtl_tag.pmask = HTONS((uint16_t)1 << port);
+
+            tcpip_output();
+        }
+    }
+}
+
+void lldp_set_addresses(void) __banked {
+    // LLDP destination multicast addr: 01:80:c2:00:00:0e
+    memcpyc(LLDP_O->dst.addr, "\x01\x80\xc2\x00\x00\x0e", MAC_ADDR_LEN);
+    memcpy(LLDP_O->src.addr, uip_ethaddr.addr, MAC_ADDR_LEN);
+}
+
+void lldp_set_rtl_wrapper(void) __banked {
+    /*
+     * This is the RTL CPU tag, not the Ethernet EtherType.
+     *     port 0 -> 0x0001
+     *     port 1 -> 0x0002
+     *     port 2 -> 0x0004
+     */
+    LLDP_O->rtl_tag.tag = HTONS(RTL_FRAME_TAG_ID);
+    LLDP_O->rtl_tag.version = RTL_FRAME_TAG_VERSION;
+    LLDP_O->rtl_tag.reason = 0x00;
+    LLDP_O->rtl_tag.flags = HTONS(RTL_TAG_LEARN_DIS);
+
+    LLDP_O->ether_type = HTONS(LLDP_ETHERTYPE);
+}
+
+uint8_t lldp_sysname(__xdata uint8_t *p) __banked
+{
+    uint8_t hostname_length = strlen_x(hostname);
+
+    *p++ = LLDP_TYPE(LLDP_SYSNAME_TLV_TYPE);
+    *p++ = hostname_length;
+    memcpy(p, hostname, hostname_length);
+    return hostname_length + 2;
+}
+
+uint8_t lldp_sysdesc(__xdata uint8_t *p) __banked
+{
+    uint16_t machine_name_length = strlen(machine.machine_name);
+
+    *p++ = LLDP_TYPE(LLDP_SYSDESC_TLV_TYPE);
+    *p++ = machine_name_length;
+    memcpyc(p, machine.machine_name, machine_name_length);
+    return machine_name_length + 2; 
+}
@@ -0,0 +1,36 @@
+#ifndef _LLDP_H_
+#define _LLDP_H_
+
+#include <stdint.h>
+
+#define LLDP_MIN_ETHERNET_PAYLOAD_LENGTH 46
+#define LLDP_ETHERTYPE       0x88cc
+#define LLDP_ETHERTYPE_LENGTH 2
+#define LLDP_MAX_FRAME       256
+#define MAC_ADDR_LEN    6
+#define LLDP_TX_INTERVAL_TICKS 6000
+
+#define LLDP_PORT_ID_TLV_TYPE 2
+#define LLDP_PORT_ID_TLV_LENGTH 0x02
+#define LLDP_PORT_ID_TLV_SUBTYPE 0x07
+
+#define LLDP_TTL_TLV_TYPE 3
+#define LLDP_TTL_TLV_LENGTH 2
+#define LLDP_TTL_TTL_SECONDS 120
+
+#define LLDP_CHASSIS_ID_TLV_TYPE 1
+#define LLDP_CHASSIS_ID_TLV_LENGTH 7
+#define LLDP_CHASSIS_ID_TLV_SUBTYPE 4
+
+#define LLDP_SYSNAME_TLV_TYPE 5
+#define LLDP_SYSDESC_TLV_TYPE 6
+
+void lldp_init(void) __banked;
+void lldp_tick(void) __banked;
+void lldp_send(void) __banked;
+void lldp_set_addresses(void) __banked;
+void lldp_set_rtl_wrapper(void) __banked;
+uint8_t lldp_sysname(__xdata uint8_t *p) __banked;
+uint8_t lldp_sysdesc(__xdata uint8_t *p) __banked;
+
+#endif
@@ -16,6 +16,7 @@
 #include "rtl837x_leds.h"
 #include "rtl837x_bandwidth.h"
 #include "rtl837x_init.h"
+#include "rtl837x_lldp.h"
 #include "dhcp.h"
 #include "cmd_parser.h"
 #include "cmd_editor.h"
@@ -127,6 +128,7 @@ __xdata uint8_t tx_seq;

 __xdata bool stp_enabled;
 __xdata uint8_t igmpEnabled;
+__xdata bool lldp_enabled;
 __xdata char hostname[24];	/* device hostname, default set at boot, see rtl837x_common.h */

 __code const uint16_t bit_mask[16] = {
@@ -1286,6 +1288,8 @@ static void handle_tick(void)
 		}
 	}
 	health_phase(HEALTH_PH_STP);
+	lldp_tick();
+	health_phase(HEALTH_LLDP);
 }


@@ -1752,8 +1756,6 @@ void main(void)
 	leds_setup();
 	machine_custom_init();

-	leds_dump();
-
 	set_sys_led_state(SYS_LED_SLOW);

 	if (machine_detected.isRTL8373)
@@ -1794,6 +1796,7 @@ void main(void)
 	uip_init();
 	uip_arp_init();
 	httpd_init();
+	lldp_init();

 	management_vlan = 1; // Default management VLAN is 1

@@ -0,0 +1,410 @@
+; Assembler file to intercept register writes/reads and PHY writes/reads
+; assemble with as31
+; Compile with
+; as31 -Fbyte -Orwintercept_zoerax_hg0402xg.hex rwintercept_zoerax_hg0402xg.asm
+; ./injector zoerax_hg0402xg.bin RTLPlayground/rwintercept_zoerax_hg0402xg.hex zoerax_hg0402xg_patched.bin
+; Start at 0x3b00, where there is always some space in BANK 0
+	.equ	valptr, 0xc7
+
+
+	.equ	SFR_DATA_0, 0xa7
+	.equ	SFR_DATA_8, 0xa6
+	.equ	SFR_DATA_16, 0xa5
+	.equ	SFR_DATA_24, 0xa4
+
+; Intercept Register Write
+	.org 0x4d62
+	lcall	reg_write
+	nop
+
+; Intercept Register Read
+	.org 0x4dad
+	lcall	reg_read_head
+	.org 0x4e6f
+	lcall	reg_read_tail
+
+; Intercept PHY write
+	.org 0x522c
+	lcall	phy_write
+
+; Intercept PHY read
+	.org 0x526f
+	lcall	phy_read_head
+	.org 0x5295
+	ljmp	phy_read_tail
+
+; Intercept SDS write
+	.org 0x503c
+	lcall	sds_write
+	nop
+
+; Intercept SDS read
+	.org 0x5061
+	lcall	sds_read_head
+	nop
+	.org 0x507b
+	ljmp	sds_read_tail
+
+;
+; BEGIN actual code at unused end of BANK0
+;
+	.org 0x3b00
+
+;
+; print the address of a register write. The address is in R6/R7. A and r4 can be scratched
+;
+reg_write:	
+	mov	a, #'R'
+	acall	putc
+
+	mov	a, r6
+	acall	wbyte
+
+	mov	a, r7
+	acall	wbyte
+
+	mov	a, #'-'
+	acall	putc
+
+	mov	dptr, #valptr
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 1
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 2
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #valptr + 3
+	movx	a, @dptr
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	a, r7
+	mov	r5, a
+	mov	a, r6
+	mov	r4, a
+	ret
+
+;
+; print the address of a register read The address is in R2/R3. Registers 4-7 are scratch
+;
+reg_read_head:
+	mov	a, #'r'
+	acall	putc
+
+	mov	a, r2
+	acall	wbyte
+
+	mov	a, r3
+	acall	wbyte
+
+	mov	a, #':'
+	acall	putc
+	clr	a
+	mov	r7, a
+	mov	r6, a
+	mov	r5, a
+	mov	r4, a
+	ret
+
+reg_read_tail:
+	mov	dptr, #0xc5
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #0xc5 + 1
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #0xc5 + 2
+	movx	a, @dptr
+	acall	wbyte
+	mov	dptr, #0xc5 + 3
+	movx	a, @dptr
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	dptr,#0xc5
+	ret
+
+
+;
+; print phy write options
+;
+phy_write:
+	mov	a, #'P'
+	acall	putc
+
+	mov	a, r4
+	acall	wbyte
+
+; phymask
+	mov	a, r6
+	acall	wbyte
+	mov	a, r7
+	acall	wbyte
+
+	mov	a, #'.'
+	acall	putc
+
+; dev_id?
+	mov	a, r5
+	acall	wbyte
+
+; x_phywrite_opt
+	mov	dptr, #0xf1
+	movx	a, @dptr
+	acall	wbyte
+
+; The register going to SFR_C2 and SFR_C3
+	mov	a, r2
+	acall	wbyte
+	mov	a, r3
+	acall	wbyte
+
+	mov	a, #':'
+	acall	putc
+
+	mov	dptr, #0xf2
+	movx	a, @dptr
+	acall	wbyte
+
+	
+	mov	dptr, #0xf3
+	movx	a, @dptr
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	dptr, #0xeb
+	mov	r4, #0
+	ret
+
+;
+; print phy read options
+;
+phy_read_head:
+	mov	r1, 4	; actually r4
+
+	mov	a, #'p'
+	acall	putc
+
+	mov	a, r7
+	acall	wbyte
+
+	mov	a, r5
+	acall	wbyte
+
+	mov	a, #'.'
+	acall	putc
+
+	mov	a, r2
+	acall	wbyte
+	mov	a, r3
+	acall	wbyte
+
+	mov	a, #':'
+	acall	putc
+
+	mov	r1, 7
+	mov	a, r2
+	ret
+
+phy_read_tail:
+	mov	r6, 4
+	mov	a, r6
+	acall	wbyte
+	mov	a, r7
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+	mov	r4, 6
+	ret
+
+	
+;
+; print SDS write options
+;
+sds_write:
+	mov	a, r4
+	mov	r2, a	; R2 is scratch
+
+	mov	a, #'Q'
+	acall	putc
+
+
+	mov	a, r7
+	acall	wbyte
+	mov	a, r5
+	acall	wbyte
+	mov	a, r3
+	acall	wbyte
+	
+	mov	a, #':'
+	acall	putc
+
+	mov	dptr, #0xe1
+	movx	a, @dptr
+	acall	wbyte
+
+	
+	mov	dptr, #0xe2
+	movx	a, @dptr
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	a, r7
+	mov	r1, a
+	mov	a, r5
+	mov	r7, a
+	mov	a, r2
+	mov	r4, a
+	ret
+
+;
+; print SDS read options
+;
+sds_read_head:
+	mov	a, r4
+	mov	r1, a	; R1 is scratch
+
+	mov	a, #'q'
+	acall	putc
+
+	mov	a, r7	; sds_index bit
+	acall	wbyte
+	mov	a, r5	; SFR_94 (2 x r5 | r7)
+	acall	wbyte
+	mov	a, r3	; SFR_93
+	acall	wbyte
+
+	mov	a, #':'
+	acall	putc
+
+	mov	a, r1
+	mov	r4, a	; R1 is scratch
+
+	mov	a, r7
+	mov	r1, a
+	mov	a, r5 
+	mov	r7, a 
+
+	ret
+
+;
+; print SDS read result
+;
+sds_read_tail:
+	mov	a, r4
+	mov	r6, a	; R6 is returned and preserved
+
+	mov	a, r7	; = r7 = SFR_DATA_8
+	acall	wbyte
+	mov	r7, SFR_DATA_0
+	mov	a, r7	; SFR_DATA_0
+	acall	wbyte
+
+	mov	a, #' '
+	acall	putc
+
+	mov	a, r6	; R6 is returned and preserved
+	mov	r4, a	
+	ret
+
+;
+;	Write a byte as hex to serial
+;
+	nop
+	nop
+wbyte:
+	mov	r4, a
+	swap	a
+	anl	a, #0x0f
+	mov	dptr,#hex
+	movc	a, @a+dptr
+
+	jb	ET0, wbyte1
+	ret
+wbyte1:
+	jbc	TI, wbyte2
+	sjmp	wbyte1
+wbyte2:
+	mov	SBUF,a
+	
+	mov	a, r4
+	anl	a, #0x0f
+	mov	dptr,#hex
+	movc	a, @a+dptr
+
+wbyte3:
+	jbc	TI, wbyte4
+	sjmp	wbyte3
+wbyte4:
+	mov	SBUF,a
+
+	ret
+
+;
+;	Intercept isr_ext0
+;
+isr_ext0:
+	mov	a, #'i'
+	acall	putc
+	mov	r0,#0x51
+	inc	@r0
+	ret
+
+;
+;	Intercept isr_ext1
+;
+isr_ext1:
+	mov	a, #'I'
+	acall	putc
+	mov	r0,#0x25
+	mov	a, @r0
+	ret
+;
+;	Intercept isr_ext2
+;
+isr_ext2:
+	mov	a, #'J'
+	acall	putc
+	mov	r0, #0x1e
+	mov	a, #0xa
+	ret
+
+;
+;	Intercept isr_ext3
+;
+isr_ext3:
+	mov	a, #'j'
+	acall	putc
+	mov	r0,#0x1e
+	mov	a,#0x14
+	ret
+
+;
+;	Write a character to serial
+;
+	nop
+	nop
+putc:
+	jb	ET0, putc1
+	ret
+putc1:
+	jbc	TI,putc2
+	sjmp	putc1
+putc2:
+	mov	SBUF,a
+	ret
+
+hex:
+	.byte "0123456789abcdef"
+	.end
@@ -84,6 +84,9 @@ char     port_names[9][PORT_NAME_SIZE];
 struct flash_region_t flash_region;
 struct syslog_state syslog_state;
 bool     stp_enabled;
+bool lldp_enabled;
+uint16_t lldp_logical_port_status;
+

 uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask;
 struct uip_eth_addr uip_ethaddr = { .addr = { 0x02, 0x11, 0x22, 0x33, 0x44, 0x55 } };
@@ -152,6 +152,7 @@ void send_lag(void) { }
 void send_stp(void) { }
 void send_stp_counters(void) { }
 void send_vlanlist(void) { }
+void send_lldp(void) {}

 extern uint8_t authenticated;

@@ -447,13 +447,41 @@ void send_mtu(int s)
 		json_object_object_add(v, "mtu", json_object_new_string(mtu));
 		json_object_array_add(mtus, v);
 	}
-        write(s, header, strlen(header));
+	write(s, header, strlen(header));

 	jstring = json_object_to_json_string_ext(mtus, JSON_C_TO_STRING_PLAIN);
        write(s, jstring, strlen(jstring));
 	json_object_put(mtus);
 }

+void send_lldp(int s)
+{
+	struct json_object *c, *portStatuses, *p;
+	const char *jstring;
+	char *header = "HTTP/1.1 200 OK\r\n"
+                         "Content-Type: application/json; charset=UTF-8\r\n\r\n";
+
+	c = json_object_new_object();
+	json_object_object_add(c, "on", json_object_new_int(1));
+	portStatuses = json_object_new_array_ext(PORTS);
+
+	for (int i = 1; i <= PORTS; i++) {
+		p = json_object_new_object();
+		json_object_object_add(p, "portNum", json_object_new_int(i));
+		json_object_object_add(p, "logPort", json_object_new_int(i-1));
+		json_object_object_add(p, "name", json_object_new_string(""));
+		json_object_object_add(p, "permitted", json_object_new_int(1));
+		json_object_array_add(portStatuses, p);
+	}
+
+	json_object_object_add(c, "portStatus", portStatuses);
+
+	write(s, header, strlen(header));
+
+	jstring = json_object_to_json_string_ext(c, JSON_C_TO_STRING_PLAIN);
+	write(s, jstring, strlen(jstring));
+	json_object_put(c);
+}

 void send_cmd_log(int s)
 {
@@ -468,7 +496,6 @@ void send_cmd_log(int s)
 	}
 }

-
 void send_config(int s)
 {
        char *header = "HTTP/1.1 200 OK\r\n"
@@ -701,6 +728,13 @@ void launch(struct Server *server)
 					else
 						send_vlan(new_socket, vlan);
 					goto done;
+				} else if (!strncmp(&buffer[4], "/lldp.json", 10)) {
+					printf("LLDP request");
+					if (!authenticated)
+						send_unauthorized(new_socket);
+					else
+						send_lldp(new_socket);
+					goto done;
 				} else if (!strncmp(&buffer[4], "/cmd_log", 8)) {
 					printf("Request cmd_log\n");
 					if (!authenticated)
@@ -3,7 +3,7 @@

 #include <netinet/in.h>

-#define BUFFER_SIZE 131072
+#define BUFFER_SIZE 262144

 struct Server {
    int domain;
Author	SHA1	Message	Date
logicog	c263a8ab64	Add assmebler injection script	2026-10-15 06:53:23 +02:00
logicog	c02f660c08	doc: Add HOWTO for using firmware tracing to figure LED configuration This adds a howto for figuring out LED configuration via tracing of functions in the originam firmware image. The method also provides information on PHY and SDS configuration, including PHY patches.	2026-10-11 22:31:33 +02:00
René van Dorst	4e00f5a592	Merge pull request #398 from mintsoft/lldpd LLDP implementation	2026-10-10 09:17:00 +00:00
Rob Emery	eff3f42ae1	Rewriting sim implementation to be data driven The value for enabled should be an int, not a string	2026-10-10 09:51:50 +01:00
Rob Emery	dda873a633	Moving lldp cmd parsing to be above the is_sfp check to take precedence Needed to increase buffer size for this to send app.js The logical port status is what is returned in the array, for non-sequential systems we need to map through physToLog rather than just subtracting 1 physToLog is 1 based! not 0; also fixing up typecasts Reimplementing using an array of objects to represent ports. The previous approach of a bitmask of logical ports, was just too simple on devices such as the SWGT024_V2_0_MANAGED which has gaps in the port assignments.	2026-10-10 09:51:33 +01:00
Rob Emery	9b2bd7f1b8	The tick rate has been changed now so we'll have to approximate timing with ticks Fixing up the log_to_phys_port assignment 2000 is about every 10 seconds, so scaling up to once every 30ish Removing the attempt to block lldp frames, This does not work however the hard work has been done for us in the #514 so we can borrow that work later on	2026-10-10 09:50:38 +01:00
Rob Emery	2dfe531fe0	Fixing missing parts to make the tests pass boot_to_html outputs 1 and 0 not true and false, making the sim match the real implementation. lldp.json has a hanging , in the array; so overwriting it	2026-10-10 09:50:27 +01:00
Rob Emery	72c2625121	Icon from https://github.com/logicog/RTLPlayground/pull/429#issuecomment-5687458129	2026-10-10 09:50:27 +01:00
Rob Emery	58fd1a3ccc	Adding lldp.json to the simulator Moving the global on/off onto the LLDP page Building a table of LLDP status from the S ports. Later on, if we wish to implement an lldp receiver we can display the remote details here Adding support to the cmd parser for the lldp commands	2026-10-10 09:50:01 +01:00
Rob Emery	4f1a2f04d8	Allowing commands like `port 1 lldp block` and `port 2 lldp permit` so we are able to enable/disable lldp transmission on a specific port.	2026-10-10 09:50:01 +01:00
Rob Emery	cedc795b82	Adding UI options to enable/disable LLDP	2026-10-10 09:50:01 +01:00
Rob Emery	ccf541a06b	Refactor and golfing from https://github.com/logicog/RTLPlayground/pull/398#issuecomment-5654087271 I've tweaked it a little to keep the port_position in as I think that is clearer than a random "12" in the loop later on	2026-10-10 09:50:01 +01:00
Rob Emery	d5124df89e	avoid SRAM	2026-10-10 09:50:01 +01:00
Rob Emery	3eacc9c8a5	LLPD_MAC_ADDR_LEN -> MAC_ADDR_LEN and memcopy instead of manually setting bytes	2026-10-10 09:50:01 +01:00
Rob Emery	735672ccf1	Moving to Bank3	2026-10-10 09:49:52 +01:00
Rob Emery	1ebee4d6e9	Implementing basic LLDP server, should send port_id message to each port once every 30 seconds. * Additionally fixes the on-ward passing of LLDP frames through the switch The ports on the case are marked 1-8 so this should reflect that rather than being 0-based We can send the hostname as well, this can be dynamically allocated Let's send the model as the system description as well	2026-10-10 09:49:24 +01:00
René van Dorst	e67c928eb7	Merge pull request #465 from andreas5232/add-device-ONT-S207CW-62TS-SE add support for ONT-S207CW-62TS-SE and identical Binardat-2G06-04210GSM	2026-10-08 06:45:31 +00:00
Andreas Erhard	46f8ea8712	re-added struct comments again	2026-10-08 00:32:02 +02:00
Andreas Erhard	b0eab52a2e	applied feedback from review	2026-10-07 01:18:08 +02:00
Andreas Erhard	8ce062c349	resized images	2026-10-07 01:13:20 +02:00
Andreas Erhard	f768220a73	updated docs and removed duplicate picturs	2026-10-05 23:51:02 +02:00
René van Dorst	eab2e26510	Merge pull request #553 from DrDoof/cleanup/leds-dump-debug leds: move the LED register dump to BANK3 and behind a command	2026-10-05 17:43:11 +00:00
DrDoof	b0ed56d423	leds: move the LED register dump to BANK3 and behind a command leds_dump() printed the pin mux, the LED enables and every LED set on each boot, from BANK2. It now lives in its own file in BANK3, where there is room, and runs only on the new "leds" command, next to gpio and sds, so it stays at hand for bringing up a new board without costing BANK2 or boot output.	2026-10-05 08:22:19 +02:00
Andreas Erhard	fa632cdc6e	updated docs and corrected led mapping	2026-10-05 00:43:25 +02:00
Andreas Erhard	177fb76e1b	Merge branch 'main' into add-device-ONT-S207CW-62TS-SE	2026-10-04 23:45:20 +02:00
Andreas Erhard	24069439b0	reversed rj45 port order and optimized led config	2026-10-04 01:11:10 +02:00
Andreas Erhard	4117f549cc	Merge branch 'main' into add-device-ONT-S207CW-62TS-SE	2026-10-03 19:27:49 +02:00
Andreas Erhard	9733ff61a0	another almost working state. port order is wrong and leds are not correct, but ports are all working	2026-09-21 01:16:16 +02:00
Andreas Erhard	36459fdd76	Merge branch 'main' into add-device-ONT-S207CW-62TS-SE	2026-09-20 22:18:41 +02:00
Andreas Erhard	a4e3b4368b	extracted ONT-S207CW-62TS-SE into separate device	2026-09-18 22:16:06 +02:00
Andreas Erhard	c514eb8bf3	Merge branch 'logicog:main' into add-device-ONT-S207CW-62TS-SE	2026-09-17 23:33:30 +02:00
Andreas Erhard	575274786a	incorporated feedback from PR	2026-09-17 12:08:37 +02:00
Andreas Erhard	eb83b8be09	added support for ONT-S207CW-62TS-SE and identical Binardat-2G06-04210GSM	2026-09-17 00:18:46 +02:00