 logicog
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8b1b4aff68
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Fix parsing of mirror command, fix parsing of serial buffer beyond wrap arond, add bulk reading of flash and start of config file parser
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2025-07-28 23:04:08 +02:00 |
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logicog
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7481c88ace
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Improve debugging
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2025-07-28 23:01:50 +02:00 |
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logicog
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417dfe2345
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Fix serial buffer length to fit signed char
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2025-07-28 23:00:15 +02:00 |
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logicog
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2eaea39e18
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Fix SFR address of trampoline return
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2025-07-28 22:59:23 +02:00 |
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logicog
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2e5f3169b3
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Fix typo
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2025-07-28 22:58:17 +02:00 |
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logicog
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a5d156a645
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Fix dropping of RTL VLAN tag for 802.1Q Tag, add L2 configuration
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2025-07-25 22:51:18 +02:00 |
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logicog
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fcd1f85eb6
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Add trunking support and initial L2 setup
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2025-07-25 22:50:27 +02:00 |
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logicog
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891ee08243
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Add support for non-linear mapping of physical ports to logical ports. Add support for trunking
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2025-07-25 22:49:51 +02:00 |
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logicog
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2998b4a791
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Fix links in SFP doc
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2025-07-23 09:17:07 +02:00 |
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logicog
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55e851ef5e
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Adding SFP documentation
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2025-07-23 09:14:04 +02:00 |
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logicog
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0b30019769
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Use names for I2C-controller registers
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2025-07-23 08:34:26 +02:00 |
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logicog
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96a108e891
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Use common SDS configuration code also for RTL8224
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2025-07-23 08:01:33 +02:00 |
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logicog
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e7bffb4a34
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Update on features: RTL8224 supported and others
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2025-07-22 20:57:20 +02:00 |
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logicog
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bcc58d2965
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Make RTL8224 work
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2025-07-22 19:05:27 +02:00 |
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logicog
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8fee855da2
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Separate code for rtl8272 from rtl8373 for readability and stability against accidental changes
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2025-07-22 09:42:56 +02:00 |
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logicog
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995deb313c
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Cleanup of unused code
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2025-07-22 09:41:44 +02:00 |
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logicog
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066edd672e
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Add off-state for SDS
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2025-07-22 09:34:40 +02:00 |
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logicog
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6be1124ecf
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Fixed shift arithmetic bug reported by airjinkela
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2025-07-21 21:59:20 +02:00 |
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logicog
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fa4a80c291
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Cleanup of printouts
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2025-07-21 11:11:52 +02:00 |
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logicog
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ccd8bf1633
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Cleanup
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2025-07-17 23:29:20 +02:00 |
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logicog
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b6d92b10fa
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Latest status
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2025-07-17 15:17:33 +02:00 |
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logicog
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b0a41a5af6
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Add support for RTL8372-devices with 2 SFP+ ports
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2025-07-17 13:25:07 +02:00 |
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logicog
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ec69299a7b
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Clarification that flashing can always be done via patch-clamp
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2025-07-14 08:06:56 +02:00 |
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logicog
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a6e933fde6
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L2 table access feature added
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2025-07-14 08:01:59 +02:00 |
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logicog
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9b5cfb0e1b
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Mirroring and VLAN explained
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2025-07-14 08:00:48 +02:00 |
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logicog
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84b84f5c32
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Cleanup of L2 and mirroring features
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2025-07-14 07:59:31 +02:00 |
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logicog
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20b5c7b833
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Latest update on features
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2025-07-14 07:58:55 +02:00 |
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logicog
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38cc74d1fa
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Add documentation for mirroring
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2025-07-13 23:34:03 +02:00 |
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logicog
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ba1b03dd63
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More documentation on the L2 table
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2025-07-13 23:15:51 +02:00 |
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logicog
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e3bb76ec1b
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Initial description of L2 table
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2025-07-13 20:48:37 +02:00 |
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logicog
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1ae617c38b
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Initial description of L2 table
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2025-07-13 20:48:05 +02:00 |
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logicog
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d66931acdf
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Adding initial http daemon implementation
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2025-07-13 12:03:40 +02:00 |
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logicog
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e2716da6c8
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Typo fixed
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2025-07-13 11:53:23 +02:00 |
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logicog
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4edc826c39
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Accidentally checked in
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2025-07-13 11:52:57 +02:00 |
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logicog
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8d4b102e97
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More porting to RTL837x architecture of psock
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2025-07-12 16:11:51 +02:00 |
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logicog
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b192a87cab
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Cleaning up printouts for debugging of uIP
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2025-07-11 16:36:16 +02:00 |
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logicog
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a2af2f9151
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Empty application for testing
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2025-07-11 15:50:55 +02:00 |
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logicog
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37cee7692a
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Use lc-switch, becasue labels as values is not supported by sdcc
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2025-07-11 15:17:38 +02:00 |
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logicog
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8b761cfcc8
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Add UIP stack. Still lots of debug output on packets...
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2025-07-11 14:54:57 +02:00 |
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logicog
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e486c04186
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Add initial port of uip TCP/IP stack
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2025-07-11 14:16:08 +02:00 |
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logicog
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f0701295db
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Add description of checksum offload bits
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2025-07-11 14:14:00 +02:00 |
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logicog
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f25cc47c5f
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Adding uip lib support
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2025-07-06 09:55:12 +02:00 |
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logicog
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062c5576de
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Fixing banked call
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2025-07-05 23:46:09 +02:00 |
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logicog
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2d8c0efabd
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Add 802.1Q VLAN and PVID support. Support VLAN tag at CPU-port
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2025-07-04 09:17:10 +02:00 |
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logicog
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997d85ba02
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Add basic VLAN configuration
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2025-07-02 11:57:15 +02:00 |
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logicog
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6f90e1db53
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Add support for changing Ethernet speeds
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2025-06-29 20:06:53 +02:00 |
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logicog
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b59f51b3ca
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Cleanup of initialitation, make debug code conditional
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2025-06-29 11:10:29 +02:00 |
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logicog
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669ebdc616
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Access to sfp register reading in common
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2025-06-29 11:09:41 +02:00 |
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logicog
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fd48ae80c1
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Feature updates
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2025-06-29 11:09:01 +02:00 |
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logicog
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4f799f3677
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Adding port module
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2025-06-29 11:08:37 +02:00 |
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logicog
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5a87d81b8c
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Adding port statistics
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2025-06-29 11:07:54 +02:00 |
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logicog
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5faf31cdb8
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Moving PHY code to BANK1
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2025-06-25 15:30:50 +02:00 |
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logicog
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73a0a7d137
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Add banking support
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2025-06-25 13:20:06 +02:00 |
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logicog
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f543b58490
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More on checksum offloading
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2025-06-25 13:19:44 +02:00 |
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logicog
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797ae23865
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Banking support
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2025-06-24 06:06:49 +02:00 |
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logicog
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178e3d2550
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More doc on TX
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2025-06-23 19:43:33 +02:00 |
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logicog
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08d6c27605
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More documentation
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2025-06-23 19:41:26 +02:00 |
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logicog
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b8352f9430
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Implement ARP broadcast and make ping work
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2025-06-23 17:57:54 +02:00 |
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logicog
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2776df9ca8
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Make RX of packets work
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2025-06-21 16:18:19 +02:00 |
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logicog
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dd039494c2
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Add more RTL8224 config
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2025-06-21 05:58:55 +02:00 |
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logicog
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869db02865
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Emable RTL8224 PHY. Better implementation of sleep/delay timer
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2025-06-17 18:21:15 +02:00 |
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logicog
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e4d477938d
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Detect RTL8373 and name registers for GPIO. Enable RTL8224
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2025-06-16 06:55:47 +02:00 |
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logicog
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85cb2a52a5
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Cleanup
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2025-06-15 18:26:27 +02:00 |
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logicog
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b49f2aa16f
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Add initial support for RTL8373
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2025-06-15 18:24:23 +02:00 |
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logicog
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88067d3a3e
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Add command byte macros and NIC SFRs
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2025-06-15 18:19:43 +02:00 |
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logicog
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c435feee45
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Add REG_SET macro
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2025-06-15 18:18:36 +02:00 |
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logicog
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9a69fac07a
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Adding support for 2.5Gbit Ethernet modules
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2025-06-14 09:52:15 +02:00 |
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logicog
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37ca55392a
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Add support for 10G Fiber
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2025-06-14 09:12:24 +02:00 |
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logicog
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7eb7057787
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use uint types
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2025-06-14 09:12:07 +02:00 |
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logicog
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d78e28cbdb
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New features: SFP EEProm reading and SFP configuration
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2025-06-13 20:39:18 +02:00 |
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logicog
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0485c21da0
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Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
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2025-06-13 20:36:49 +02:00 |
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logicog
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c00c908579
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Keep up with features: SerDes configuration for port 5
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2025-06-12 20:36:59 +02:00 |
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logicog
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b41410ce6b
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Cleanup
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2025-06-12 20:33:35 +02:00 |
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logicog
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8c8b92ed65
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Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit
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2025-06-12 20:32:36 +02:00 |
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logicog
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86aebcbf08
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Add rtl837x_regs.h register header
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2025-06-12 20:31:53 +02:00 |
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logicog
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c7965d048e
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An injector of .hex files from as31 into .bin images
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2025-06-11 06:44:35 +02:00 |
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logicog
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8302b0d0d2
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Update on console
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2025-06-10 18:14:37 +02:00 |
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logicog
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fdec0ad80c
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Status update
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2025-06-10 18:11:29 +02:00 |
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logicog
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8243a454de
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Adding support for link status display
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2025-06-10 17:57:28 +02:00 |
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logicog
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2ae0b5caba
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Moving registers to dedicated header so they can be better documented
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2025-06-10 17:56:42 +02:00 |
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logicog
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c54227f057
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Fix SFR_DATA access, make internal switch work
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2025-06-09 11:22:52 +02:00 |
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logicog
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c5d7628ea0
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Adding support for the ASIC second counter register and sleeping
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2025-06-06 20:49:15 +02:00 |
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logicog
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a0a5328ecd
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Document default baud of 115200
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2025-06-05 20:16:24 +02:00 |
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logicog
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9f22c49af7
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Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud
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2025-06-05 20:15:42 +02:00 |
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logicog
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98403e25d3
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Add definitions for SFRs 0x93 and 0x94
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2025-06-05 20:14:08 +02:00 |
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logicog
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7c2e1509a5
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Cosmetics
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2025-06-05 20:13:07 +02:00 |
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logicog
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73a6f0f311
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Adding more flash functionality and image documentation
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2025-05-14 20:40:44 +02:00 |
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logicog
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7493089c39
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Adding DIO for flash access
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2025-05-11 20:29:31 +02:00 |
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logicog
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3a953bba47
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More commands, fixing strange sdcc behaviour for clock setting defines
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2025-05-11 18:28:08 +02:00 |
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logicog
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138ed7dd25
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More HW info
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2025-05-11 06:36:11 +02:00 |
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logicog
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8fedd9c997
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More on the image
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2025-05-10 17:13:04 +02:00 |
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logicog
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4f654d5a0b
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Nicer README
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2025-05-10 17:07:31 +02:00 |
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logicog
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6d3214d13d
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More initial documentation
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2025-05-10 17:01:33 +02:00 |
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logicog
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c4835b7a6c
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Initial commit
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2025-05-10 15:52:02 +02:00 |
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