mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit
This commit is contained in:
logicog
+170
-78
@@ -108,7 +108,6 @@ void print_string(__code char *p)
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write_char(*p++);
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}
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void print_short(unsigned short a)
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{
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print_string("0x");
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@@ -306,17 +305,94 @@ unsigned char read_flash(unsigned char bank, __code unsigned char *addr)
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void print_long_x(__xdata unsigned char v[])
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{
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write_char('0'); write_char('x');
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for (int i=0; i < 4; i++) {
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write_char(hex[v[i] >> 4]);
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write_char(hex[v[i] & 0xf]);
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}
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}
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/*
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* Read a SerDes register in the SoC
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* Input must be: sds_id = 0/1, page < 128, reg <= 0xff
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* The result is in SFR A6 and A7 (SFR_DATA_8, SFR_DATA_0)
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*/
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void sds_read(unsigned char sds_id, unsigned char page, unsigned char reg)
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{
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SFR_93 = reg; // 93
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SFR_94 = page << 1 | sds_id; // 94
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SFR_EXEC_GO = 5;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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/*
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* Write a SerDes register in the SoC
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* Input must be: sds_id = 0/1, page < 128, reg <= 0xff
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* The value written must be in SFR A6 and A7 (SFR_DATA_8, SFR_DATA_0)
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*/
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void sds_write(unsigned char sds_id, unsigned char page, unsigned char reg)
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{
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SFR_93 = reg;
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SFR_94 = page << 1 | sds_id;
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SFR_EXEC_GO = 5;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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void sds_write_v(unsigned char sds_id, unsigned char page, unsigned char reg, unsigned short v)
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{
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SFR_DATA_8 = v >> 8;
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SFR_DATA_0 = v;
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SFR_93 = reg;
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SFR_94 = page << 1 | sds_id;
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SFR_EXEC_GO = 5;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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void print_sfr_data(void)
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{
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write_char('0');
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write_char('x');
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write_char(hex[v[0] >> 4]);
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write_char(hex[v[0] & 0xf]);
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write_char(hex[v[1] >> 4]);
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write_char(hex[v[1] & 0xf]);
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write_char(hex[v[2] >> 4]);
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write_char(hex[v[2] & 0xf]);
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write_char(hex[v[3] >> 4]);
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write_char(hex[v[4] & 0xf]);
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write_char(hex[SFR_DATA_24 >> 4]);
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write_char(hex[SFR_DATA_24 & 0xf]);
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write_char(hex[SFR_DATA_16 >> 4]);
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write_char(hex[SFR_DATA_16 & 0xf]);
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write_char(hex[SFR_DATA_8 >> 4]);
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write_char(hex[SFR_DATA_8 & 0xf]);
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write_char(hex[SFR_DATA_0 >> 4]);
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write_char(hex[SFR_DATA_0 & 0xf]);
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}
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void print_phy_data(void)
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{
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write_char('0');
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write_char('x');
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write_char(hex[SFR_DATA_8 >> 4]);
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write_char(hex[SFR_DATA_8 & 0xf]);
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write_char(hex[SFR_DATA_0 >> 4]);
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write_char(hex[SFR_DATA_0 & 0xf]);
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}
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void print_reg(unsigned short reg)
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{
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reg_read(reg);
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print_sfr_data();
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}
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void print_sds_reg(unsigned char sds_id, unsigned char page, unsigned char reg)
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{
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sds_read(sds_id, page, reg);
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print_phy_data();
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}
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@@ -340,6 +416,72 @@ void cpy_4(__xdata unsigned char dest[], __xdata unsigned char source[])
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}
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void sds_config_p5(unsigned char mode)
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{
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// 2.5G
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// Q002110:6480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f
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// Q003610:0200 Q002804:0080 Q002807:1201 Q002809:0601 Q00280b:232c Q00280c:9217 Q00280f:5b50 Q002815:e7f1 Q002816:0443 Q00281d:abb0
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// Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100
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// 1G
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// Q002110:6480 Q002113:0400 Q002118:6d02 Q00211b:424e Q00211d:0002 Q00361c:1390 Q003614:003f
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// Q003610:0300 Q002404:0080 Q002407:1201 Q002409:0601 Q00240b:232c Q00240c:9217 Q00240f:5b50 Q002415:e7c1 Q002416:0443 Q00241d:abb0
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// Q000612:5078 Q000706:9401 Q000708:9401 Q00070a:9401 Q00070c:9401 Q001f0b:0003 Q000603:c45c Q00061f:2100
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reg_read_m(RTL837X_REG_SDS_MODES);
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sfr_mask_data(0, 0x1f, mode);
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reg_write_m(RTL837X_REG_SDS_MODES);
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print_string("\r\nRTL837X_REG_SDS_MODES: ");
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print_reg(RTL837X_REG_SDS_MODES);
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sds_write_v(0, 0x21, 0x10, 0x6400); // Q002110:6480
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sds_write_v(0, 0x21, 0x13, 0x0400); // Q002113:0400
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sds_write_v(0, 0x21, 0x18, 0x6d02); // Q002118:6d02
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sds_write_v(0, 0x21, 0x1b, 0x424e); // Q00211b:424e
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sds_write_v(0, 0x21, 0x1d, 0x0002); // 00211d:0002
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sds_write_v(0, 0x36, 0x1c, 0x1390); // Q00361c:1390
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sds_write_v(0, 0x36, 0x14, 0x003f); // Q003614:003f
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unsigned char page = 0;
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SFR_DATA_0 = 0x00;
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switch (mode) {
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case 0x02:
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print_string("SDS mode set to 0x02\r\n");
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SFR_DATA_8 = 0x03;
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page = 0x24;
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break;
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case 0x12:
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print_string("SDS mode set to 0x12\r\n");
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SFR_DATA_8 = 0x02;
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page = 0x28;
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break;
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default:
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print_string("Error in SDS Mode\r\n");
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return;
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}
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sds_write(0, 0x36, 0x10); // Q003610:0200
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sds_write_v(0, page, 0x04, 0x0080); // Q002804:0080
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sds_write_v(0, page, 0x07, 0x1201); // Q002807:1201
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sds_write_v(0, page, 0x09, 0x0601); // Q002809:0601
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sds_write_v(0, page, 0x0b, 0x232c); // Q00280b:232c
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sds_write_v(0, page, 0x0c, 0x9217); // Q00280c:9217
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sds_write_v(0, page, 0x0f, 0x5b50); // Q00280f:5b50
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sds_write_v(0, page, 0x15, 0xe7f1); // Q002815:e7f1
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sds_write_v(0, page, 0x16, 0x0443); // Q002816:0443
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sds_write_v(0, page, 0x1d, 0xabb0); // Q00281d:abb0
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sds_write_v(0, 0x06, 0x12, 0x5078); // Q000612:5078
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sds_write_v(0, 0x07, 0x06, 0x9401); // Q000706:9401
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sds_write_v(0, 0x07, 0x08, 0x9401); // Q000708:9401
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sds_write_v(0, 0x07, 0x0a, 0x9401); // Q00070a:9401
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sds_write_v(0, 0x07, 0x0c, 0x9401); // Q00070c:9401
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sds_write_v(0, 0x1f, 0x0b, 0x0003); // Q001f0b:0003
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sds_write_v(0, 0x06, 0x03, 0xc45c); // Q000603:c45c
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sds_write_v(0, 0x06, 0x1f, 0x2100); // Q00061f:2100
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}
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//
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// An idle function that sleeps for 1 tick and does all the house-keeping
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//
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@@ -374,8 +516,22 @@ void idle(void)
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if (cmp_4(sfr_data, linkbits_last)) {
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print_string("\r\n<new link: ");
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print_long_x(sfr_data);
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print_string(", was ");
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print_long_x(linkbits_last);
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print_string(">\r\n");
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unsigned char p5 = sfr_data[2] >> 4;
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unsigned char p5_last = linkbits_last[2] >> 4;
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cpy_4(linkbits_last, sfr_data);
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if (p5_last != p5) {
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if (p5 == 0x5) // 2.5GBit Mode
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sds_config_p5(0x12);
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else if (p5 == 0x2) // 1GBit
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sds_config_p5(0x2);
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print_string("\r\n: q01011d:8000: ");
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print_sds_reg(0x01, 0x01, 0x1d);
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print_string("\r\n: q00011d:8000: ");
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print_sds_reg(0x00, 0x01, 0x1d);
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}
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}
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}
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@@ -450,32 +606,6 @@ void setup_clock(void)
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}
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void print_sfr_data(void)
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{
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write_char('0');
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write_char('x');
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write_char(hex[SFR_DATA_24 >> 4]);
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write_char(hex[SFR_DATA_24 & 0xf]);
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write_char(hex[SFR_DATA_16 >> 4]);
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write_char(hex[SFR_DATA_16 & 0xf]);
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write_char(hex[SFR_DATA_8 >> 4]);
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write_char(hex[SFR_DATA_8 & 0xf]);
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write_char(hex[SFR_DATA_0 >> 4]);
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write_char(hex[SFR_DATA_0 & 0xf]);
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}
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void print_phy_data(void)
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{
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write_char('0');
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write_char('x');
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write_char(hex[SFR_DATA_8 >> 4]);
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write_char(hex[SFR_DATA_8 & 0xf]);
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write_char(hex[SFR_DATA_0 >> 4]);
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write_char(hex[SFR_DATA_0 & 0xf]);
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}
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/*
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* Write a register reg of phy phy_id, in page page
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* Data to be written must be in SFR a6/a7
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@@ -512,23 +642,6 @@ void phy_read(unsigned char phy_id, unsigned char device, unsigned short reg)
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}
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void phy22_read(unsigned char phy_id, unsigned short reg, unsigned char opt)
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{
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SFR_93 = phy_id; // 93
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SFR_94 = reg << 1 | opt; // 94
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SFR_EXEC_GO = 5;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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void print_reg(unsigned short reg)
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{
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reg_read(reg);
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print_sfr_data();
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}
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void sds_init(void)
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{
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/*
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@@ -993,13 +1106,6 @@ void setup_serial(void)
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}
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void print_phy22_reg(unsigned char phy_id, unsigned char reg, unsigned char opt)
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{
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phy22_read(phy_id, reg, opt);
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print_phy_data();
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}
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__code struct command commands[N_COMMANDS] = {
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{ "reset", 1 },
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};
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@@ -1078,25 +1184,11 @@ void bootloader(void)
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print_string("\r\nClock register: ");
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print_reg(0x6040);
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/*
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print_string("\r\n");
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for (int i = 0; i < 32; i ++) {
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for (int j = 0; j < 32; j ++) {
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print_phy22_reg(i, j, 0);
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write_char(' ');
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}
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print_string("\r\n");
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}
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print_string("\r\n");
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for (int i = 0; i < 32; i ++) {
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for (int j = 0; j < 32; j ++) {
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print_phy22_reg(i, j, 1);
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write_char(' ');
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}
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print_string("\r\n");
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}
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*/
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// q01011d:8000
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print_string("\r\n: q01011d:8000: ");
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print_sds_reg(0x01, 0x01, 0x1d);
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print_string("\r\n: q00011d:8000: ");
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print_sds_reg(0x00, 0x01, 0x1d);
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print_string("\r\n> ");
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char l = sbuf_ptr;
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