logicog
717247bc0e
Add MAC-EEE functionality
2025-10-11 13:09:47 +02:00
René van Dorst
f148bdad20
port: fix REG_SET() compiler warning.
...
Compiler
rtl837x_port.c:466: warning 116: right shifting more than size of object changed to zero
provided value is a uint16. So shifting it more then 16 cause this error.
Solution: cast the value to uint32_t.
2025-09-11 07:36:01 +02:00
logicog
44298f2b71
Add MSTP port state registers for STP
...
Each register holds the STP port state for one Forwarding ID (FID),
of which there 16 can be used by the RTL8372. The mapping between
FID and VLAN is done in the VLAN table. This allows the SoC
to maintain 16 different MSTP states.
In the register 2 bits per port are used to designate the following
(R)STP states
00 disable, 01 blocking, 10 learning, 11 forwarding
The STP listening state is not available.
2025-09-08 22:22:57 +02:00
René van Dorst
1b578405c0
Remove unused and not related to GPIO define
2025-09-07 14:56:13 +02:00
René van Dorst
74b8280d80
gpio: SOC only has 64 gpio not 96.
...
Remove BANK_A
Rename BANK_B to GPIO_00_31
Rename BACK_C to GPIO_32_63
Added also _INPUT, _DIRECTIOn registers
2025-09-06 17:04:25 +02:00
logicog
326d94f48d
Add support for STP
2025-08-30 18:42:46 +02:00
logicog
963d53335c
Add initial IGMP handling via ASIC
2025-08-29 17:23:14 +02:00
logicog
739ab5ef40
Cleanup of register definitions
2025-08-29 17:12:58 +02:00
logicog
ef742f8f19
Cleanup and fix flushing of L2 UC entries
2025-08-24 19:26:24 +02:00
logicog
81b7e4fa87
Identify pin configuration registers
2025-08-22 09:04:34 +02:00
logicog
0a05fe923e
Add port isolation methods
2025-08-22 07:15:49 +02:00
logicog
ad53165351
Introduce identified RX/TX control register names
2025-08-19 09:34:14 +02:00
logicog
c01014f1d8
Add more documentation on vlans and trunking
2025-07-26 19:10:24 +02:00
logicog
fcd1f85eb6
Add trunking support and initial L2 setup
2025-07-25 22:50:27 +02:00
logicog
0b30019769
Use names for I2C-controller registers
2025-07-23 08:34:26 +02:00
logicog
066edd672e
Add off-state for SDS
2025-07-22 09:34:40 +02:00
logicog
b0a41a5af6
Add support for RTL8372-devices with 2 SFP+ ports
2025-07-17 13:25:07 +02:00
logicog
84b84f5c32
Cleanup of L2 and mirroring features
2025-07-14 07:59:31 +02:00
logicog
b59f51b3ca
Cleanup of initialitation, make debug code conditional
2025-06-29 11:10:29 +02:00
logicog
5faf31cdb8
Moving PHY code to BANK1
2025-06-25 15:30:50 +02:00
logicog
73a0a7d137
Add banking support
2025-06-25 13:20:06 +02:00
logicog
b8352f9430
Implement ARP broadcast and make ping work
2025-06-23 17:57:54 +02:00
logicog
e4d477938d
Detect RTL8373 and name registers for GPIO. Enable RTL8224
2025-06-16 06:55:47 +02:00
logicog
c435feee45
Add REG_SET macro
2025-06-15 18:18:36 +02:00
logicog
9a69fac07a
Adding support for 2.5Gbit Ethernet modules
2025-06-14 09:52:15 +02:00
logicog
7eb7057787
use uint types
2025-06-14 09:12:07 +02:00
logicog
0485c21da0
Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
2025-06-13 20:36:49 +02:00
logicog
86aebcbf08
Add rtl837x_regs.h register header
2025-06-12 20:31:53 +02:00
logicog
2ae0b5caba
Moving registers to dedicated header so they can be better documented
2025-06-10 17:56:42 +02:00
logicog
René van Dorst
logicog