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Detect RTL8373 and name registers for GPIO. Enable RTL8224
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+7
-3
@@ -23,6 +23,7 @@
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*/
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#define SDS_SGMII 0x02
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#define SDS_1000BX_FIBER 0x04
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#define SDS_QXGMII 0x0d
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#define SDS_HISGMII 0x12
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#define SDS_HSG 0x16
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#define SDS_10GR 0x1a
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@@ -35,15 +36,18 @@
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5: 2.5Gbit
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*/
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#define RTL837X_REG_GPIOA 0x40
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#define RTL837X_REG_GPIO_A 0x40
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// BIT 4 resets RTL8224 on 9000-9XH
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#define RTL837X_REG_GPIOB 0x44
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#define RTL837X_REG_GPIO_B 0x44
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// Bit 1e cleared: SFP Module inserted on 9000-6XH (MOD_DEF0 pin)
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#define RTL837X_REG_GPIOC 0x48
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#define RTL837X_REG_GPIO_C 0x48
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// BIT 5 set: SIGNAL LOS of SFP module on 9000-6XH (RX_LOS pin)
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#define RTL837X_REG_GPIO_CONF_A 0x50
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// Configures IO direction for bank a
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#define REG_SET(r, v) SFR_DATA_24 = (v >> 24) & 0xff; \
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SFR_DATA_16 = (v >> 16) & 0xff; \
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SFR_DATA_8 = (v >> 8 & 0xff); \
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