Commit Graph
100 Commits
Author SHA1 Message Date
logicog 1a457c29ac Add support for 100FX modules and forcing 100FX 2026-05-30 23:08:44 +02:00
logicog 8c61010a84 Add support for configuring SFP modules speeds 2026-05-29 20:46:08 +02:00
logicog 32f9b91def Fix duplex setting on the CLI
Fixes commands such as
> port 1 duplex half
2026-05-22 21:07:29 +02:00
logicog 8ab2a6a9da Add URL decoding for password comparison. 2026-05-15 16:04:48 +02:00
logicog 9c668969d4 Fix POST upload request handling for Chrome browser
Chrome sends upload requests using POST with multipart/form-data
content type in multiple packets for the header part of the form-data.

Introduce a TSTATE_MULTIPART for the httpd server states that denotes
that so far only a part of the multipart header has been transmitted.
Once the full header has been transmitted, we change to TSTATE_POST
as for Firefox which sends all the multipart header in one piece.

The main further change required then is to make sure that the parsing
of the initial part of the multipart request is only parsed once and initially
to distinguish between configuration and firmware uploads.
2026-05-03 08:16:55 +02:00
logicog 8abbececd1 Add device description for ZX310S-4T2XH 2026-04-24 10:53:05 +02:00
logicog d6dbf4e4dd Add photos of ZX310S-4T2XH 2026-04-24 10:53:05 +02:00
logicog e2b3201c9f Add machine name for ZX310S-4T2XH 2026-04-24 10:53:05 +02:00
logicog a7f4543698 Add support for (Horaco) ZX310S-4T2XH
Add support for the ZX310S-4T2XH switch, which is a 4x2.5GBit + 1x10GBit + SFP
device. The device does not have any branding and is sold under different
brand names, in particular by Horaco. There is no branding on either label
nor PCB.

CPU: RTL8372
Flash: 2MByte Winbond W25Q16DV
10GBit PHY: RTL8261BE

UART header present, but solder holes are filled with solder that needs
removal, first, e.g with a 1.2mm drill.

The original firmware uses 57600baud 8N1
2026-04-24 10:53:05 +02:00
logicog 2e0e55967c Do not send SFP info if no SFP port present 2026-04-24 10:53:05 +02:00
logicog 7877ce60f3 Add support for 5G link speeds, make 5G/10G LED blue 2026-04-24 10:53:05 +02:00
logicog a3dd25e0fe Add SDS parameter for RTL8261 setup 2026-04-24 10:53:05 +02:00
logicog 441340a4d4 Add SMI configuration support for dual 10G Ethernet 2026-04-24 10:53:05 +02:00
logicog 9a3f8c359d Enable 10g EEE on init 2026-04-24 10:53:05 +02:00
logicog 63ab6500c0 Add 10G/5G speed configuration/display 2026-04-24 10:53:05 +02:00
logicog ec5f74bbed Add is10g_port field in phy_settings 2026-04-24 10:53:05 +02:00
logicog a597d2d08b Fix EEE control register address and add 5G/10G EEE defines
Register RTL8373_EEE_CTRL_BASE did not actually exist at 0x606c,
instead RTL837X_EEE_STATUS is actually not only a status, but also
a control register for EEE enable/disable at the MAC.

The defines are not actually register bits, but port EEE settings,
so move them to rtl837x_port.h while adding 5G/10G flags.
2026-04-24 10:53:05 +02:00
logicog abc9cb7afd Add 5G speed display support and 5/10G EEE display/settings 2026-04-24 10:53:05 +02:00
logicog 6d579c4f00 Add speed bits for 5G/10G EEE 2026-04-24 10:53:05 +02:00
logicog c342964327 Add SDS init for RTL8261BE connection 2026-04-24 10:53:05 +02:00
logicog fd3a272255 Add RTL8261BE PHY configuration
Add configuration of the RTL8261BE PHY on startup.
2026-04-24 10:52:24 +02:00
logicog 4f4f69ecc1 Handle RTL8261BE SerDes configuration
The RTL8261BE uses a 10GBit QSGMII connection. Add handler for initial
configuration of the SerDes speed and upon link changes.
2026-04-24 10:52:24 +02:00
logicog c8e21b394b Add forgotten register RTL837X_REG_LED3_2_SET3
The register had been forgotten in the LED configuration registers,
add the register definition and print out the content in leds_dump().
2026-04-24 10:50:53 +02:00
logicog c34249b90a Add n_10g property in machine structure
This uint8_t field corresponds to the n_sfp field and gives the number
of 10G ports for the machine. The values can be 0, 1, 2 for known machines,
all currently supported machines do not have any 10G ports, so no
need to change any entries in machine.c
2026-04-24 10:50:53 +02:00
logicog e280ccd2f9 Use RTL descriptor definition 2026-04-24 08:42:00 +02:00
logicog baa4e5e142 Use header structures of TX and RX, add dot1q for management VLAN TX 2026-04-22 22:36:26 +02:00
logicog b53e7e1a06 Add NOTHS macro 2026-04-22 22:36:26 +02:00
logicog 14b45735e2 Cleanup STP, use new frame descriptor definitions 2026-04-22 22:36:26 +02:00
logicog 946e80cebe Add frame descriptor structure 2026-04-22 22:36:26 +02:00
logicog e2df95ba90 Cleanup DHCP client code 2026-04-22 22:36:26 +02:00
logicog 570ee6c995 Move initialization routines to BANK2 2026-04-22 22:36:26 +02:00
logicog e2717ef7ca Count pages instead of bytes reading config in execute_config() 2026-04-17 11:37:15 +02:00
logicog 1769528420 Introduce global error variable, check during config execution 2026-04-16 22:01:51 +02:00
logicog c3530aaafc Handle error when configuration file cmd too long 2026-04-14 18:00:29 +02:00
logicog 1683eef94b Fix bug where cmd_words[] is not properly initialized 2026-04-14 05:16:45 +02:00
logicog 036d9ca229 Add port isolation cmd 2026-04-13 20:13:28 +02:00
logicog b7ad67d336 Make port isolation API available 2026-04-13 18:15:01 +02:00
logicog 4440bcc43a Fix reading configuration over flash block boundaries 2026-04-09 22:34:32 +02:00
logicog fce64ac368 Fix display of VLANs for ports 2026-03-22 13:45:42 +01:00
logicog c530ec4ae3 Fix missing assignment of bank when html_data.c code is generated 2026-03-18 08:34:26 +01:00
logicog 090283d538 Add retry mechanism for xhttp requests to make Chrome happy 2026-03-16 17:32:50 +01:00
logicog 7e3a0f5d8f Allow javascript to modify svg styles for Firefox version >140 2026-03-16 17:32:15 +01:00
logicog fa37940075 Control xhttp concurrency 2026-03-10 06:16:18 +01:00
logicog ed8dc0f43c Fix bug in atoi_hex when uneven number of digits parsed
We fix a bug in atoi_hex when parsing an unneven number of digits
by rotating the entire number 4 bits right as would have been
done if the number had been preceded by a 0 to make the number
of digits even.
2026-03-09 06:48:24 +01:00
logicog 7949975191 Add backend support for bandwidth control 2026-03-08 20:55:50 +01:00
logicog 1374272db6 Add simulation support for bandwidth control 2026-03-08 20:55:50 +01:00
logicog 20fb626cc1 Make bandwidth control page accessible 2026-03-08 20:55:50 +01:00
logicog 31a488e4e9 Add web page for bandwidth control 2026-03-08 20:55:50 +01:00
logicog 14bc823024 Add reg_bit_test function 2026-03-08 20:55:50 +01:00
logicog 04ab083652 Add documentation for bandwidth control 2026-03-08 19:04:48 +01:00
logicog 1836c7dcb6 Add Bandwidth control for ingress/egreess at port 2026-03-08 19:04:48 +01:00
logicog eb13d4ab04 Add iniital implementation of bandwidth control 2026-03-05 07:43:11 +01:00
logicog dc16b25d62 Add support for the SWTG018AS-A V2.0 8+1 unmanged switch
The SWTG018AS-A V2.0 is an 8x2.5GBit/s port + 1 SFP+ port unmanged device
It is sold in an unbranded casing e.g. by Ampcom.
Hardware:
SoC: RTL8373N
Additional PHY: RTL8224
Flash: Puya P25D40SH (4MBit, slimmer, not standard SOP-8 package!)
LEDs: 1 Green + 1 Orange per Ethernet port (green designates 2.5GBit)
      1 Green LED for the SFP+ port

The photos already show a modified PCB: Unpopulated resistors R52 and R53
have been bridged in order to enable the serial console. The smaller flash
memory chip at U2 has been replaced with a Windbond 128MBit standard-sized
SOIC-8 chip in order to easily use SOIC clamps to flash the device. Also
the serial header has been populated.
2026-02-27 20:11:53 +01:00
logicog 70127018da Add device photos of KeepLink KP-9000-6XHML-X2 2026-02-25 18:07:54 +01:00
logicog 734cce381a Fix reset button GPIO-Number for MACHINE_KP_9000_6XHML_X2 2026-02-25 06:28:49 +01:00
logicog dfc96761b3 Add support for history editing 2026-02-24 19:57:22 +01:00
logicog 94d4ace88b Add support for command line editing
The current code for entering commands via the serial CLI is completely
refactored and moved out of rtlplayground.c into a separate file cmd_edit.c
putting code into BANK2.
The serial ring buffer sbuf[] is now exclusively used for receiving
keys, including escape sequences (DEL will generate a 4-byte escape
sequence). The command is now held in cmd_buffer. This reduces
XMEM use, because the serial buffer can be much smaller.

Supported is only editing the current command line via backspace, del,
cursor left and right.

Because the code cannot distinguish escape sequences which are not yet
complete (because the serial isr has not yet put all characters into
the serial buffer) from the dozens of unsupported ones (F-keys/home,
Page up/down, cursor up/down...) they are ignored and remain in the
serial buffer until the ring-pointer overwrites them. This is standard
behaviour for consoles, which will print out garbage for unsupported
characters. In this implementation, the command line buffer and the
visible command line in the terminal are always synced, so garbage
can be removed again by ediing the line.

The code makes several redundant checks in order to prevent race-conditions
between the serial ISR and the comand-editing code.
2026-02-24 19:57:22 +01:00
logicog 1b43addb11 Fix MACHINE_KP_9000_6XHML_X2: swap SFP-ports remove unnecessary LED-MUX
The left and right SFP ports were swapped in the machine structure. They
are now correctly identified a comment is added. The custo LED-mux
is removed again, as this was accidentally added for demonstration
purposes. It is not necessary, as the device uses the default.
2026-02-13 07:53:29 +01:00
logicog d29adafe3c Use generic led configuration 2026-02-08 20:25:01 +01:00
logicog 59894e68cb Add LED-pad mapping 2026-02-08 20:24:58 +01:00
logicog 6af072eb2c Add LED configuration in machine profile 2026-02-08 20:24:05 +01:00
logicog 8cae3f1212 Add generic LED configuration support 2026-02-08 20:23:30 +01:00
logicog 9aaddcd9b9 Reduce DSEG usage as we need 1 OSEG byte 2026-02-08 20:23:30 +01:00
logicog 196e430ec6 Remove debug output 2026-02-08 20:23:30 +01:00
logicog 9424aa3a3b LED configuration support 2026-02-08 20:23:30 +01:00
logicog 7a57416e4c Add MACHINE_HG0402XG_V1_1 2026-02-08 20:23:29 +01:00
logicog 47878ac580 Add more printout 2026-02-08 16:46:56 +01:00
logicog d83f91f9e8 Fix Auto-negotiation
Commit 7f4c276 used the wrong MMD device
for use with the auto-negotiation page:
- phy_write(port, PHY_MMD_AN, 0x00, 0x3200);	// Restart AN
+ phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3200);	// Restart AN

Fix this.
2026-02-08 16:46:56 +01:00
logicog 708b6b7f28 Use new signatures for vlan_create and phy-settings 2026-02-08 16:46:56 +01:00
logicog 9d07416641 Convert phy_set_duplex phy_set_speed to use struct phy_settings 2026-02-08 16:46:56 +01:00
logicog 4747eac9bf Reduce DSEG usage for parameters used in port/vlan configuration
Currently 5 Bytes are used by the port and vlan configuration:
--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
	.area DSEG    (DATA)
_port_ingress_filter_PARM_2:
	.ds 1
_vlan_create_PARM_2:
	.ds 2
_vlan_create_PARM_3:
	.ds 2

They are used for passing parameters. Use __xdata to pass the
parameters instead.
2026-02-08 16:03:37 +01:00
logicog ecf152990f Fix MACHINE_KP_9000_6XHML_X2: the SDS ids were swapped 2026-02-08 16:03:37 +01:00
logicog ea230615f9 Use a MAC address based on the SoC's UUID
We use the SoC's UUID to generate a fixed MAC for a particular
switch device. The MAC generated uses a Realtek prefix and then
is followed by 3 bytes genertaed from the first 3 bytes of the
UUID xored with the last byte in order to prevent being able
to deduce the UUID from the public MAC.
2026-02-08 15:49:49 +01:00
logicog 9d4eef2dd6 Add support for management vlan
This adds support for the verification of a mangement vlan.
When enabled, then the switch's CPU will not listen to any packets
that are not tagged with the respective VLAN tag.
On the command line this is enabled by setting:
> vlan <vlan> mgmt

Setting the vlan ID of the management VLAN to 0 or 1 disables
the mangement VLAN function.
2026-01-29 19:56:01 +01:00
logicog f48c84b18e Document checksum calculation offload in hardware 2026-01-18 07:50:38 +01:00
logicog 3bfcabbb99 Add main directory for includes 2026-01-18 07:50:38 +01:00
logicog 5eecab4844 Move SYS_TICK_HZ to rtl837x_common.h
The definition is needed everywhere in the code where the ticks
need to be related to seconds.
2026-01-18 07:50:38 +01:00
logicog fd1d14a3e7 Use main directory for includes in httpd 2026-01-18 07:50:38 +01:00
logicog 34cebe5971 Enable UDP for DHCP in uIP 2026-01-18 07:50:38 +01:00
logicog 4269745521 Make dhcp client implementation available 2026-01-18 07:50:38 +01:00
logicog af3be9a067 Initial DHCP implementation 2026-01-18 07:39:49 +01:00
logicog e8a719d911 Add itoa function 2026-01-18 07:39:49 +01:00
logicog d1d5d5e18f Consistently use banked externally visible functions 2026-01-17 17:54:31 +01:00
logicog 892920a627 Mover phy code to bank 2 as bank 1 already overflows 2026-01-17 17:54:31 +01:00
logicog eb0e90df5c Enable bank 2 in Makefile 2026-01-17 17:54:31 +01:00
logicog 2ce168883b Add support for banks > 1 2026-01-17 17:54:31 +01:00
logicog 300f599551 Fix output of l2 command 2026-01-17 12:56:43 +01:00
logicog 73a355cff5 Add L2-table access method defintions 2026-01-17 12:56:43 +01:00
logicog e53f5e7134 Add L2 entry deletion support via web 2026-01-17 12:56:43 +01:00
logicog 3509f7da04 Add web functionality to delete L2 entries 2026-01-16 18:04:22 +01:00
logicog 55d10ae3fc Make L2 information page available in navigation menu 2026-01-16 18:04:22 +01:00
logicog 88e706c295 Add simulation support for L2 entries in web 2026-01-16 18:04:22 +01:00
logicog e59158e006 Add backend support for L2 entries in web 2026-01-16 18:04:22 +01:00
logicog e0c9338357 Add support in web-interface for displaying L2 entries 2026-01-16 18:04:22 +01:00
logicog e7df748b6a Fix error in calculating VLAN for L2 entries 2026-01-16 18:04:22 +01:00
logicog 84fe44cc9a Add httpd backend implementation for MIB counter requests 2026-01-15 18:07:56 +01:00
logicog 6326428406 Add simulation of MIB counters 2026-01-15 18:07:56 +01:00
logicog f33c4e3dc9 Add display of MIB counters to Web-Interface 2026-01-15 18:07:56 +01:00
logicog 66c58a50df Fix typo in register address for RLDP Leds 2026-01-13 18:02:21 +01:00
logicog 48c12fa0bb Correct TX and RX good MIB counter
The counters for good TX and RX packages were swapped. Fix this
and also use propper names for the counters.
2026-01-11 07:51:18 +01:00