René van Dorst
9dafeab490
Added SFR_NIC_DATA_U16LE and SFR_NIC_RING_U16LE.
...
Let's use sfr16 for NIC data and ring.
SFR define can so reordered to it does the BE to LE swap for us.
2025-09-01 09:20:36 +02:00
René van Dorst
af0135bcce
Add sfr16 SFR_REG_ADDR_U16.
...
So instead do it manual split a uint16_t in to two uint8_t.
The compiler can do it, so reduces user error.
Note: compiler writes the lower/LSB part first.
When that is importent this can´t be used.
Assembly is still the same except note above.
2025-09-01 09:20:36 +02:00
René van Dorst
7ff028303d
Add phy_write() with bit_mask lookup inside the function.
...
Move the lookup saves a lot of instructions for every phy_write() call.
Assembly diff for one change.
< ; rtl837x_phy.c:240: phy_write_mask(bit_mask[port], 0x07, 0x00, 0x3200); // Enable AN
< mov dpl,r5
< mov dph,r6
---
> ; rtl837x_phy.c:240: phy_write(port, 0x07, 0x00, 0x3200); // Enable AN
> mov _phy_write_PARM_2,#0x07
1345,1359c1019,1024
< movc a,@a+dptr
< mov r5,a
< inc dptr
< clr a
< movc a,@a+dptr
< mov r6,a
< mov _phy_write_mask_PARM_2,#0x07
< clr a
< mov _phy_write_mask_PARM_3,a
< mov (_phy_write_mask_PARM_3 + 1),a
< mov _phy_write_mask_PARM_4,a
< mov (_phy_write_mask_PARM_4 + 1),#0x32
< mov dpl, r5
< mov dph, r6
< lcall _phy_write_mask
---
> mov _phy_write_PARM_3,a
> mov (_phy_write_PARM_3 + 1),a
> mov _phy_write_PARM_4,a
> mov (_phy_write_PARM_4 + 1),#0x32
> mov dpl, r7
> lcall _phy_write
Replace all phy_write_mask(bit_mask[<var>], ...) to phy phy_write(<var>, ...).
2025-09-01 00:12:12 +02:00
René van Dorst
d6ea9be4c0
rename phy_write() to phy_write_mask().
...
It seems that bit_mask[phy] lookup is expensive and it used in many places.
But most of the time we only addressing a single phy.
2025-09-01 00:07:27 +02:00
logicog
829fbf707a
Use uip for mac-address, enable STP packages
2025-08-30 18:43:31 +02:00
logicog
83dcd22863
Add STP packet identification
2025-08-30 08:29:25 +02:00
logicog
81b7e4fa87
Identify pin configuration registers
2025-08-22 09:04:34 +02:00
logicog
52f8366d03
Improve command parser to work with other than serial buffer
2025-08-21 16:11:22 +02:00
logicog
940ee648df
Use definition of NSFP in header file
2025-08-20 10:19:07 +02:00
logicog
ad53165351
Introduce identified RX/TX control register names
2025-08-19 09:34:14 +02:00
logicog
0fb4fafdb2
strtox now returns copied length
2025-08-05 09:34:44 +02:00
logicog
8b1b4aff68
Fix parsing of mirror command, fix parsing of serial buffer beyond wrap arond, add bulk reading of flash and start of config file parser
2025-07-28 23:04:08 +02:00
logicog
a5d156a645
Fix dropping of RTL VLAN tag for 802.1Q Tag, add L2 configuration
2025-07-25 22:51:18 +02:00
logicog
0b30019769
Use names for I2C-controller registers
2025-07-23 08:34:26 +02:00
logicog
96a108e891
Use common SDS configuration code also for RTL8224
2025-07-23 08:01:33 +02:00
logicog
bcc58d2965
Make RTL8224 work
2025-07-22 19:05:27 +02:00
logicog
8fee855da2
Separate code for rtl8272 from rtl8373 for readability and stability against accidental changes
2025-07-22 09:42:56 +02:00
logicog
ccd8bf1633
Cleanup
2025-07-17 23:29:20 +02:00
logicog
b0a41a5af6
Add support for RTL8372-devices with 2 SFP+ ports
2025-07-17 13:25:07 +02:00
logicog
d66931acdf
Adding initial http daemon implementation
2025-07-13 12:03:40 +02:00
logicog
b192a87cab
Cleaning up printouts for debugging of uIP
2025-07-11 16:36:16 +02:00
logicog
8b761cfcc8
Add UIP stack. Still lots of debug output on packets...
2025-07-11 14:54:57 +02:00
logicog
e0924314b4
Add memcpy function for __xdata
2025-07-06 09:53:28 +02:00
logicog
65c2336313
Use external command parser module. Add support for mirroring
2025-07-05 09:24:16 +02:00
logicog
2d8c0efabd
Add 802.1Q VLAN and PVID support. Support VLAN tag at CPU-port
2025-07-04 09:17:10 +02:00
logicog
997d85ba02
Add basic VLAN configuration
2025-07-02 11:57:15 +02:00
logicog
6f90e1db53
Add support for changing Ethernet speeds
2025-06-29 20:06:53 +02:00
logicog
b59f51b3ca
Cleanup of initialitation, make debug code conditional
2025-06-29 11:10:29 +02:00
logicog
5faf31cdb8
Moving PHY code to BANK1
2025-06-25 15:30:50 +02:00
logicog
73a0a7d137
Add banking support
2025-06-25 13:20:06 +02:00
logicog
b8352f9430
Implement ARP broadcast and make ping work
2025-06-23 17:57:54 +02:00
logicog
2776df9ca8
Make RX of packets work
2025-06-21 16:18:19 +02:00
logicog
dd039494c2
Add more RTL8224 config
2025-06-21 05:58:55 +02:00
logicog
869db02865
Emable RTL8224 PHY. Better implementation of sleep/delay timer
2025-06-17 18:21:15 +02:00
logicog
e4d477938d
Detect RTL8373 and name registers for GPIO. Enable RTL8224
2025-06-16 06:55:47 +02:00
logicog
85cb2a52a5
Cleanup
2025-06-15 18:26:27 +02:00
logicog
b49f2aa16f
Add initial support for RTL8373
2025-06-15 18:24:23 +02:00
logicog
9a69fac07a
Adding support for 2.5Gbit Ethernet modules
2025-06-14 09:52:15 +02:00
logicog
37ca55392a
Add support for 10G Fiber
2025-06-14 09:12:24 +02:00
logicog
0485c21da0
Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
2025-06-13 20:36:49 +02:00
logicog
b41410ce6b
Cleanup
2025-06-12 20:33:35 +02:00
logicog
8c8b92ed65
Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit
2025-06-12 20:32:36 +02:00
logicog
8243a454de
Adding support for link status display
2025-06-10 17:57:28 +02:00
logicog
c54227f057
Fix SFR_DATA access, make internal switch work
2025-06-09 11:22:52 +02:00
logicog
c5d7628ea0
Adding support for the ASIC second counter register and sleeping
2025-06-06 20:49:15 +02:00
logicog
9f22c49af7
Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud
2025-06-05 20:15:42 +02:00
logicog
73a6f0f311
Adding more flash functionality and image documentation
2025-05-14 20:40:44 +02:00
logicog
7493089c39
Adding DIO for flash access
2025-05-11 20:29:31 +02:00
logicog
3a953bba47
More commands, fixing strange sdcc behaviour for clock setting defines
2025-05-11 18:28:08 +02:00
logicog
6d3214d13d
More initial documentation
2025-05-10 17:01:33 +02:00
René van Dorst
logicog
logicog