mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-10-29 17:54:14 +08:00
João Silva
98369c37fe
nic: move other nic functions into the dedicated nic files uip: alloc buffer multiple of 8 bytes Signed-off-by: João Silva <jgc3silva@gmail.com>
112 lines
4.8 KiB
Markdown
112 lines
4.8 KiB
Markdown
# The CPU Port
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The RTL827x provide a CPU Port for a NIC on the 8051 side of the SoC.
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## Receiving packets
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In order to receive packets on the ASIC side, bit 0 of RTL837X_REG_RX_CTRL
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(0x785c) must be set. Further bits in the register enable reception of various
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kinds of Ethernet frames. They should all be set in order for the firmware
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to decide what to do with them. To drop packets with incorrect Ethernet frame CRC
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already by the ASIC, clear bit 2 of this register.
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Packets are received by either polling the RTL837X_REG_RX_AVAIL register
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(0x7874), which will be > 0 if data is within a ring-buffer on the ASIC side
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of the SoC. Alternatively, an interrupt can be triggered (EX1).
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Data is transferred to the 8051 side by calling an SFR function. First, the
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frame header of the received frame will be copied over. For this, provide
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the destination memory location in xdata memory in SFRs B3 and B4 (little
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endian), the source location on the ASIC-side in SFRs B5/B6 (also little
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endian, found in RTL837X_REG_RX_RINGPTR, 0x787c) and execute the function
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by setting SFR_NIC_CTRL (B7) to the length to be transferred divided by 8,
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i.e. 1.
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The frame header has the following format:
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```
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SS xx xx xP LL LH xx xx
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SS: 8-bit sequence number
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P: Port number
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LHLL: Length of Ethernet frame (little endian)
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xx: Unknown
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```
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Next, transfer the actual packet over by repeating the SFR function with a
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pointer to the frame on the ASIC directly after the frame header and a
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length as given by the length in the frame header + 7, again divided by 8.
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The RX ring's inclusive last slot is configured as `0x4ff`, giving a byte
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range of `0x0000` through `0x27ff`. If the descriptor occupies the last slot
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at `0x27f8`, its payload starts at `0x0000`, not `0x2800`. The RX copy code
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normalizes that starting address before DMA. It relies on the hardware to
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wrap transfers that start inside the ring and cross its end, as observed
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on SWTGW218AS. Programming an initial address of `0x2800` does not wrap
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and can instead read zeros or stale TX data outside the RX ring.
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Frame lengths are checked against `UIP_CONF_BUFFER_SIZE` before copying.
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DMA works in whole eight-byte units. `UIP_CONF_BUFFER_ALLOC_SIZE` rounds
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the backing storage up to the next complete word: 1,560 bytes for the
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1,556-byte logical frame limit. This padding allows a maximum-size frame
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to be transferred directly without a separate tail copy. The logical
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frame limit and advertised MSS are unchanged.
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The received frame will have an RTL proprietary Ethernet frame type of
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0x8899 (RRPC) where normally the frame type 0x0800 for IPv4 would be located.
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Further 6 bytes follow describing the frame, before the normal IPv4 data
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starts. A documentation can be found here:
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[TAG8899_COMMIT](https://github.com/torvalds/linux/commit/1521d5adfc2b557e15f97283c8b7ad688c3ebc40)
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After copying over header and frame, the frame is marked read in the ring
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buffer on the ASIC side by writing 0x1 to RTL837X_REG_RX_DONE (0x784c).
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## Transmissing packets
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Packets are transmitted by preparing a frame-header plus frame in xdata memory
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and transferring both to the ASIC side via the SFRs. The ASIC will transmit
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packets if bit 0 of RTL837X_REG_TX_CTRL (0x7860) is set.
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```
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SS 07 00 00 LL LH 00 00
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SS: 8-bit sequence number
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07: Enables header and TCP checksum offloading to ASIC
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LHLL: Length of the Ethernet frame
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```
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The Ethernet frame data starts immediately after the frame header in xdata
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memory. The frame is transferred to the ASIC side by setting SFRs B3 and B4
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to the xdata source address of the frame header, and the ring pointer to the
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free space indicated by register 0x7890 multiplied by 8 and the MSB set.
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The length is given by the length of the frame plus 15, divided by 8.
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Writing 0x1 to register 0x7850 will transmit the frame. The Ethernet frame
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checksum and the TCP checksum are automatically calculated (offloaded) by the
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ASIC before transmitting on the wire.
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## The RTL tag words
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The frame header uses the Realtek Remote Control Protocol (RRCP) format or
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the like.
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The `flags` word:
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```
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bit15 EFID_EN | 14:12 EFID | 11 PRI_EN | 10:8 PRI |
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bit7 KEEP | 6 VSEL | 5 LEARN_DIS | 4:0 VIDX
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```
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All fields are in network byte order.
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* `EFID_EN`, `EFID`: look the destination up under this filtering ID
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instead of the port's own
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* `PRI_EN`, `PRI`: force the given priority on the frame
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* `KEEP`: keep the 802.1Q tagging of the frame exactly as injected,
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bypassing the egress tagging rules of the port
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* `VSEL`, `VIDX`: classify the frame into the VLAN at this index of the
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VLAN table
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* `LEARN_DIS`: do not learn the source address from this frame
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The `pmask` word: bit 15 is `ALLOW`, bits 14 to 0 are a port mask.
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* `ALLOW` clear: the mask is the egress set, the frame goes to exactly
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the ports given
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* `ALLOW` set: the ASIC looks the destination up as usual and the mask
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only limits which ports the result may use
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