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54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
#ifndef _RTL837X_REGS_H_
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#define _RTL837X_REGS_H_
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#define RTL837X_REG_HW_CONF 0x6040
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// Bits 4 & 5: CLOCK DIVIDER from 125MHz for Timer
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#define RTL837X_REG_LED_MODE 0x6520
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// Defines the LED Mode for steering the Port LEDS and the System LED
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// BIT 17 set: LED solid on
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// Bytes 0/1 hold the LED mode, e.g. serial, RTL8231?
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// Blink rate is defined by setAsicRegBits(0x6520,0xe00000,rate);
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#define RTL837X_REG_SMI_CTRL 0x6454
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#define RTL837X_REG_RESET 0x0024
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// Writing 0x01 into this register causes a reset of the entire SoC
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#define RTL837X_REG_SEC_COUNTER 0x06f4
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// Used for counting seconds
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#define RTL837X_REG_SDS_MODES 0x7b20
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/*
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* 5 Bits each give the state of the 2 SerDes of the RTL8372
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* Values are:
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*/
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#define SDS_SGMII 0x02
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#define SDS_1000BX_FIBER 0x04
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#define SDS_HISGMII 0x12
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#define SDS_HSG 0x16
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#define SDS_10GR 0x1a
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#define RTL837X_REG_LINKS 0x63f0
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/* Each nibble encodes the link state of a port.
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Port 0 appears to be the CPU port
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The RTL8372 serves ports 4-7, port 3 is the RTL8221
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2: 1Gbit
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5: 2.5Gbit
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*/
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#define RTL837X_REG_GPIOA 0x40
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// BIT 4 resets RTL8224 on 9000-9XH
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#define RTL837X_REG_GPIOB 0x44
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// Bit 1e cleared: SFP Module inserted on 9000-6XH (MOD_DEF0 pin)
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#define RTL837X_REG_GPIOC 0x48
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// BIT 5 set: SIGNAL LOS of SFP module on 9000-6XH (RX_LOS pin)
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#define REG_SET(r, v) SFR_DATA_24 = (v >> 24) & 0xff; \
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SFR_DATA_16 = (v >> 16) & 0xff; \
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SFR_DATA_8 = (v >> 8 & 0xff); \
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SFR_DATA_0 = v & 0xff; \
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reg_write(r);
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#endif
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