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https://github.com/logicog/RTLPlayground.git
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logicog
d4e2b9872d
Fix several bugs found in the write-flash code during installer coding. Move all flash functions into CODE0. This is required to share these functions with the installer image (currently they are duplicated so they are not within the CODE1 segment). De-magics all Flash command codes based on the Winbond W25Q32JV datasheet.
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/* SFR control registers for switch register access */
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__sfr __at(0xa0) SFR_EXEC_GO;
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__sfr __at(0xa1) SFR_EXEC_STATUS;
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__sfr16 __at(0xa2a3) SFR_REG_ADDR_U16;
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__sfr __at(0xa2) SFR_REG_ADDRH;
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__sfr __at(0xa3) SFR_REG_ADDRL;
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__sfr16 __at(0xa6a7) SFR_DATA_U16;
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__sfr32 __at(0xa4a5a6a7) SFR_DATA_U32;
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__sfr32 __at(0xa7a6a5a4) SFR_DATA_U32LE;
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__sfr __at(0xa4) SFR_DATA_24;
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__sfr __at(0xa5) SFR_DATA_16;
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__sfr __at(0xa6) SFR_DATA_8;
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__sfr __at(0xa7) SFR_DATA_0;
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// Command bytes to write to SFR_EXEC_GO
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#define SFR_EXEC_READ_REG 1
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#define SFR_EXEC_WRITE_REG 3
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#define SFR_EXEC_READ_SDS 5
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#define SFR_EXEC_WRITE_SDS 7
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#define SFR_EXEC_READ_SMI 9
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#define SFR_EXEC_WRITE_SMI 11
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/* SFR control registers for phy access via SMI/MDIO */
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__sfr16 __at(0xc2c3) SFR_SMI_REG_U16;
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__sfr __at(0xc2) SFR_SMI_REG_H;
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__sfr __at(0xc3) SFR_SMI_REG_L;
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__sfr __at(0xc4) SFR_SMI_DEV;
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__sfr __at(0xc5) SFR_SMI_PHYMASK;
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#define SFR_SMI_PHY SFR_DATA_16
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/* Extended IRQ EIE register for external interrupts */
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__sfr __at(0xe8) EIE;
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__sbit __at(0xe8) EX2;
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__sbit __at(0xe9) EX3;
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/* EXIF additional external IRQ control register */
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__sfr __at(0x91) EXIF;
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/* Extended IRQ EIP register for external interrupt priority */
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__sfr __at(0xf8) EIP;
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__sbit __at(0xf9) PX3;
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/* SFR control registers for serial communication */
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__sfr __at(0xc8) T2CON;
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__sfr __at(0xca) RCAP2L;
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__sfr __at(0xcb) RCAP2H;
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/* SFR Bank control register: 0x0-3f. A value of 0 is bank 1 */
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__sfr __at(0x96) PSBANK;
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// SFR used to store return bank for trampoline
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__sfr __at(0xbb) SFR_BANK_RET;
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__sfr __at(0x8e) CKCON;
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__sfr __at(0x97) SFR_97; // HADDR?
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__sfr __at(0xb9) SFR_b9;
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__sfr __at(0xba) SFR_ba;
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// Clause 22 PHY access ???
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__sfr __at(0x93) SFR_93;
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__sfr __at(0x94) SFR_94;
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/* FLASH controller SFRs */
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__sfr __at(0x80) SFR_FLASH_EXEC;
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__sbit __at(0x82) SFR_FLASH_EXEC_GO;
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__sbit __at(0x80) SFR_FLASH_EXEC_BUSY;
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__sfr __at(0xb1) SFR_FLASH_CMD_R;
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__sfr __at(0xb2) SFR_FLASH_CMD;
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__sfr __at(0xbc) SFR_FLASH_CONFIG;
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__sfr __at(0x9b) SFR_FLASH_CONF_DIV;
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__sfr __at(0x9c) SFR_FLASH_CONF_RCMD;
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__sfr __at(0x9d) SFR_FLASH_DUMMYCYCLES;
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__sfr __at(0x9a) SFR_FLASH_MODEB;
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__sfr __at(0x9e) SFR_FLASH_TCONF;
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__sfr __at(0xaf) SFR_FLASH_DATA24;
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__sfr __at(0xae) SFR_FLASH_DATA16;
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__sfr __at(0xad) SFR_FLASH_DATA8;
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__sfr __at(0xac) SFR_FLASH_DATA0;
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__sfr __at(0xab) SFR_FLASH_ADDR16;
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__sfr __at(0xaa) SFR_FLASH_ADDR8;
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__sfr __at(0xa9) SFR_FLASH_ADDR0;
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/*
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* NIC Interface
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* CAREFUL: This is now Little Endian
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*/
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__sfr __at(0xb7) SFR_NIC_CTRL;
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__sfr16 __at(0xb4b3) SFR_NIC_DATA_U16LE;
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__sfr __at(0xb3) SFR_NIC_DATA_L;
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__sfr __at(0xb4) SFR_NIC_DATA_H;
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__sfr16 __at(0xb6b5) SFR_NIC_RING_U16LE;
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__sfr __at(0xb5) SFR_NIC_RING_L;
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__sfr __at(0xb6) SFR_NIC_RING_H;
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