mirror of
https://github.com/logicog/RTLPlayground.git
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251 lines
6.6 KiB
C
251 lines
6.6 KiB
C
/*
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* This is a driver implementation for the Port features for the RTL827x platform
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* This code is in the Public Domain
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*/
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// #define REGDBG
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#include <stdint.h>
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#include "rtl837x_common.h"
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#include "rtl837x_sfr.h"
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#include "rtl837x_regs.h"
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#pragma codeseg BANK1
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extern __code uint16_t bit_mask[16];
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extern __xdata uint8_t minPort;
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extern __xdata uint8_t maxPort;
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extern __xdata uint8_t nSFPPorts;
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extern __xdata uint8_t sfr_data[4];
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__xdata uint32_t l2_head;
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/*
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* Table access registers of the RTL837x
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* See e.g. RTL8366/RTL8369 datasheet for explanation
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*/
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#define RTL837X_TBL_CTRL 0x5cac
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/* Bytes in control register: EE EE TT CC: EE: Entry, TT: Table type, CC: Command
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* CC: BIT 0: 01: Execute. Bit 1: 1: WRITE, 0: READ
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* TT: 04: L2-table, 03: VLAN-table
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*/
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#define TBL_L2_UNICAST 0x04
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#define RTL837x_TBL_DATA_0 0x5cb0
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#define RTL837x_L2_LIST_DATA_A 0x5ccc
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#define RTL837x_L2_LIST_DATA_B 0x5cd0
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#define RTL837x_L2_LIST_DATA_C 0x5cd4
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#define RTL837x_TBL_DATA_IN_A 0x5cb8
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#define RTL837x_PVID_BASE_REG 0x4e1c
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void vlan_setup(void) __banked
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{
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print_string("\r\nvlan_setup called \r\n");
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// Initialize VLAN table with VLAN 1
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REG_SET(RTL837x_TBL_DATA_IN_A, 0x0007ffff);
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REG_SET(RTL837X_TBL_CTRL, 0x00010303);
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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} while (sfr_data[3] & 0x01);
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// Set PVID 1 for every port. TODO: Skip unused ports!
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for (uint8_t i = minPort; i <= maxPort + 1; i++) { // Do this also for the CPU port
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print_byte(i); write_char(':'); write_char(' ');
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uint16_t reg = RTL837x_PVID_BASE_REG + ((i >> 1) << 2);
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print_short(reg); write_char(' '); write_char('B'); write_char('>');
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print_sfr_data();
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reg_read_m(reg);
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if (i & 0x1) {
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REG_WRITE(reg, sfr_data[0], 0, sfr_data[2] & 0x0f | 0x10, sfr_data[3]);
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} else {
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REG_WRITE(reg, sfr_data[0], sfr_data[1], sfr_data[2] & 0xf0, 0x01);
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}
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write_char(' '); write_char('A'); write_char('>'); print_sfr_data();
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reg_bit_clear(0x6738, i << 1);
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reg_bit_clear(0x6738, i << 1 + 1);
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reg_bit_set(0x4e18, i);
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print_string("\r\n");
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}
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// Enable 4k VLAN
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REG_SET(0x4e14, 4);
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REG_SET(0x4e30, 0);
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REG_SET(0x4e34, 0);
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// Enable VLAN 1
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REG_SET(RTL837x_TBL_DATA_IN_A, 0x0207ffff);
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REG_SET(RTL837X_TBL_CTRL, 0x00010303);
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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} while (sfr_data[3] & 0x01);
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print_string("\r\nvlan_setup done \r\n");
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}
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/*
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* Forget all dynamic L2 learned entries
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*/
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uint8_t port_l2_forget(void) __banked
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{
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// r53dc:00000000 R53dc-00000000 r53d4:000001ff r53d4:000001ff R53d4-000101ff r53d4:000001ff
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reg_read_m(0x53dc);
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if (sfr_data[0] || sfr_data[1] ||sfr_data[2] ||sfr_data[3]) {
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print_string("List busy\r\n");
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return -1;
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}
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REG_WRITE(0x53dc, sfr_data[0], sfr_data[1], sfr_data[2], sfr_data[3]);
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reg_read_m(0x53d4);
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REG_WRITE(0x53d4, 0x00, 0x01, sfr_data[2], sfr_data[3]);
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do {
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reg_read_m(0x53d4);
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} while (sfr_data[1] & 0x1);
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return 0;
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}
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void port_l2_learned(void) __banked
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{
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// Whait for any table action to be finished
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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} while (sfr_data[3] & 0x01);
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print_string("\r\n\tMAC\t\tVLAN\ttype\tport\r\n");
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uint16_t entry = 0x0000;
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uint16_t first_entry = 0xffff; // Table does not have that many entries
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while (1) {
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uint8_t port = 0;
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reg_read_m(RTL837x_TBL_DATA_0);
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REG_WRITE(RTL837x_TBL_DATA_0, sfr_data[0], sfr_data[1],sfr_data[2] | 0xc0, sfr_data[3]);
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REG_WRITE(RTL837X_TBL_CTRL, entry >> 8, entry, TBL_L2_UNICAST, 0x1);
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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} while (sfr_data[3] & 0x1);
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// MAC
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reg_read_m(RTL837x_L2_LIST_DATA_B);
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print_byte(sfr_data[2]); write_char(':');
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print_byte(sfr_data[3]); write_char(':');
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port = (sfr_data[0] >> 6) & 0x3;
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reg_read_m(RTL837x_L2_LIST_DATA_A);
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print_byte(sfr_data[0]); write_char(':');
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print_byte(sfr_data[1]); write_char(':');
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print_byte(sfr_data[2]); write_char(':');
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print_byte(sfr_data[3]); write_char('\t');
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// VLAN
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reg_read_m(RTL837x_L2_LIST_DATA_B);
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print_short( ((uint16_t) (sfr_data[0] & 0x0f)) | sfr_data[1]); // VLAN
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// type
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reg_read_m(RTL837x_L2_LIST_DATA_C);
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if (sfr_data[2] & 0x1)
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print_string("\tstatic\t");
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else
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print_string("\tlearned\t");
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port |= (sfr_data[3] & 0x3) << 2;
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if (port < 9)
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write_char('1' + port);
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else
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print_string("10");
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reg_read_m(RTL837x_TBL_DATA_0);
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entry = (((uint16_t)sfr_data[2] & 0x0f) << 8) | sfr_data[3] + 1;
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if (first_entry == 0xffff) {
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first_entry = entry;
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} else {
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if (first_entry == entry)
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break;
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}
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print_string("\r\n");
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}
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print_string("\r\nport_l2_learned done \r\n");
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}
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void port_stats_print(void) __banked
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{
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print_string("\r\n Port\tState\tLink\tTxGood\t\tTxBad\t\tRxGood\t\tRxBad\r\n");
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for (uint8_t i = minPort; i <= maxPort; i++) {
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write_char('1' + i); write_char('\t');
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phy_read(i, 0x1f, 0xa610); // p001f.a610:2058
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if (i <= maxPort - nSFPPorts) {
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if (SFR_DATA_8 == 0x20)
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print_string("On\t");
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else
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print_string("Off\t");
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reg_read_m(RTL837X_REG_LINKS);
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uint8_t b = sfr_data[3 - (i >> 1)];
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b = (i & 1) ? b >> 4 : b & 0xf;
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switch (b) {
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case 0:
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print_string("Down\t");
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break;
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case 1:
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print_string("100M\t");
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break;
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case 2:
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print_string("1000M\t");
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break;
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case 5:
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print_string("2.5G\t");
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break;
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default:
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print_string("Up\t");
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break;
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}
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} else { // An SFP Module TODO: This is for 1 module devices
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reg_read_m(RTL837X_REG_GPIO_B);
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if (!(sfr_data[0] & 0x40)) {
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print_string("SFP OK\t");
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} else {
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print_string("NO SFP\t");
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}
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reg_read_m(RTL837X_REG_GPIO_C);
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if (sfr_data[3] & 0x20) {
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print_string("Down\t");
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} else {
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uint8_t rate = sfp_read_reg(12);
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if (rate == 0xd)
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print_string("1000BX\t");
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else if (rate == 0x1f)
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print_string("2500G\t");
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else if (rate > 0x65 && rate < 0x70)
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print_string("10G\t");
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else
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print_string("Up\t");
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}
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}
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REG_WRITE(RTL837X_STAT_GET, 0x00, 0x00, 0x05, 0xe0 | (i << 1) | 1);
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do {
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reg_read_m(RTL837X_STAT_GET);
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} while (sfr_data[3] & 0x1);
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// FIXME: Ignore HIGHER part of 64 bit value for now
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print_reg(RTL837X_STAT_V_LOW); write_char('\t');
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REG_WRITE(RTL837X_STAT_GET, 0x00, 0x00, 0x06, (i << 1) | 1);
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do {
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reg_read_m(RTL837X_STAT_GET);
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} while (sfr_data[3] & 0x1);
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print_reg(RTL837X_STAT_V_LOW); write_char('\t');
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REG_WRITE(RTL837X_STAT_GET, 0x00, 0x00, 0x05, 0xc0 | (i << 1) | 1);
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do {
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reg_read_m(RTL837X_STAT_GET);
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} while (sfr_data[3] & 0x1);
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print_reg(RTL837X_STAT_V_LOW); write_char('\t');
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REG_WRITE(RTL837X_STAT_GET, 0x00, 0x00, 0x06, (i << 1) | 1);
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do {
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reg_read_m(RTL837X_STAT_GET);
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} while (sfr_data[3] & 0x1);
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print_reg(RTL837X_STAT_V_LOW); write_char('\t');
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print_string("\r\n");
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}
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}
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