mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-10-29 17:54:14 +08:00
Rob Emery
9b2bd7f1b8
timing with ticks Fixing up the log_to_phys_port assignment 2000 is about every 10 seconds, so scaling up to once every 30ish Removing the attempt to block lldp frames, This does not work however the hard work has been done for us in the #514 so we can borrow that work later on
127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/*
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* env_tables.c - what rtl837x_port.c and httpd/page_impl.c link against
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* besides the register mock: the console, the buffers page_impl writes into,
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* the machine description and leaf calls into subsystems not under test.
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* Buffers keep their firmware sizes so AddressSanitizer sees the same bounds
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* the 8051 has.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include "rtl837x_common.h"
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#include "rtl837x_port.h"
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#include "machine.h"
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#include "uip.h"
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#include "rtl837x_flash.h"
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#include "syslog.h"
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#include "rtl837x_phy.h"
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#include "support.h"
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/* ---- console: everything lands in out_buf (support.c) ---- */
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void print_byte(uint8_t v)
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{
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static const char h[] = "0123456789abcdef";
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write_char(h[(v >> 4) & 0xf]);
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write_char(h[v & 0xf]);
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}
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void print_short(uint16_t v) { print_byte(v >> 8); print_byte(v); }
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void print_long(uint32_t v) { print_short(v >> 16); print_short(v); }
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void print_reg(uint16_t v) { print_short(v); }
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void itoa_short(uint16_t v)
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{
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char b[6]; int n = 0;
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do { b[n++] = '0' + v % 10; v /= 10; } while (v);
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while (n) write_char(b[--n]);
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}
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void dbg_string(char *p) { (void)p; }
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void dbg_short(uint16_t v) { (void)v; }
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void dbg_char(char c) { (void)c; }
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void dbg_byte(uint8_t v) { (void)v; }
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/* ---- copied verbatim from rtlplayground.c ---- */
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uint16_t strtox(uint8_t *dst, const char *s)
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{
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uint8_t *b = dst;
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while (*s)
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*dst++ = *s++;
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*dst = 0;
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return dst - b;
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}
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const uint16_t bit_mask[16] = {
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0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
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0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
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};
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const uint8_t hex_chars[] = "0123456789abcdef";
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uint8_t *hex = (uint8_t *)hex_chars;
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/* ---- a 9-port RTL8373 whose logical ports map to themselves ---- */
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const struct machine machine = {
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.machine_name = "HOSTTEST",
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.min_port = 0,
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.max_port = 8,
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.n_sfp = 0,
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.log_to_phys_port = { 1, 2, 3, 4, 5, 6, 7, 8, 9 },
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.phys_to_log_port = { 0, 1, 2, 3, 4, 5, 6, 7, 8 },
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};
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struct machine_runtime machine_detected = { .isRTL8373 = 1 };
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/* ---- firmware state the modules read or write ---- */
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uint8_t outbuf[TCP_OUTBUF_SIZE];
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uint16_t slen;
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uint16_t management_vlan = 1;
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uint16_t cont_len;
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uint32_t cont_addr;
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uint8_t vlan_names[VLAN_NAMES_SIZE];
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uint16_t vlan_ptr;
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uint8_t sfp_pins_last = 0xff;
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uint8_t sfp_options[2];
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char sfp_module_vendor[2][17];
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char sfp_module_model[2][17];
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char sfp_module_serial[2][17];
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char hostname[24] = "hosttest";
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char port_names[9][PORT_NAME_SIZE];
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struct flash_region_t flash_region;
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struct syslog_state syslog_state;
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bool stp_enabled;
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bool lldp_enabled;
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uint16_t lldp_logical_port_status;
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uip_ipaddr_t uip_hostaddr, uip_draddr, uip_netmask;
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struct uip_eth_addr uip_ethaddr = { .addr = { 0x02, 0x11, 0x22, 0x33, 0x44, 0x55 } };
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/* ---- leaf calls into subsystems not under test ---- */
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void flash_read_bulk(uint8_t *dst) { (void)dst; }
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const char *get_flash_size_str(void) { return "2M"; }
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uint8_t sfp_read_reg(uint8_t slot, uint8_t reg) { (void)slot; (void)reg; return 0; }
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bool gpio_pin_test(uint8_t pin) { (void)pin; return false; }
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void phy_read(uint8_t phy_id, uint8_t dev_id, uint16_t reg) { (void)phy_id; (void)dev_id; (void)reg; }
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void phy_write(uint8_t phy_id, uint8_t dev_id, uint16_t reg, uint16_t val) { (void)phy_id; (void)dev_id; (void)reg; (void)val; }
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void phy_reset(uint8_t port) { (void)port; }
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uint8_t stp_port_role(uint8_t port) { (void)port; return 0; }
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uint8_t stp_port_state(uint8_t port) { (void)port; return 3; }
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/* ---- STP state send_stp() prints; the tree is not under test here ---- */
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#include "rtl837x_stp.h"
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struct bridge root_bridge;
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struct bridge stp_dbridge[STP_ENTITIES];
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uint16_t stp_bpdu_age[STP_ENTITIES];
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uint16_t stp_dpid[STP_ENTITIES];
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uint16_t stp_lag_mask[STP_LAG_COUNT];
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uint16_t stp_tc_count;
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uint32_t root_bridge_cost;
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uint32_t stp_dcost[STP_ENTITIES];
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uint32_t stp_pcost[STP_ENTITIES];
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uint8_t stp_ent_of[10] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
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uint8_t stp_fwddelay_s = 15, stp_hello_s = 2, stp_maxage_s = 20;
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uint8_t stp_pflags[STP_ENTITIES];
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uint8_t stp_pp2p[STP_ENTITIES];
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uint8_t stp_pprio[STP_ENTITIES];
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uint8_t stp_prio = 0x80, stp_root_port = 0xff, stp_rstp = 1, stp_txhold = 6;
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/* ---- SFP: no module present, reads fail ---- */
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uint8_t sfp_buf[16];
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bool sfp_read_block(uint8_t slot, uint8_t reg, uint8_t len) { (void)slot; (void)reg; (void)len; return false; }
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void print_phys_port(uint8_t port) { itoa_short(machine.log_to_phys_port[port]); }
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