mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
René van Dorst
745c170f0a
In commit 884bc18, `Fast Read 0x0b` was exchanged for `Read 0x03` command.
This was done because I did not see the difference between the commands
and the extra dummycycles looks like wasted time. But I overlooked that
many flash devices, the `Read 0x03` command can't run at the maximum
SPI-clock speed, but only half or less of the maximum SPI-clock speed.
This can cause in-transit data corruption while reading the device.
So change it back to `Fast Read 0x0b` command, so the SPI device is used
within the device specification.
374 lines
8.3 KiB
C
374 lines
8.3 KiB
C
/*
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* This is driver implementation for the RTL837x flash controller
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* This code is in the Public Domain
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*/
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#include <stdint.h>
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#include "rtl837x_common.h"
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#include "rtl837x_sfr.h"
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__xdata uint8_t dio_enabled;
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__xdata uint8_t markbuf[16];
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extern __xdata uint16_t mpos;
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__xdata struct flash_region_t flash_region;
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// For the flash commands, see e.g. Windbond W25Q32JV datasheet
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#define CMD_WRITE_STATUS 0x01
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#define CMD_PAGE_PROGRAM 0x02
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// Don't use command `READ 0x03`, because on many device this command can't run at maximum SPI-clock speed.
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// Use `Fast READ 0x0b` instead!
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//#define CMD_READ 0x03
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#define CMD_WRITE_ENABLE 0x06
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#define CMD_FREAD 0x0b
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#define CMD_SECTOR_ERASE 0x20
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#define CMD_READ_SECURITY_REGS 0x48
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#define CMD_READ_UNIQUE_ID 0x4b
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#define CMD_READ_JEDEC_ID 0x9f
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#define CMD_FREAD_DIO 0xbb
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/*
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* Configure Memory Managed IO
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*/
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void flash_configure_mmio(void)
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{
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// Set configuration for MMIO access by controller
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if (dio_enabled) {
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SFR_FLASH_MODEB = 0x18;
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SFR_FLASH_CMD_R = CMD_FREAD_DIO; // By default we read with Dual speed
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SFR_FLASH_DUMMYCYCLES = 4;
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return;
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}
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_FREAD; // Default is Single IO
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SFR_FLASH_DUMMYCYCLES = 8;
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}
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/*
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* Initializes the flash controller for programmed control
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* The configuration options are not really understood, the SPI speed
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* seems to be directly linked to the CPU frequency
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* This configures fast single IO at 20.8 MHz when the CPU clock is at 20.8MHz
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* and 62.5MHz when the CPU clock is configured at 125MHz
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*/
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void flash_init(uint8_t enable_dio)
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{
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if (enable_dio) {
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SFR_FLASH_CONFIG = 9; // There may be a chip-select in here
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SFR_FLASH_CONF_RCMD = CMD_FREAD_DIO;
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SFR_FLASH_CONF_DIV = 4;
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} else {
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// Configure fast read via divider = 8 and read-cmd being CMD_FREAD (for mmio)
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SFR_FLASH_CONFIG = 9;
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SFR_FLASH_CONF_RCMD = CMD_FREAD;
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SFR_FLASH_CONF_DIV = 8;
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}
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// Test Controller Busy
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while(SFR_FLASH_EXEC_BUSY);
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// Write 0 to status register
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SFR_FLASH_DUMMYCYCLES = 8;
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SFR_FLASH_MODEB = 0;
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SFR_FLASH_TCONF = 0x19;
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SFR_FLASH_CMD = CMD_WRITE_STATUS;
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SFR_FLASH_DATA0 = 0;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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dio_enabled = enable_dio;
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flash_configure_mmio();
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}
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uint8_t flash_read_status(void)
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{
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// Test Controller Busy (we might call this directly after executing a command)
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while(SFR_FLASH_EXEC_BUSY);
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// setup status read command
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SFR_FLASH_TCONF = 0x11;
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SFR_FLASH_CMD_R = 5;
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// execute and wait for controller done
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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return SFR_FLASH_DATA0;
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}
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void flash_read_uid(void)
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{
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while (flash_read_status() & 0x1);
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// Set slow read mode for UID
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_READ_UNIQUE_ID;
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SFR_FLASH_DUMMYCYCLES = 8;
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// Transfer 4 bytes (command + 3 dummy bytes)
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SFR_FLASH_TCONF = 4;
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SFR_FLASH_ADDR16 = 0;
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SFR_FLASH_ADDR8 = 0;
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SFR_FLASH_ADDR0 = 0;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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print_byte(SFR_FLASH_DATA0);
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print_byte(SFR_FLASH_DATA8);
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print_byte(SFR_FLASH_DATA16);
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print_byte(SFR_FLASH_DATA24);
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SFR_FLASH_EXEC_GO = 1;
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SFR_FLASH_DUMMYCYCLES = 24;
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while(SFR_FLASH_EXEC_BUSY);
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print_byte(SFR_FLASH_DATA0);
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print_byte(SFR_FLASH_DATA8);
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print_byte(SFR_FLASH_DATA16);
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print_byte(SFR_FLASH_DATA24);
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flash_configure_mmio();
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}
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void flash_read_jedecid(void)
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{
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while (flash_read_status() & 0x1);
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// Set read mode for JEDEC ID
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_READ_JEDEC_ID;
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SFR_FLASH_DUMMYCYCLES = 0;
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// Transfer 3 bytes back
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SFR_FLASH_TCONF = 0x13;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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print_byte(SFR_FLASH_DATA0);
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print_byte(SFR_FLASH_DATA8);
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print_byte(SFR_FLASH_DATA16);
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print_byte(SFR_FLASH_DATA24);
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// Reset slow read mode
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_FREAD;
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SFR_FLASH_DUMMYCYCLES = 8;
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}
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void flash_write_enable(void)
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{
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short status;
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// Wait until busy bit clear
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do {
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status = flash_read_status();
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} while (status & 0x1);
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SFR_FLASH_TCONF = 0x18;
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SFR_FLASH_CMD = CMD_WRITE_ENABLE;
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/* The following makes sure that the PAGE_PROGRAM command,
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* where the data to be written follows the command word directly
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* works properly
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*/
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SFR_FLASH_DUMMYCYCLES = 0;
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SFR_FLASH_MODEB = 0;
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SFR_FLASH_EXEC_GO = 1;
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// Wait for write status enabled
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do {
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status = flash_read_status();
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} while (!(status & 0x2));
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}
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void flash_dump(uint8_t len)
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{
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short status;
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do {
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status = flash_read_status();
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print_short(status);
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} while (status & 0x1);
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// Set fast read mode
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if (dio_enabled) {
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SFR_FLASH_MODEB = 0x18;
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SFR_FLASH_CMD_R = CMD_FREAD_DIO;
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SFR_FLASH_DUMMYCYCLES = 4;
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} else {
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_FREAD; // Fast read
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SFR_FLASH_DUMMYCYCLES = 8; // Add 8 dummy clocks after read?
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}
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// Read 4 bytes
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SFR_FLASH_TCONF = 4;
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while (len) {
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SFR_FLASH_ADDR16 = flash_region.addr >> 16;
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SFR_FLASH_ADDR8 = flash_region.addr >> 8;
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SFR_FLASH_ADDR0 = flash_region.addr;
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flash_region.addr += 4;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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print_short(SFR_FLASH_DATA0);
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if (len == 1)
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return;
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print_short(SFR_FLASH_DATA8);
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if (len == 2)
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return;
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print_short(SFR_FLASH_DATA16);
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if (len == 3)
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return;
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print_short(SFR_FLASH_DATA24);
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len -= 4;
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}
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}
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/*
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* Reads bulk data of length len from the flash memory starging at address src
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* and writes the data into a buffer pointed to by dst in XMEM
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*/
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void flash_read_bulk(__xdata uint8_t *dst)
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{
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short status;
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do {
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status = flash_read_status();
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} while (status & 0x1);
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// Set fast read mode
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if (dio_enabled) {
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SFR_FLASH_MODEB = 0x18;
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SFR_FLASH_CMD_R = CMD_FREAD_DIO;
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SFR_FLASH_DUMMYCYCLES = 4;
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} else {
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_FREAD; // Fast read
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SFR_FLASH_DUMMYCYCLES = 8; // Add 8 dummy clocks
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}
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// Read 4 bytes
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while (1) {
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SFR_FLASH_ADDR16 = flash_region.addr >> 16;
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SFR_FLASH_ADDR8 = flash_region.addr >> 8;
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SFR_FLASH_ADDR0 = flash_region.addr;
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flash_region.addr += 4;
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SFR_FLASH_TCONF = 4;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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*dst++ = SFR_FLASH_DATA0;
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if (flash_region.len == 1)
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break;
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*dst++ = SFR_FLASH_DATA8;
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if (flash_region.len == 2)
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break;
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*dst++ = SFR_FLASH_DATA16;
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if (flash_region.len == 3)
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break;
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*dst++ = SFR_FLASH_DATA24;
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if (flash_region.len == 4)
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break;
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flash_region.len -= 4;
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}
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}
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void flash_read_security(void)
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{
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while (flash_read_status() & 0x1);
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// Set slow read mode
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = CMD_READ_SECURITY_REGS; // read security register
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SFR_FLASH_DUMMYCYCLES = 8; // Add 8 dummy clocks as for fast read
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// Transfer 4 bytes (command + 3byte address)
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SFR_FLASH_TCONF = 4;
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do {
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SFR_FLASH_ADDR16 = flash_region.addr >> 16;
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SFR_FLASH_ADDR8 = flash_region.addr >> 8;
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SFR_FLASH_ADDR0 = flash_region.addr;
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flash_region.addr += 4;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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print_byte(SFR_FLASH_DATA0);
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if (flash_region.len == 1)
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break;
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print_byte(SFR_FLASH_DATA8);
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if (flash_region.len == 2)
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break;
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print_byte(SFR_FLASH_DATA16);
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if (flash_region.len == 3)
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break;
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print_byte(SFR_FLASH_DATA24);
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flash_region.len -= 4;
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} while(flash_region.len);
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}
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void flash_sector_erase(void)
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{
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flash_write_enable();
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SFR_FLASH_TCONF = 8;
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SFR_FLASH_CMD = CMD_SECTOR_ERASE;
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SFR_FLASH_ADDR16 = flash_region.addr >> 16;
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SFR_FLASH_ADDR8 = flash_region.addr >> 8;
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SFR_FLASH_ADDR0 = flash_region.addr;
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SFR_FLASH_EXEC_GO = 1;
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while (flash_read_status() & 0x1);
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flash_configure_mmio();
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}
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void flash_write_bytes(__xdata uint8_t *ptr)
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{
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write_char('>'); print_long(flash_region.addr); write_char(':'); print_short(flash_region.len); write_char('-'); print_byte(*ptr); write_char('\n');
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while(1) {
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flash_write_enable();
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SFR_FLASH_CMD = CMD_PAGE_PROGRAM;
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SFR_FLASH_TCONF = 0x40 | 8 | 4; // Bytes written is 4, 8 enables write, 0x40 is unknown
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// Last transfer?
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if (flash_region.len < 5) {
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SFR_FLASH_TCONF = 8 | flash_region.len;
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}
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SFR_FLASH_ADDR16 = flash_region.addr >> 16;
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SFR_FLASH_ADDR8 = flash_region.addr >> 8;
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SFR_FLASH_ADDR0 = flash_region.addr;
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SFR_FLASH_DATA0 = *ptr++;
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SFR_FLASH_DATA8 = *ptr++;
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SFR_FLASH_DATA16 = *ptr++;
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SFR_FLASH_DATA24 = *ptr++;
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// Execute transfer, we wait for completion at top of loop
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SFR_FLASH_EXEC_GO = 1;
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if (flash_region.len < 5)
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break;
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flash_region.len -= 4;
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flash_region.addr += 4;
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};
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while (flash_read_status() & 0x1);
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flash_configure_mmio();
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}
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