mirror of
https://github.com/logicog/RTLPlayground.git
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Erdnusschokolade
3a93ce1786
Adds CLI reference for the previously undocumented vlan <id> mgmt command, including the disable case (vlan 0 mgmt), default state, and a lockout warning. Fixes #235
102 lines
3.8 KiB
Markdown
102 lines
3.8 KiB
Markdown
# VLAN
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The RTL827x provides support for up to 4096 802.1Q VLANs, each port can be
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assigend a PVID.
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## VLAN control
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VLANs are controlled by the VLAN table. Configuration of entries is done as
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for the L2 entries, apart from that the ASIC does not add entries by itself.
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Adding a VLAN entry is done by setting:
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```
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RTL837x_TBL_DATA_IN_A = 02 0v vv vv
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```
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where 0x02 designates a valid entry and vvvvv is a 20bit field made of lower 10bits designating whether a
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port is a member of a VLAN. The higher 10 bits are '0' for tagged ports
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and '1' for untagged ports (the bit-logic definition is `v = (~members) ^ tagged ^
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members`). Ports are numbered 0-9, 9 being the CPU-port. Note that for
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the RTL8372 devices, the ports are not in their physical order.
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Once RTL837x_TBL_DATA_IN_A is set, the entry is added to the table by:
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```
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RTL837X_TBL_CTRL = 0V VV TT CC
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CC: TBL_WRITE | TBL_EXECUTE
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VVV: VLAN-Id
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TT: 0x02 (TBL_VLAN)
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CC: 0x03 (TBL_WRITE | TBL_EXECUTE)
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```
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The ASIC will clear bit 0 once the entry has been added.
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An entry is deleted by adding an invalid entry (00 instead of 0x02 in
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RTL837x_TBL_DATA_IN_A).
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A port is assigned a PVID by setting the PVID-bits of the corresponding
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register of the port. 2 ports share a register. An odd port uses bits [23:12],
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an even port uses bits [11:0]. The base register is
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RTL837x_PVID_BASE_REG (0x4e1c) and the registers go to 0x4e2c so that also
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the CPU-Port may have a PVID.
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Register RTL837x_REG_INGRESS (0x4e10) allows to define the ingress rules of
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a port. 2 bits define a rule and bits 0-19 are being used. A value of 00
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defines no filtering, 01 (0x01) allows only tagged packets, while 10 (0x02)
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allows only untagged packets to enter a port.
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Register RTL837X_VLAN_PORT_IGR_FLTR (0x4e18) enables or disables ingres VLAN
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filtering, each bit corresponds to given port (port0 -> bit0, port9 -> bit9).
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When enabled, incomming package's vlan tag is checked against VLAN membership
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on given port. When package contains VLAN not in member list, package is dropped.
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The default PVID on all port is 1, ingress VLAN filtering is enabled and all types of
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frames are accepted on input on all ports.
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By default, the ports transmit Ethernet frames with Realtek's proprietary
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tag format. By setting bit 6 (0x40) of the respective port configuration
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registers 0x1238, 0x1338, ...
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## VLAN API
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The code currently provides the following functions:
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```
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void port_pvid_set(uint8_t port, __xdata uint16_t pvid) __banked;
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uint16_t port_pvid_get(uint8_t port) __banked;
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void vlan_create(void) __banked; // reads from global vlan_settings
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int8_t vlan_get(register uint16_t vlan) __banked; // returns data in sfr_data
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void vlan_delete(uint16_t vlan) __banked;
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```
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# VLAN configuration on the Serial Console
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For testing the following commands are provided on the serial console:
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```
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vlan <VLAN-ID> p[t/u]...
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create or set vlan with given ID and the list of ports as members, a t
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behind a port defines the port as a tagged member, the u is optional
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vlan <VLAN-ID> d
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deletes the VLAN
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vlan show
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Dumps the current ingress vlan settings.
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vlan <VLAN-ID> mgmt
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Restricts network access to the switch (web UI, syslog) to the given
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VLAN. Use `vlan 0 mgmt` to disable the filter. Default is `vlan 1 mgmt`.
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Warning: setting this to an unreachable VLAN locks out the web UI;
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recovery requires serial console.
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pvid <port> <VLAN-ID>
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assigns PVID to a port. ports are numbered as on the casing
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ingress [p]<t|u|a>...
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Allows ingress packages on port `p` only when `t`agged, `u`ntagged or `a`ny.
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Multiple ports can be given at once as in vlan. When `p` is missing, all ports
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are assigned the same mode. CPU port can not be changed.
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Use `vlan show` to see current configuration.
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Example:
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`ingress 1t 2a` -> Set port 1 as tagged input only, set port 2 accepting any frames.
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`ingress a` -> Set all ports to accept both tagged and untagged frames (default behaviour).
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```
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