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130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
#ifndef _RTL837X_REGS_H_
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#define _RTL837X_REGS_H_
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#define RTL837X_REG_HW_CONF 0x6040
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// Bits 4 & 5: CLOCK DIVIDER from 125MHz for Timer
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#define RTL837X_REG_LED_MODE 0x6520
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// Defines the LED Mode for steering the Port LEDS and the System LED
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// BIT 17 set: LED solid on
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// Bytes 0/1 hold the LED mode, e.g. serial, RTL8231?
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// Blink rate is defined by setAsicRegBits(0x6520,0xe00000,rate);
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#define RTL837X_REG_SMI_CTRL 0x6454
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#define RTL837X_REG_RESET 0x0024
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// Writing 0x01 into this register causes a reset of the entire SoC
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#define RTL837X_REG_SEC_COUNTER 0x06f4
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#define RTL837X_REG_SEC_COUNTER2 0x06f8
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// Used for counting seconds
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#define RTL837X_REG_SDS_MODES 0x7b20
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/*
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* 5 Bits each give the state of the 2 SerDes of the RTL8372
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* Values are:
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*/
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#define SDS_SGMII 0x02
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#define SDS_1000BX_FIBER 0x04
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#define SDS_QXGMII 0x0d
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#define SDS_HISGMII 0x12
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#define SDS_HSG 0x16
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#define SDS_10GR 0x1a
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#define SDS_OFF 0x1f
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#define RTL837X_REG_LINKS 0x63f0
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/* Each nibble encodes the link state of a port.
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Port 0 appears to be the CPU port
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The RTL8372 serves ports 4-7, port 3 is the RTL8221
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2: 1Gbit
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5: 2.5Gbit
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*/
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#define RTL837X_REG_GPIO_A 0x40
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// BIT 4 resets RTL8224 on 9000-9XH
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#define RTL837X_REG_GPIO_B 0x44
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// Bit 1e cleared: SFP Module inserted on 9000-6XH (MOD_DEF0 pin)
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#define RTL837X_REG_GPIO_C 0x48
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// BIT 5 set: SIGNAL LOS of SFP module on 9000-6XH (RX_LOS pin)
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#define RTL837X_REG_GPIO_CONF_A 0x50
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// Configures IO direction for bank a
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#define RTL837X_REG_GPIO_EXT 0x63e8
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/*
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* NIC Related registers
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*/
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#define RTL837X_REG_RX_AVAIL 0x7874
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#define RTL837X_REG_RX_RINGPTR 0x787c
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#define RTL837X_REG_RX_DONE 0x784c
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/*
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* Statistics related registers
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*/
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#define RTL837X_STAT_GET 0x0f60
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#define RTL837X_STAT_V_HIGH 0x0f64
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#define RTL837X_STAT_V_LOW 0x0f68
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/*
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* Table access registers of the RTL837x
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* See e.g. RTL8366/RTL8369 datasheet for explanation
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*/
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#define RTL837X_TBL_CTRL 0x5cac
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/* Bytes in control register: EE EE TT CC: EE: Entry, TT: Table type, CC: Command
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* CC: BIT 0: 01: Execute. Bit 1: 1: WRITE, 0: READ
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* TT: 04: L2-table, 03: VLAN-table
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*/
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// Table operation bit-smasks
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#define TBL_WRITE 0x02
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#define TBL_EXECUTE 0x01
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// Table types
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#define TBL_L2_UNICAST 0x04
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#define TBL_VLAN 0x03
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#define RTL837x_TBL_DATA_0 0x5cb0
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#define RTL837x_L2_DATA_OUT_A 0x5ccc
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#define RTL837x_L2_DATA_OUT_B 0x5cd0
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#define RTL837x_L2_DATA_OUT_C 0x5cd4
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#define RTL837x_TBL_DATA_IN_A 0x5cb8
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#define RTL837x_L2_TBL_CTRL 0x53d4
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#define RTL837x_PVID_BASE_REG 0x4e1c
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/*
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* Mirroring
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*/
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#define RTL837x_MIRROR_CONF 0x604c
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#define RTL837x_MIRROR_CTRL 0x6048
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#ifdef REGDBG
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#define REG_SET(r, v) SFR_DATA_24 = ((v) >> 24) & 0xff; \
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SFR_DATA_16 = ((v) >> 16) & 0xff; \
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SFR_DATA_8 = ((v) >> 8 & 0xff); \
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SFR_DATA_0 = (v) & 0xff; \
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reg_write(r); \
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write_char('R'); print_byte(r >> 8); print_byte(r); write_char('-'); \
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print_byte(((v) >> 24) & 0xff); print_byte((v) >> 16 & 0xff); print_byte((v) >> 8 & 0xff); print_byte( (v) & 0xff); write_char(' ');
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#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
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SFR_DATA_16 = (v16); \
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SFR_DATA_8 = (v8); \
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SFR_DATA_0 = (v0); \
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reg_write(r); \
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write_char('R'); print_byte(r>>8); print_byte(r); write_char('-'); print_byte(v24); print_byte(v16); print_byte(v8); print_byte(v0); write_char(' ');
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#else
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#define REG_SET(r, v) SFR_DATA_24 = ((v) >> 24) & 0xff; \
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SFR_DATA_16 = ((v) >> 16) & 0xff; \
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SFR_DATA_8 = ((v) >> 8 & 0xff); \
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SFR_DATA_0 = (v) & 0xff; \
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reg_write(r);
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#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
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SFR_DATA_16 = (v16); \
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SFR_DATA_8 = (v8); \
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SFR_DATA_0 = (v0); \
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reg_write(r);
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#endif
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#endif
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