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59 lines
2.9 KiB
Markdown
59 lines
2.9 KiB
Markdown
#RTL8272/3 features
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The following hardware features of the RTL8372/3 is supported:
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- Clock generation, including different divider settings
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- Interrupt control for timer, serial, external irqs 0, 1
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- Serial console via SFRs
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- Flash operations via SFRs
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- Bank switching via SFRs
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- Access to Switch registers via SFRs
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- LED setup
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- Reset
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- Some switch settings such as MAC configuration
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- GPIO to detect SFP module insert/removal/RX-LOS (depending on device/module support)
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- I2C to read SFP EEPROM on 1 and 2 SFP slot devices
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- NIC setup
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- L2 learning table access, L2 table flushing
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- VLAN setup/configuration
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- Port mirroring
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- Access to PHYs via MDIO (clause 45 via SFR):
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- Internal PHYs of RTL8372 and RTL8373
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- RTL8221 (1x2.5GBit port on devices with 5 ports)
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- RTL8224 (4x2.5GBit ports on devices with 8 ports)
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- SerDes settings of SoC via SFR:
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- Configure SFPs with 10Gbit/2.5Gbit/1Gbit (Ethernet and Fiber SFP(+) tested)
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- RTL8221, RTL8224
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- NIC TX and RX of packets via SFRs
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- send and receive Ethernet frames via SFRs and Switch registers
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- RTL-tags and VLAN ingress-tag decoding for CPU-port
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Ethernet frame RX IRQ via IRQ1 is conceptually understood, but not activated. RX is
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currently done via polling, which allows ping-times of <10ms.
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The RTL8372/3 have 256 bytes of internal RAM (INTMEM) accessible through MOV
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instructions, which are used for the stack and important globals. Some of
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these are bit-adressable, e.g. for storing global flags.
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Additionally, 64kB of extended RAM (XMEM) is built in, which is accessed
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through the MOVX instruction. It is used for global variables, for most
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of the function argument passing that is not done using the 8 registers
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R0-R7 or registers A/B, and for local variables (which requires extremely
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careful planning). The flash memory is transparently accessible for code
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being executed and can be used to store configuration. Access is done through
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the MOVC instruction, possibly setting the bank register before and
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resetting it to access the entire 4MB space. Code is prefetched from flash
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and cached in a small RAM automatically by the HW.
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The peripherial functions are accessed through 2 different mechanisms:
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- Special Function Registers (SFRs, 0x80-0xff) for banking, timers, UART, access to
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switch registers, MDIO, SPI (flash) and NIC transfers. Some SFRs are not
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used for HW purposes and can be used as RAM. Some SFRs are bit-adressable,
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allowing for very tight event wait loops (a single 2-byte instruction).
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- 0x10000 switch registers, which appear to be very similar to the registers
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of the RTL838x, for which source code and datasheets are available. This
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controls clock dividers, GPIO/LEDs and general switch functionality.
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The playground image shows access to the different types of memory using the
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SDCC compiler. Any support of Linux or e.g. Zephyr would require porting gcc.
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There are FreeRTOS ports to 8051 processors using sdcc, however.
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