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59 Commits 9 Branches 1 Tag
e486c0418680c4191186a7d2ee09b69cae6be95b
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11 Commits
Author SHA1 Message Date
logicog b59f51b3ca Cleanup of initialitation, make debug code conditional 2025-06-29 11:10:29 +02:00
logicog 5faf31cdb8 Moving PHY code to BANK1 2025-06-25 15:30:50 +02:00
logicog 73a0a7d137 Add banking support 2025-06-25 13:20:06 +02:00
logicog b8352f9430 Implement ARP broadcast and make ping work 2025-06-23 17:57:54 +02:00
logicog e4d477938d Detect RTL8373 and name registers for GPIO. Enable RTL8224 2025-06-16 06:55:47 +02:00
logicog c435feee45 Add REG_SET macro 2025-06-15 18:18:36 +02:00
logicog 9a69fac07a Adding support for 2.5Gbit Ethernet modules 2025-06-14 09:52:15 +02:00
logicog 7eb7057787 use uint types 2025-06-14 09:12:07 +02:00
logicog 0485c21da0 Add support for reading SFP EEProm data via I2C, support for 1G SFP modules 2025-06-13 20:36:49 +02:00
logicog 86aebcbf08 Add rtl837x_regs.h register header 2025-06-12 20:31:53 +02:00
logicog 2ae0b5caba Moving registers to dedicated header so they can be better documented 2025-06-10 17:56:42 +02:00