 logicog
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8b1b4aff68
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Fix parsing of mirror command, fix parsing of serial buffer beyond wrap arond, add bulk reading of flash and start of config file parser
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2025-07-28 23:04:08 +02:00 |
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logicog
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a5d156a645
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Fix dropping of RTL VLAN tag for 802.1Q Tag, add L2 configuration
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2025-07-25 22:51:18 +02:00 |
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logicog
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0b30019769
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Use names for I2C-controller registers
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2025-07-23 08:34:26 +02:00 |
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logicog
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96a108e891
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Use common SDS configuration code also for RTL8224
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2025-07-23 08:01:33 +02:00 |
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logicog
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bcc58d2965
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Make RTL8224 work
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2025-07-22 19:05:27 +02:00 |
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logicog
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8fee855da2
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Separate code for rtl8272 from rtl8373 for readability and stability against accidental changes
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2025-07-22 09:42:56 +02:00 |
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logicog
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ccd8bf1633
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Cleanup
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2025-07-17 23:29:20 +02:00 |
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logicog
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b0a41a5af6
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Add support for RTL8372-devices with 2 SFP+ ports
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2025-07-17 13:25:07 +02:00 |
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logicog
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d66931acdf
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Adding initial http daemon implementation
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2025-07-13 12:03:40 +02:00 |
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logicog
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b192a87cab
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Cleaning up printouts for debugging of uIP
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2025-07-11 16:36:16 +02:00 |
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logicog
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8b761cfcc8
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Add UIP stack. Still lots of debug output on packets...
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2025-07-11 14:54:57 +02:00 |
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 logicog
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e0924314b4
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Add memcpy function for __xdata
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2025-07-06 09:53:28 +02:00 |
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logicog
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65c2336313
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Use external command parser module. Add support for mirroring
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2025-07-05 09:24:16 +02:00 |
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logicog
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2d8c0efabd
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Add 802.1Q VLAN and PVID support. Support VLAN tag at CPU-port
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2025-07-04 09:17:10 +02:00 |
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logicog
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997d85ba02
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Add basic VLAN configuration
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2025-07-02 11:57:15 +02:00 |
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logicog
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6f90e1db53
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Add support for changing Ethernet speeds
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2025-06-29 20:06:53 +02:00 |
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logicog
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b59f51b3ca
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Cleanup of initialitation, make debug code conditional
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2025-06-29 11:10:29 +02:00 |
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logicog
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5faf31cdb8
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Moving PHY code to BANK1
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2025-06-25 15:30:50 +02:00 |
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logicog
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73a0a7d137
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Add banking support
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2025-06-25 13:20:06 +02:00 |
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logicog
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b8352f9430
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Implement ARP broadcast and make ping work
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2025-06-23 17:57:54 +02:00 |
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logicog
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2776df9ca8
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Make RX of packets work
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2025-06-21 16:18:19 +02:00 |
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logicog
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dd039494c2
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Add more RTL8224 config
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2025-06-21 05:58:55 +02:00 |
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logicog
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869db02865
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Emable RTL8224 PHY. Better implementation of sleep/delay timer
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2025-06-17 18:21:15 +02:00 |
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logicog
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e4d477938d
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Detect RTL8373 and name registers for GPIO. Enable RTL8224
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2025-06-16 06:55:47 +02:00 |
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logicog
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85cb2a52a5
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Cleanup
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2025-06-15 18:26:27 +02:00 |
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logicog
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b49f2aa16f
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Add initial support for RTL8373
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2025-06-15 18:24:23 +02:00 |
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logicog
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9a69fac07a
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Adding support for 2.5Gbit Ethernet modules
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2025-06-14 09:52:15 +02:00 |
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logicog
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37ca55392a
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Add support for 10G Fiber
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2025-06-14 09:12:24 +02:00 |
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logicog
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0485c21da0
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Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
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2025-06-13 20:36:49 +02:00 |
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logicog
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b41410ce6b
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Cleanup
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2025-06-12 20:33:35 +02:00 |
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logicog
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8c8b92ed65
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Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit
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2025-06-12 20:32:36 +02:00 |
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logicog
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8243a454de
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Adding support for link status display
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2025-06-10 17:57:28 +02:00 |
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logicog
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c54227f057
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Fix SFR_DATA access, make internal switch work
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2025-06-09 11:22:52 +02:00 |
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logicog
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c5d7628ea0
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Adding support for the ASIC second counter register and sleeping
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2025-06-06 20:49:15 +02:00 |
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logicog
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9f22c49af7
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Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud
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2025-06-05 20:15:42 +02:00 |
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logicog
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73a6f0f311
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Adding more flash functionality and image documentation
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2025-05-14 20:40:44 +02:00 |
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logicog
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7493089c39
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Adding DIO for flash access
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2025-05-11 20:29:31 +02:00 |
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logicog
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3a953bba47
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More commands, fixing strange sdcc behaviour for clock setting defines
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2025-05-11 18:28:08 +02:00 |
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logicog
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6d3214d13d
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More initial documentation
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2025-05-10 17:01:33 +02:00 |
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logicog
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c4835b7a6c
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Initial commit
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2025-05-10 15:52:02 +02:00 |
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