stp_loop_hold_peer() takes operEdge away from the port that sent the
BPDU we got back, though that port heard nothing itself. When the hold
ran out the port stayed non-edge until its next link change, and every
later state change on it counted as a topology change. Restore edge when
the hold ends with the port still silent and auto-edge on, before the
transition is reported, so the recovery itself is not a change. Hellos
go out on edge ports too, so a loop that persists is caught again.
The console column that shows seconds since the last BPDU is now called
age[s]; it never was a receive count.
stp_in() propagated the TC flag of any BPDU that did not arrive on an
alternate port, and acknowledged and propagated a TCN from any port, so a
port still in its listen period or held discarding in a dispute could flush
the addresses of every other port and move the topology change counter.
802.1D-2004 17.31 keeps the Topology Change machine in LEARNING until the
port forwards and drops rcvdTc and rcvdTcn there. Both paths now ask for
the forwarding state first; an alternate port is discarding, so the old
check is covered by the new one.
Scenario 53 plays a TC flag and a TCN into a port that is still discarding,
and then into the same port once it forwards. Scenario 51 used a TCN on a
port one tick short of its edge transition as the trigger for the clock it
tests; it now waits for the transition.
* stp: select the root port by cost and block redundant links
* stp: move the protocol to BANK4 and keep the command line in BANK2
* stp: implement the RSTP state machines of 802.1D-2004 clause 17
* stp: counters, more settings and a fuller Spanning Tree page
* stp: make a link aggregation group one port of the RSTP tree
* web: serve the Spanning Tree JSON from BANK4 as well
Kept in BANK1, the larger Spanning Tree page would leave under 1 kB
there for the rest of the web server and every page still to come, so
send_stp() and send_stp_counters() move to httpd/page_stp.c in BANK4
with the protocol, as banked calls, with their own copies of the few output
helpers and of the JSON header, so nothing in BANK4 calls into BANK1
directly or hands it a pointer into its code space. BANK4 takes the
free flash between BANK3 and the web files.
KP_9000_6XHML_X2: BANK1 44336, BANK2 36969, BANK3 11942, BANK4 20965
bytes of 49152.
SW1 on PCB-SWTG024AS-A-V2.0.1_19650 is wired to GPIO48. Measured on
HC-SWTG124AS: GPIO48 reads 1 idle and 0 while the button is held.
HC_SWTG124AS.c is a symlink to PCB_SWTG024AS_A_2_0_1.c.
Device page following doc/adding-a-device.md: label data, PCB versus label
naming, CPU identified with 'regget 4' (RTL8373, non-N), separate PHY and flash
identification, build target, PCB silkscreen, port mapping, board signals, front
panel and LED configuration, reset button, MAC location, what works and what is
unverified, plus photos. Row added to supported_devices.md.
html_min was phony, so every make deleted output/html_min and minified
all of html/ again, even with nothing changed. A stamp file now stands for
the minified copy and depends on the sources and on minify.py. A list of
the source names, rewritten only when it changes, is a dependency too, so
adding or removing a file in html/ still redoes the copy and a removed
file does not stay behind in the image. If output/html_min is missing,
the stamp is remade in the same run.
The note on version.h in webui-compression.md still said it was phony.
In HEALTH=1 builds health_phase(HEALTH_LLDP) used id 7 while ph_max[] and
ph_slow[] had HEALTH_PHASES = 6 entries. The LLDP checkpoint therefore
wrote one byte past ph_max (into the high byte of ph_slow[0]) and, when
the phase took two ticks or more, incremented two bytes past ph_slow
(dhcp_state.state and transaction_id on KP_9000_6XHML_X2).
Rename it HEALTH_PH_LLDP = 6, derive HEALTH_PHASES from it so the arrays
always cover the last phase, print an lldp line in "health" and document
it.
Fixes#658
Address review by documenting regget 4 and RTL8373 N/non-N ID values under Step 4 of adding-a-device.md, without referring to a particular board or set of units. Keep the verified Horaco CPU and flash capacity in its device table and retain the unverified-chip caveat.
Read register 0x0004 on all three tested HC-SWTGW218AS units. Each returned 0x83730000, identifying RTL8373 rather than RTL8373N. Firmware reports 2 MB flash on all three.
Fill in the verified device-table fields and document the non-N/N register distinction. Leave PHY and flash-chip models explicitly unverified.
The HC-SWTGW218AS is listed only with the SWTG018AS-A V2.0 board, but it
also ships with SWTG118AS-V2.1, the board of the XikeStor SKS3200-8E1X.
That version runs MACHINE=SWTGW218AS: three such switches were flashed
through the OEM web upgrade and work.
Note in the device page that the model name alone does not tell which
firmware to build.
Add the assembled top, front and bottom of the case next to the PCB photos, and
record what the nameplate says (manufacturer, the model description translated
from the Chinese label, 12 V DC 2 A and the serial number format) so a device
can be identified by its label. The top of the case carries no model name.
Also point out where the three console through-holes sit in the top side photo
and note the PWR and SFP1/SFP2 LEDs on the front panel; the case legend for the
copper LEDs reads 1000M/2500M.
The hongyavision HYWS-SGT0204S is sold as an unmanaged 4x2.5G + 2x10G SFP+
switch and carries the 2G5F4_10G2_V1.01 marking on the PCB. It is a sibling of
the KP-9000-6XH-X2 (2M-PCB43-V1.1), so machine/2G5F4_10G2_V1_01.c is that board
definition with these changes:
- The two SFP+ cages (physical ports 5 and 6) are wired the other way round:
physical 5 is on SDS1 with GPIO30/GPIO37, physical 6 on SDS0 with
GPIO50/GPIO10. Copper ports 1-4 match the KP-9000 layout.
- No reset button is fitted and the case has no opening for one, so reset_pin
is GPIO_NA. GPIO54, the reset pin on the KP-9000 layout, reads as permanently
pressed here.
- The board definition sets flash_sio, so the flash is read with single-IO: the
fitted 512 KB Bright Moon T25S40 cannot be read in DIO mode on this board, an
image that leaves DIO enabled does not come up at all, while the same image
with single-IO boots and runs normally (two units).
- The board is added to the machine_custom_init() group that sets
LED_GLB_IO_EN bit 6, otherwise the RTL837x "solid" conditions (LINK/speed)
never drive the LEDs and the 2.5G LED glows faintly at 100M/1000M.
flash_sio is a new field of struct machine that rtlplayground.c hands to
flash_init(); only this board sets it, every other machine keeps DIO. It costs
management-plane speed only, the ASIC keeps forwarding in hardware.
The stock firmware runs a factory test console on the serial header at 9600
baud, whose silkscreen labels are shifted by one pin.
Verified: warning-free build, `make machine_check` passes for every target, the
host tests pass, and a control build of this target without the LED hook differs
from the KP-9000-6XH_X2_V1_1 image in 44 bytes: all inside the machine
description (including flash_sio) and the image CRC16, nothing else in the
firmware moved. On the board the single-IO image boots and runs on two units;
port order, SFP cages and LED behaviour come from the machine definition
verified on this board earlier.
UART is broken out to the unpopulated switch header at the front of the
board.
This isn't quite the same as the V2.0 definition as the system led is
always on, not routed through the CPU.
Additionally, document that the newer revision of the same "YS25-0402"
is supported via the existing PCB-K0402WS-V3.0 target.
René van Dorst
Zoe O'Connell
feelfree69
João Silva
d00f
logicog
rwalli@gmx.at
HL Yi
gtytup
Luca S.
Andre Brait
avicarmeli
Kamikaze94
logicog
Matt Merhar
Robert Klauco