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640 Commits 9 Branches 1 Tag
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Author SHA1 Message Date
logicog 178e3d2550 More doc on TX 2025-06-23 19:43:33 +02:00
logicog 08d6c27605 More documentation 2025-06-23 19:41:26 +02:00
logicog b8352f9430 Implement ARP broadcast and make ping work 2025-06-23 17:57:54 +02:00
logicog 2776df9ca8 Make RX of packets work 2025-06-21 16:18:19 +02:00
logicog dd039494c2 Add more RTL8224 config 2025-06-21 05:58:55 +02:00
logicog 869db02865 Emable RTL8224 PHY. Better implementation of sleep/delay timer 2025-06-17 18:21:15 +02:00
logicog e4d477938d Detect RTL8373 and name registers for GPIO. Enable RTL8224 2025-06-16 06:55:47 +02:00
logicog 85cb2a52a5 Cleanup 2025-06-15 18:26:27 +02:00
logicog b49f2aa16f Add initial support for RTL8373 2025-06-15 18:24:23 +02:00
logicog 88067d3a3e Add command byte macros and NIC SFRs 2025-06-15 18:19:43 +02:00
logicog c435feee45 Add REG_SET macro 2025-06-15 18:18:36 +02:00
logicog 9a69fac07a Adding support for 2.5Gbit Ethernet modules 2025-06-14 09:52:15 +02:00
logicog 37ca55392a Add support for 10G Fiber 2025-06-14 09:12:24 +02:00
logicog 7eb7057787 use uint types 2025-06-14 09:12:07 +02:00
logicog d78e28cbdb New features: SFP EEProm reading and SFP configuration 2025-06-13 20:39:18 +02:00
logicog 0485c21da0 Add support for reading SFP EEProm data via I2C, support for 1G SFP modules 2025-06-13 20:36:49 +02:00
logicog c00c908579 Keep up with features: SerDes configuration for port 5 2025-06-12 20:36:59 +02:00
logicog b41410ce6b Cleanup 2025-06-12 20:33:35 +02:00
logicog 8c8b92ed65 Add SerDes configuration support for the RTL8221B ethernet port to support 2.5 and 1GBit 2025-06-12 20:32:36 +02:00
logicog 86aebcbf08 Add rtl837x_regs.h register header 2025-06-12 20:31:53 +02:00
logicog c7965d048e An injector of .hex files from as31 into .bin images 2025-06-11 06:44:35 +02:00
logicog 8302b0d0d2 Update on console 2025-06-10 18:14:37 +02:00
logicog fdec0ad80c Status update 2025-06-10 18:11:29 +02:00
logicog 8243a454de Adding support for link status display 2025-06-10 17:57:28 +02:00
logicog 2ae0b5caba Moving registers to dedicated header so they can be better documented 2025-06-10 17:56:42 +02:00
logicog c54227f057 Fix SFR_DATA access, make internal switch work 2025-06-09 11:22:52 +02:00
logicog c5d7628ea0 Adding support for the ASIC second counter register and sleeping 2025-06-06 20:49:15 +02:00
logicog a0a5328ecd Document default baud of 115200 2025-06-05 20:16:24 +02:00
logicog 9f22c49af7 Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud 2025-06-05 20:15:42 +02:00
logicog 98403e25d3 Add definitions for SFRs 0x93 and 0x94 2025-06-05 20:14:08 +02:00
logicog 7c2e1509a5 Cosmetics 2025-06-05 20:13:07 +02:00
logicog 73a6f0f311 Adding more flash functionality and image documentation 2025-05-14 20:40:44 +02:00
logicog 7493089c39 Adding DIO for flash access 2025-05-11 20:29:31 +02:00
logicog 3a953bba47 More commands, fixing strange sdcc behaviour for clock setting defines 2025-05-11 18:28:08 +02:00
logicog 138ed7dd25 More HW info 2025-05-11 06:36:11 +02:00
logicog 8fedd9c997 More on the image 2025-05-10 17:13:04 +02:00
logicog 4f654d5a0b Nicer README 2025-05-10 17:07:31 +02:00
logicog 6d3214d13d More initial documentation 2025-05-10 17:01:33 +02:00
logicog c4835b7a6c Initial commit 2025-05-10 15:52:02 +02:00
logicog d35eaa8a49 Initial commit 2025-05-10 15:45:00 +02:00