logicog
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ad53165351
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Introduce identified RX/TX control register names
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2025-08-19 09:34:14 +02:00 |
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logicog
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c01014f1d8
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Add more documentation on vlans and trunking
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2025-07-26 19:10:24 +02:00 |
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logicog
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fcd1f85eb6
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Add trunking support and initial L2 setup
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2025-07-25 22:50:27 +02:00 |
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logicog
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0b30019769
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Use names for I2C-controller registers
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2025-07-23 08:34:26 +02:00 |
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logicog
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066edd672e
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Add off-state for SDS
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2025-07-22 09:34:40 +02:00 |
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logicog
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b0a41a5af6
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Add support for RTL8372-devices with 2 SFP+ ports
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2025-07-17 13:25:07 +02:00 |
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logicog
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84b84f5c32
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Cleanup of L2 and mirroring features
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2025-07-14 07:59:31 +02:00 |
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logicog
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b59f51b3ca
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Cleanup of initialitation, make debug code conditional
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2025-06-29 11:10:29 +02:00 |
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logicog
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5faf31cdb8
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Moving PHY code to BANK1
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2025-06-25 15:30:50 +02:00 |
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logicog
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73a0a7d137
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Add banking support
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2025-06-25 13:20:06 +02:00 |
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logicog
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b8352f9430
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Implement ARP broadcast and make ping work
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2025-06-23 17:57:54 +02:00 |
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logicog
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e4d477938d
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Detect RTL8373 and name registers for GPIO. Enable RTL8224
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2025-06-16 06:55:47 +02:00 |
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logicog
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c435feee45
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Add REG_SET macro
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2025-06-15 18:18:36 +02:00 |
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logicog
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9a69fac07a
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Adding support for 2.5Gbit Ethernet modules
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2025-06-14 09:52:15 +02:00 |
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logicog
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7eb7057787
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use uint types
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2025-06-14 09:12:07 +02:00 |
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logicog
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0485c21da0
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Add support for reading SFP EEProm data via I2C, support for 1G SFP modules
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2025-06-13 20:36:49 +02:00 |
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logicog
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86aebcbf08
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Add rtl837x_regs.h register header
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2025-06-12 20:31:53 +02:00 |
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logicog
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2ae0b5caba
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Moving registers to dedicated header so they can be better documented
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2025-06-10 17:56:42 +02:00 |
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