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412098d0ed2a3e2819b21e633e92726ae68a723b
Commit Graph
48 Commits
Author SHA1 Message Date
d00f 412098d0ed phy: advertise half duplex only when half duplex was asked for 
The 100M branch of phy_set_speed() is missing an else. A port set to 100M
half writes 0x1481, falls into the next if, finds duplex is not 1 and takes
its else, and immediately overwrites the register with 0x1581. The port
ends up advertising 100BASE-TX half and full, which is what "both" is
supposed to mean.

The 10M branch directly above has the chain the 100M one meant to have, and
the values line up with it: bit 7 is 100BASE-TX half, bit 8 is full, so
0x1481, 0x1501 and 0x1581 are half, full and both, exactly as 0x1421,
0x1441 and 0x1461 are for 10M.

Forcing half duplex is something people do to match a link partner that
cannot negotiate, so quietly advertising full as well is the wrong way for
this to fail.

Not tried on hardware: every port on the switch here has a link up, and
setting the speed restarts negotiation.
 2026-09-08 23:49:11 +02:00
René van Dorst f187261085 Fix all compiler warnings. 
- Many times we need help the compiler to reason about variable type or
define.
 2026-08-30 21:41:30 +02:00
René van Dorst 95b3bde822 Rename print_port() to print_phys_port() 2026-08-25 07:55:17 +02:00
René van Dorst 3c183f73f8 Added print_port() helper to print physical port number. 2026-08-25 07:54:15 +02:00
logicog 63ab6500c0 Add 10G/5G speed configuration/display 2026-04-24 10:53:05 +02:00
logicog fd3a272255 Add RTL8261BE PHY configuration 
Add configuration of the RTL8261BE PHY on startup.
 2026-04-24 10:52:24 +02:00
feelfree69 41f0dad49d Add ability to assign a name to a port 2026-04-13 14:55:10 +02:00
logicog 47878ac580 Add more printout 2026-02-08 16:46:56 +01:00
logicog d83f91f9e8 Fix Auto-negotiation 
Commit 7f4c276 used the wrong MMD device
for use with the auto-negotiation page:
- phy_write(port, PHY_MMD_AN, 0x00, 0x3200);	// Restart AN
+ phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3200);	// Restart AN

Fix this.
 2026-02-08 16:46:56 +01:00
logicog 9d07416641 Convert phy_set_duplex phy_set_speed to use struct phy_settings 2026-02-08 16:46:56 +01:00
René van Dorst 1d94e99612 Demagic 0x7, 0x3e to PHY_MMD_AN, PHY_EEE_ADV2 2026-01-26 23:00:29 +01:00
René van Dorst a134335308 Demagic PHY_MMD31, 0xa432 to PHY_MMD31, PHY_MMD31_PHYCR2 2026-01-26 22:58:57 +01:00
René van Dorst 6495310ba9 Demagic PHY_MMD31, 0xa434 to PHY_MMD31, PHY_MMD31_PHYSR 2026-01-26 22:48:04 +01:00
René van Dorst 5962c3a8a6 Demagic PHY_MMD31, 0xa414 to PHY_MMD31, PHY_MMD31_GANLPAR 2026-01-26 22:45:44 +01:00
René van Dorst a6e452e638 Demagic PHY_MMD_AN, 33 to PHY_MMD_AN, PHY_ANEG_MGBASE_ADV 2026-01-26 22:42:54 +01:00
René van Dorst 7f4c276285 Demagic PHY_MMD_AN, 0x00 to PHY_MMD_AN, PHY_ANEG_CTRL 2026-01-26 22:41:49 +01:00
René van Dorst f9fdc6b81d Demagic PHY_MMD_AN, 0x13 to PHY_MMD_AN, PHY_ANEG_LP_ABILITY 2026-01-26 22:39:16 +01:00
René van Dorst d9185b3505 Demagic PHY_MMD31, 0xa400 to PHY_MMD31, PHY_MMD31_FEDCR 2026-01-26 22:37:16 +01:00
René van Dorst 3d7ef55ced Demagic PHY_MMD31, 0xa412 to PHY_MMD31, PHY_MMD31_GBCR 2026-01-26 22:35:03 +01:00
René van Dorst 44779404df Demagic PHY_MMD_AN, 0x20 to PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL 2026-01-26 22:31:44 +01:00
René van Dorst 1997d7379b Demagic PHY_MMD_AN, 0x10 to PHY_MMD_AN, PHY_ANEG_ADV 2026-01-26 22:28:33 +01:00
René van Dorst c11099b9ec Rename PHY_SDS_CTRL and RTL8224_DEV_ID to PHY_MMD30. 
So demagic the `phy_(, 0x1e, )` to `phy_(, PHY_MMD30, )`.
Use `rg -tc phy | rg -i 0x1e` to find to most locations.
 2026-01-25 23:44:03 +01:00
René van Dorst 13d0781455 Rename PHY_MMD_CTRL to PHY_MMD31. 
So demagic the `phy_(, 0x1f, )` to `phy_(, PHY_MMD31, )`.
 2026-01-25 23:38:04 +01:00
René van Dorst fc327810ed Add more comments about the SDS-settings for RTL8224. 
Remove the unused array `rtl8224_cb`.
Rename `rtl8224_ca` to `rtl8224_sds0_setttings`.
 2026-01-25 20:24:40 +01:00
René van Dorst b7b4594406 N-type SOC need to swap some Serdes lines to make it work. 
Without this fix N-type SOC devices like RTL8372N, RTL8383N and also the
4-port PHY RTL8224N, don't have a functional Serdes. Although the SOC
sees a link, there is no packet flow on both SFP-port nor RTL8224 ports.

Added helper functions to read/write to the RTL8224.
RTL8224 has the same register layout so we can use the same register
defines as for the main SOC.
 2026-01-25 17:22:51 +01:00
logicog 892920a627 Mover phy code to bank 2 as bank 1 already overflows 2026-01-17 17:54:31 +01:00
logicog 2a7bfdc119 Add duplex setting in PHY speed configuration 2025-12-23 13:04:34 +01:00
logicog eb0106d9f4 Correct bits in advertised PHY speeds 2025-12-22 23:28:50 +01:00
logicog 58c9af242d Cleanup code in rtl837x_phy.c 2025-12-17 06:44:11 +01:00
logicog 95fae8bad2 Display actual link speed 2025-12-15 06:54:41 +01:00
logicog b41452026f Make sure port is not called for an SFP module 2025-12-14 12:17:53 +01:00
logicog 2ed9974c04 Add more options to Link configuration and status display 2025-12-14 11:41:50 +01:00
logicog 28f832a24d Fix PHY issues 2025-12-13 22:22:40 +01:00
logicog 03fb3fe6b4 Reduce PHY reset time to 20ms 2025-10-21 17:47:38 +02:00
logicog 7546d0c685 Fix bug in usage of CONST segment in banked code. Use #pragma constseg 2025-10-14 18:41:52 +02:00
logicog 31c61faa60 Use PHY page definitions, add PHY reset routine 2025-10-11 11:32:23 +02:00
René van Dorst 001c52ef39 Use phy_modify(). 
This saves 210 bytes.
 2025-09-02 22:23:02 +02:00
René van Dorst 22dccbad8c Replace phy_write_mask(0x1 with phy_write(0x00. 
Also added define `RTL8224_PHY_ID` for RTL8224 phy_id.
So it is more clear that we want to talk to that phy.
Replaced in the function which contains `8224` in the name the
`phy_write(0x00, ...)` with `phy_write(RTL8224_PHY_ID, ...)`, same for the
`phy_read(0x00, ...)` with `phy_read(RTL8224_PHY_ID, ...)`.

Removed the extra `phy_read()` in `rtl8224_phy_enable()`.
 2025-09-01 12:26:27 +02:00
René van Dorst 689d208ff1 phy: fix whitespace and comments alinement 2025-09-01 09:59:06 +02:00
René van Dorst d865862625 phy: fix or/and-opperation conversion errors 2025-09-01 09:27:28 +02:00
René van Dorst 94cf079fcb PHY: also use SFR_DATA_U16. 
Again less error prone and easier to read.

Also see a lot of better optimalizations.
A snipped.

390c390
< ;pval          Allocated to registers r3 r4
---
> ;pval          Allocated to registers
838,852c838,844
< ;     rtl837x_phy.c:181: pval = SFR_DATA_8 & 0xbf;
<       mov     r7,_SFR_DATA_8
<       anl     ar7,#0xbf
< ;     rtl837x_phy.c:182: pval <<= 8;
<       mov     ar4,r7
<       mov     r7,#0x00
< ;     rtl837x_phy.c:183: pval |= SFR_DATA_0;
<       mov     r2,_SFR_DATA_0
<       mov     r3,#0x00
<       mov     a,r2
<       orl     a,r7
<       mov     _phy_write_PARM_4,a
<       mov     a,r3
<       orl     a,r4
<       mov     (_phy_write_PARM_4 + 1),a
---
> ;     rtl837x_phy.c:181: pval = SFR_DATA_U16 & 0xbfff;
>       mov     r4,((_SFR_DATA_U16 >> 0) & 0xFF)
>       mov     a,#0xbf
>       anl     a,((_SFR_DATA_U16 >> 8) & 0xFF)
>       mov     r7,a
>       mov     _phy_write_PARM_4,r4
>       mov     (_phy_write_PARM_4 + 1),r7
864c856
<       mov     _phy_write_PARM_3,r7
---
>       mov     _phy_write_PARM_3,#0x00
 2025-09-01 09:25:33 +02:00
René van Dorst 7ff028303d Add phy_write() with bit_mask lookup inside the function. 
Move the lookup saves a lot of instructions for every phy_write() call.

Assembly diff for one change.
< ;     rtl837x_phy.c:240: phy_write_mask(bit_mask[port], 0x07, 0x00, 0x3200);  // Enable AN
<       mov     dpl,r5
<       mov     dph,r6
---
> ;     rtl837x_phy.c:240: phy_write(port, 0x07, 0x00, 0x3200); // Enable AN
>       mov     _phy_write_PARM_2,#0x07
1345,1359c1019,1024
<       movc    a,@a+dptr
<       mov     r5,a
<       inc     dptr
<       clr     a
<       movc    a,@a+dptr
<       mov     r6,a
<       mov     _phy_write_mask_PARM_2,#0x07
<       clr     a
<       mov     _phy_write_mask_PARM_3,a
<       mov     (_phy_write_mask_PARM_3 + 1),a
<       mov     _phy_write_mask_PARM_4,a
<       mov     (_phy_write_mask_PARM_4 + 1),#0x32
<       mov     dpl, r5
<       mov     dph, r6
<       lcall   _phy_write_mask
---
>       mov     _phy_write_PARM_3,a
>       mov     (_phy_write_PARM_3 + 1),a
>       mov     _phy_write_PARM_4,a
>       mov     (_phy_write_PARM_4 + 1),#0x32
>       mov     dpl, r7
>       lcall   _phy_write

Replace all phy_write_mask(bit_mask[<var>], ...) to phy phy_write(<var>, ...).
 2025-09-01 00:12:12 +02:00
René van Dorst d6ea9be4c0 rename phy_write() to phy_write_mask(). 
It seems that bit_mask[phy] lookup is expensive and it used in many places.
But most of the time we only addressing a single phy.
 2025-09-01 00:07:27 +02:00
logicog c9a82b550a Fix for issue #3 reported by airjinkela: wrong register ID exceeding 16bit 2025-08-06 08:22:19 +02:00
logicog 995deb313c Cleanup of unused code 2025-07-22 09:41:44 +02:00
logicog 6f90e1db53 Add support for changing Ethernet speeds 2025-06-29 20:06:53 +02:00
logicog b59f51b3ca Cleanup of initialitation, make debug code conditional 2025-06-29 11:10:29 +02:00
logicog 5faf31cdb8 Moving PHY code to BANK1 2025-06-25 15:30:50 +02:00