mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Enable EEE on boot, do not reset interfaces immediately to save boot time.
This commit is contained in:
+9
-6
@@ -429,29 +429,32 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
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return;
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// Enable all speeds up to the specified speed
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if (speed == EEE_100) {
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if ((speed & (EEE_100 | EEE_1000 | EEE_2G5)) == EEE_100) {
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REG_SET(RTL8373_EEE_CTRL_BASE + (port << 2), EEE_100);
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// Enable EEE advertisement for 100BASE-T via EEE Advertisement Reg
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phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_100M);
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phy_reset(port);
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if (!(speed & EEE_NORESET))
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phy_reset(port);
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return;
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}
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if (speed == EEE_1000) {
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if ((speed & (EEE_100 | EEE_1000 | EEE_2G5)) == EEE_1000) {
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REG_SET(RTL8373_EEE_CTRL_BASE + (port << 2), EEE_100 | EEE_1000);
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// Disable EEE advertisement for 2.5GBASE-T via EEE Advertisement Reg 2
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phy_write(port, PHY_MMD_AN, PHY_EEE_ADV2, 0);
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// Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg
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phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_1G | PHY_EEE_BIT_100M);
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phy_reset(port);
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if (!(speed & EEE_NORESET))
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phy_reset(port);
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return;
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}
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if (speed == EEE_2G5) {
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if ((speed & (EEE_100 | EEE_1000 | EEE_2G5)) == EEE_2G5) {
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REG_SET(RTL8373_EEE_CTRL_BASE + (port << 2), EEE_100 | EEE_1000 | EEE_2G5);
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// Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg
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phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_1G | PHY_EEE_BIT_100M);
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// Enable EEE advertisement for 2.5GBASE-T via EEE Advertisement Reg 2
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phy_write(port, PHY_MMD_AN, PHY_EEE_ADV2, PHY_EEE_BIT_2G5);
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phy_reset(port);
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if (!(speed & EEE_NORESET))
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phy_reset(port);
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return;
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}
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@@ -257,6 +257,7 @@
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#define EEE_100 0x01
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#define EEE_1000 0x04
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#define EEE_2G5 0x10
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#define EEE_NORESET 0x80
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/*
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* RANDOM
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@@ -1637,6 +1637,9 @@ void rtl8373_init(void)
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reg_bit_set(RTL837X_REG_HW_CONF, 0);
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// enable EEE for all ports at 2.5G and 10G, but don't reset the PHYs
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port_eee_enable_all(EEE_2G5 | EEE_NORESET);
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// TODO: patch the PHYs
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// Re-enable PHY after configuration
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@@ -1700,6 +1703,10 @@ void rtl8372_init(void)
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reg_bit_set(RTL837X_REG_HW_CONF, 0);
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// enable EEE for all ports at 2.5G and 10G, but don't reset the PHYs
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port_eee_enable_all(EEE_2G5 | EEE_NORESET);
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// TODO: patch the PHYs
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// Re-enable PHY after configuration
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@@ -1954,6 +1961,8 @@ void bootloader(void)
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REG_SET(RTL837X_PIN_MUX_2, 0x0); // Disable pins for ACL
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init_smi();
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rtl8373_revision();
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if (machine_detected.isRTL8373)
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rtl8373_init();
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