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port: make the trunk hash default reachable again, and per group

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Wrapping REG_SET restored the guard in front of the hash default, and
that exposed three things about the line it guards.

The test was against zero. The register does not read zero: it comes out
of reset holding source port number plus both MAC fields, both IP fields
and the L4 source port, which the header now names LAG_HASH_RESET.
Measured on an SWTGW218AS, where all four groups read 0x3f after a cold
boot and a value written before a power cycle is gone afterwards. With
the guard working and the test unreachable, the default would never be
installed, where before it was installed on every call. Testing against
the reset value restores the intent, and zero is still accepted in case
another device does reset that way.

The write went to the base address while the read that decides it used
the group offset, so a group other than zero was tested and group zero
was written. Both ends use the offset now.

The range check printed a complaint and carried on. It returns, which
matters more now that the hash write also uses the group number to build
an address.

Thirty bytes of BANK1.
This commit is contained in:
d00f
2026-08-15 22:01:08 +02:00
committed by d00f
parent 8bc530d3d0
commit a3c586ef38
2 changed files with 8 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rtl837x_port.c
+6 -3
View File
@@ -757,11 +757,14 @@ void port_lag_members_set(__xdata uint8_t lag, __xdata uint16_t members) __banke
{
print_string("port_lag_members_set, lag: "); print_byte(lag); print_string(", members: "); print_short(members);
write_char('\n');
if (lag > 3)
if (lag > 3) {
print_string("Link aggregation group must be 0-3!\n");
return;
}
reg_read_m(RTL837X_TRK_HASH_CTRL_BASE + (lag << 2));
if (!(sfr_data[0] | sfr_data [1] | sfr_data [2] | sfr_data [3]))
REG_SET(RTL837X_TRK_HASH_CTRL_BASE, LAG_HASH_DEFAULT);
if (!(sfr_data[0] | sfr_data[1] | sfr_data[2])
&& (sfr_data[3] == LAG_HASH_RESET || sfr_data[3] == 0))
REG_SET(RTL837X_TRK_HASH_CTRL_BASE + (lag << 2), LAG_HASH_DEFAULT);
REG_WRITE(RTL837X_TRK_MBR_CTRL_BASE + (lag << 2), 0, 0, members >> 8, members & 0xff);
}
rtl837x_regs.h
+2
View File
@@ -232,6 +232,8 @@
#define LAG_HASH_L4_SPORT 0x20
#define LAG_HASH_L4_DPORT 0x40
#define LAG_HASH_DEFAULT (LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC | LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT | LAG_HASH_L4_DPORT)
#define LAG_HASH_RESET (LAG_HASH_SOURCE_PORT_NUMBER | LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC \
| LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT)
/*
* Port isolation