gitproxy/RTLPlayground
1
0
Fork 0
mirror of https://github.com/logicog/RTLPlayground.git synced 2026-08-30 14:52:51 +08:00
Code Issues Packages Projects Releases Wiki Activity

Demagic PHY_MMD_AN, 0x00 to PHY_MMD_AN, PHY_ANEG_CTRL

Browse Source
This commit is contained in:
René van Dorst
2026-01-26 22:41:49 +01:00
parent f9fdc6b81d
commit 7f4c276285
1 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rtl837x_phy.c
+7 -7
View File
@@ -208,10 +208,10 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081); phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081);
// GBCR (1000Base-T Control Register, MMD 31.0xA412) // GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); // Loop timing enabled phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); // Loop timing enabled
phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3200); // Restart AN
} else { } else {
// AN Control Register (MMD 7.0x0000) // AN Control Register (MMD 7.0x0000)
phy_write(port, PHY_MMD_AN, 0x00, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13) phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13)
if (speed == PHY_SPEED_10M) { if (speed == PHY_SPEED_10M) {
phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6001); phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6001);
if (!duplex) if (!duplex)
@@ -248,7 +248,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000); phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000);
} }
} }
phy_write(port, PHY_MMD_AN, 0x00, 0x3000); // Enable AN phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3000); // Enable AN
} }
} }
@@ -256,7 +256,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked
{ {
uint16_t v; uint16_t v;
phy_read(port, PHY_MMD_AN, 0x00); phy_read(port, PHY_MMD31, PHY_ANEG_CTRL);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (!(v & 0x1000)) { // AN disabled, we are in forced mode if (!(v & 0x1000)) { // AN disabled, we are in forced mode
phy_read(port, PHY_MMD31, PHY_MMD31_FEDCR); phy_read(port, PHY_MMD31, PHY_MMD31_FEDCR);
@@ -269,7 +269,7 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked
return; return;
} }
// Disable AN // Disable AN
phy_write(port, PHY_MMD_AN, 0x00, 0x2000); phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x2000);
phy_read(port, PHY_MMD_AN, PHY_ANEG_ADV); phy_read(port, PHY_MMD_AN, PHY_ANEG_ADV);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (v & 0x0060) { if (v & 0x0060) {
@@ -285,7 +285,7 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked
phy_modify(port, PHY_MMD_AN, PHY_ANEG_ADV, 0xff7f, 0x0080); phy_modify(port, PHY_MMD_AN, PHY_ANEG_ADV, 0xff7f, 0x0080);
} }
// Restart AN // Restart AN
phy_write(port, PHY_MMD_AN, 0x00, 0x3000); phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3000);
} }
@@ -327,7 +327,7 @@ void phy_show(uint8_t port) __banked
else else
print_string(" half duplex"); print_string(" half duplex");
phy_read(port, PHY_MMD_AN, 0x00); phy_read(port, PHY_MMD31, PHY_ANEG_CTRL);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (!(v & 0x1000)) { // AN disabled, we are in forced mode if (!(v & 0x1000)) { // AN disabled, we are in forced mode
phy_read(port, PHY_MMD_PMAPMD, 0); phy_read(port, PHY_MMD_PMAPMD, 0);