From 7f4c276285bc31ff93a0c6f7c666c42b9cbcd41a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Mon, 26 Jan 2026 22:41:49 +0100 Subject: [PATCH] Demagic PHY_MMD_AN, 0x00 to PHY_MMD_AN, PHY_ANEG_CTRL --- rtl837x_phy.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/rtl837x_phy.c b/rtl837x_phy.c index 63fffbc..a27a705 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -208,10 +208,10 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081); // GBCR (1000Base-T Control Register, MMD 31.0xA412) phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); // Loop timing enabled - phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN + phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3200); // Restart AN } else { // AN Control Register (MMD 7.0x0000) - phy_write(port, PHY_MMD_AN, 0x00, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13) + phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13) if (speed == PHY_SPEED_10M) { phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6001); if (!duplex) @@ -248,7 +248,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000); } } - phy_write(port, PHY_MMD_AN, 0x00, 0x3000); // Enable AN + phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3000); // Enable AN } } @@ -256,7 +256,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked { uint16_t v; - phy_read(port, PHY_MMD_AN, 0x00); + phy_read(port, PHY_MMD31, PHY_ANEG_CTRL); v = SFR_DATA_U16; if (!(v & 0x1000)) { // AN disabled, we are in forced mode phy_read(port, PHY_MMD31, PHY_MMD31_FEDCR); @@ -269,7 +269,7 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked return; } // Disable AN - phy_write(port, PHY_MMD_AN, 0x00, 0x2000); + phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x2000); phy_read(port, PHY_MMD_AN, PHY_ANEG_ADV); v = SFR_DATA_U16; if (v & 0x0060) { @@ -285,7 +285,7 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked phy_modify(port, PHY_MMD_AN, PHY_ANEG_ADV, 0xff7f, 0x0080); } // Restart AN - phy_write(port, PHY_MMD_AN, 0x00, 0x3000); + phy_write(port, PHY_MMD31, PHY_ANEG_CTRL, 0x3000); } @@ -327,7 +327,7 @@ void phy_show(uint8_t port) __banked else print_string(" half duplex"); - phy_read(port, PHY_MMD_AN, 0x00); + phy_read(port, PHY_MMD31, PHY_ANEG_CTRL); v = SFR_DATA_U16; if (!(v & 0x1000)) { // AN disabled, we are in forced mode phy_read(port, PHY_MMD_PMAPMD, 0);