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Update LAG configuration registers

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logicog
2025-12-05 07:38:16 +01:00
parent e63d1bf577
commit 42ea80a480
2 changed files with 22 additions and 3 deletions
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doc/trunking.md → doc/link_aggregation.md
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rtl837x_regs.h
+22 -3
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@@ -117,6 +117,17 @@
#define RTL837x_L2_TBL_FLUSH_CTRL 0x53d4
#define L2_TBL_FLUSH_EXEC 0x10000
#define RTL837x_L2_TBL_FLUSH_CNF 0x53dc
#define RTL837X_L2_LRN_PORT_CONSTRAINT 0x5384
#define RTL837X_L2_LRN_PORT_CONSTRT_ACT 0x4f80
/*
* VLAN configuration
*/
#define RTL837X_VLAN_CTRL 0x4e14
#define VLAN_CVLAN_FILTER 0x4
#define RTL837X_VLAN_PORT_EGR_TAG 0x6738
#define RTL837X_VLAN_PORT_IGR_FLTR 0x4e18
#define RTL837X_VLAN_L2_LRN_DIS_0 0x4e30
#define RTL837X_VLAN_L2_LRN_DIS_1 0x4e34
/*
* Egress / ingress filtering
@@ -134,10 +145,18 @@
#define RTL837x_MIRROR_CTRL 0x6048
/*
* Trunking
* Link Aggregation aka Trunking
*/
#define RTL837x_TRUNK_CTRL_A 0x4f38
#define RTL837x_TRUNK_CTRL_B 0x4f3c
#define RTL837X_TRK_MBR_CTRL_BASE 0x4f38
#define RTL837X_TRK_HASH_CTRL_BASE 0x4f48
#define LAG_HASH_SOURCE_PORT_NUMBER 0x01
#define LAG_HASH_L2_SMAC 0x02
#define LAG_HASH_L2_DMAC 0x04
#define LAG_HASH_L3_SIP 0x08
#define LAG_HASH_L3_DIP 0x10
#define LAG_HASH_L4_SPORT 0x20
#define LAG_HASH_L4_DPORT 0x40
#define LAG_HASH_DEFAULT (LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC | LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT | LAG_HASH_L4_DPORT)
/*
* Port isolation