From 42ea80a4805f0ebd75e8ac7293217e9c70d3dc3e Mon Sep 17 00:00:00 2001 From: logicog Date: Sun, 30 Nov 2025 22:20:53 +0100 Subject: [PATCH] Update LAG configuration registers --- doc/{trunking.md => link_aggregation.md} | 0 rtl837x_regs.h | 25 +++++++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) rename doc/{trunking.md => link_aggregation.md} (100%) diff --git a/doc/trunking.md b/doc/link_aggregation.md similarity index 100% rename from doc/trunking.md rename to doc/link_aggregation.md diff --git a/rtl837x_regs.h b/rtl837x_regs.h index ce6052e..fb4b6b9 100644 --- a/rtl837x_regs.h +++ b/rtl837x_regs.h @@ -117,6 +117,17 @@ #define RTL837x_L2_TBL_FLUSH_CTRL 0x53d4 #define L2_TBL_FLUSH_EXEC 0x10000 #define RTL837x_L2_TBL_FLUSH_CNF 0x53dc +#define RTL837X_L2_LRN_PORT_CONSTRAINT 0x5384 +#define RTL837X_L2_LRN_PORT_CONSTRT_ACT 0x4f80 +/* + * VLAN configuration + */ +#define RTL837X_VLAN_CTRL 0x4e14 +#define VLAN_CVLAN_FILTER 0x4 +#define RTL837X_VLAN_PORT_EGR_TAG 0x6738 +#define RTL837X_VLAN_PORT_IGR_FLTR 0x4e18 +#define RTL837X_VLAN_L2_LRN_DIS_0 0x4e30 +#define RTL837X_VLAN_L2_LRN_DIS_1 0x4e34 /* * Egress / ingress filtering @@ -134,10 +145,18 @@ #define RTL837x_MIRROR_CTRL 0x6048 /* - * Trunking + * Link Aggregation aka Trunking */ -#define RTL837x_TRUNK_CTRL_A 0x4f38 -#define RTL837x_TRUNK_CTRL_B 0x4f3c +#define RTL837X_TRK_MBR_CTRL_BASE 0x4f38 +#define RTL837X_TRK_HASH_CTRL_BASE 0x4f48 +#define LAG_HASH_SOURCE_PORT_NUMBER 0x01 +#define LAG_HASH_L2_SMAC 0x02 +#define LAG_HASH_L2_DMAC 0x04 +#define LAG_HASH_L3_SIP 0x08 +#define LAG_HASH_L3_DIP 0x10 +#define LAG_HASH_L4_SPORT 0x20 +#define LAG_HASH_L4_DPORT 0x40 +#define LAG_HASH_DEFAULT (LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC | LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT | LAG_HASH_L4_DPORT) /* * Port isolation