gitproxy/RTLPlayground
1
0
Fork 0
mirror of https://github.com/logicog/RTLPlayground.git synced 2026-08-30 14:52:51 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #75 from vDorst/fix_serial_timer1

Browse Source 
Fix: Serial Timer1: GATE bit should be off.
This commit is contained in:
René van Dorst
2026-01-13 19:10:22 +00:00
committed by GitHub
parent 4ce8adf954 f43bb4eac4
commit 030772f1ef
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
installer/installer.c
+1 -1
View File
@@ -111,7 +111,7 @@ void setup_serial_timer1(void)
{ {
// Timer 1: Mode 2: automatic reload // Timer 1: Mode 2: automatic reload
TMOD &= 0x0F; TMOD &= 0x0F;
TMOD |= 0xA0; // Timer1: GATE, Mode2: Timer, 8-bit with auto-reload TMOD |= 0x20; // Timer1: Mode2: Timer, 8-bit with auto-reload
CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4 CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal. PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.
rtlplayground.c
+1 -1
View File
@@ -1693,7 +1693,7 @@ void setup_serial_timer1(void)
{ {
// Timer 1: Mode 2: automatic reload // Timer 1: Mode 2: automatic reload
TMOD &= 0x0F; TMOD &= 0x0F;
TMOD |= 0xA0; // Timer1: GATE, Mode2: Timer, 8-bit with auto-reload TMOD |= 0x20; // Timer1: Mode2: Timer, 8-bit with auto-reload
CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4 CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal. PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.