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293a196c91
Covers enabling it, the bridge and per-port settings, how BPDUs are delivered on this hardware (RMA forward constrained by a CPU-only static L2 entry, since trap-to-CPU targets an external CPU these boards do not have), the timer base, and the management failsafe - enabling STP over the network can block the very port the management VLAN rides on, so that part is spelled out rather than left to be discovered.