mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
d00f
7ec0286d69
Bring the Spanning Tree page in line with a typical managed switch's per-port panel. Configuration gains the full-range path cost (raw 0..200000000, 0 = auto, replacing the old 1000x-scaled byte), a point-to-point admin control (auto/on/off), and the priority is now a 0..240 step-16 dropdown. A new status table shows, per port, the Port State, Role, Designated Bridge / Port ID / Cost (learned from received BPDUs, kept per port and aged via the BPDU age), Operational Edge and Operational Point-to-Point. The designated fields fall back to presenting this switch as the segment's designated bridge when no fresh BPDU has been heard (so a quiet port shows our own bridge-id, as the vendor UIs do). /stp.json carries the packed hex fields plus our own MAC for that fallback. Space: reclaim BANK2 for the above by moving rtl837x_pins to HOME and compacting leds_dump into a register-address table (~800B); bandwidth returns to BANK1. No BANK3 - hardware-verified that PSBANK > 2 crashes this SoC at boot (a bricked unit and an SPI-programmer recovery earlier today); a warning to that effect is now in rtl837x_lldp.c. Hardware-verified: cost 200000000 and p2p off round-trip through the CLI and JSON, the status table populates correctly with STP enabled (all ports Forwarding/Designated, oper-edge and oper-p2p True), LACP 3f/3f and the LAN unaffected. (cherry picked from commit 2ec62072f061dc9e78bc821ba1c297cb6819e206)
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
#include "rtl837x_pins.h"
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#include "rtl837x_common.h"
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#include "rtl837x_regs.h"
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uint8_t i2c_bus_from_sda_pin(uint8_t sda_pin) __banked {
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switch (sda_pin) {
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case GPIO47_I2C_SDA0:
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return 0;
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case GPIO49_I2C_SDA1:
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return 1;
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case GPIO51_I2C_SDA2_UART1_RX:
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return 2;
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case GPIO41_I2C_SDA3_MDIO1:
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return 3;
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case GPIO39_I2C_SDA4:
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return 4;
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default:
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return 0xFF;
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}
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}
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uint8_t i2c_bus_from_scl_pin(uint8_t scl_pin) __banked{
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switch (scl_pin) {
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case GPIO46_I2C_SCL0:
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return 0;
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case GPIO48_I2C_SCL1:
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return 1;
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case GPIO50_I2C_SCL2_UART1_TX:
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return 2;
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case GPIO40_I2C_SCL3_MDC1:
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return 3;
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default:
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return 0xFF;
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}
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}
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/* Returns RTL837X_REG_GPIO_XX_OUTPUT register address */
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static uint16_t gpio_output_reg(uint8_t pin) __banked{
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return pin < 32 ? RTL837X_REG_GPIO_00_31_OUTPUT : RTL837X_REG_GPIO_32_63_OUTPUT;
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}
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/* Returns RTL837X_REG_GPIO_XX_DIRECTION register address */
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static uint16_t gpio_direction_reg(uint8_t pin) __banked {
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return pin < 32 ? RTL837X_REG_GPIO_00_31_DIRECTION : RTL837X_REG_GPIO_32_63_DIRECTION;
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}
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/* Enable GPIO functions for pin */
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static void gpio_mux_setup(uint8_t pin) __banked
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{
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// Some GPIOs require setting MUX registers to enable GPIO
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switch (pin) {
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case GPIO10_LED10:
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reg_bit_clear(RTL837X_PIN_MUX_0, 10);
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break;
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case GPIO30_ACL_BIT3_EN:
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reg_bit_clear(RTL837X_PIN_MUX_2, 3);
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break;
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case GPIO36_PWM_OUT:
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reg_bit_set(RTL837X_PIN_MUX_1, 30);
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break;
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case GPIO37:
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case GPIO38:
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// Intentionally empty, always GPIO
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break;
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case GPIO46_I2C_SCL0:
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// Bit 7-8 0b00 -> GPIO
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reg_read_m(RTL837X_PIN_MUX_1);
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sfr_mask_data(0, 0x80, 0x00);
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sfr_mask_data(1, 0x01, 0x00);
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reg_write_m(RTL837X_PIN_MUX_1);
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break;
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case GPIO50_I2C_SCL2_UART1_TX:
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// Bit 15-16 0b00 -> GPIO
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reg_read_m(RTL837X_PIN_MUX_1);
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sfr_mask_data(1, 0x80, 0x00);
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sfr_mask_data(2, 0x01, 0x00);
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reg_write_m(RTL837X_PIN_MUX_1);
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break;
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case GPIO51_I2C_SDA2_UART1_RX:
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// Bit 17-18 0b00 -> GPIO
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reg_read_m(RTL837X_PIN_MUX_1);
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sfr_mask_data(2, 0x06, 0x00);
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reg_write_m(RTL837X_PIN_MUX_1);
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break;
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case GPIO54_ACL_BIT2_EN:
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reg_bit_clear(RTL837X_PIN_MUX_2, 2);
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break;
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case GPIO_NA:
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print_string("Attemped to assign GPIO function to N/A pin!");
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break;
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default:
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print_string("GPIO MUX setup not implemented for pin="); print_byte(pin); print_string("\n");
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}
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}
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void gpio_input_setup(uint8_t pin) __banked {
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if (pin == GPIO_NA) {
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return;
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}
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gpio_mux_setup(pin);
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reg_bit_clear(gpio_direction_reg(pin), (pin % 32));
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}
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void gpio_output_setup(uint8_t pin, __xdata uint8_t initial_val) __banked{
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if (pin == GPIO_NA) {
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return;
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}
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gpio_mux_setup(pin);
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// We need to setup value before enabling output on PIN
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if (initial_val) {
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reg_bit_set(gpio_output_reg(pin), (pin % 32));
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} else {
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reg_bit_clear(gpio_output_reg(pin), (pin % 32));
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}
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reg_bit_set(gpio_direction_reg(pin), (pin % 32));
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}
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