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231 lines
6.1 KiB
C
231 lines
6.1 KiB
C
#ifndef _RTL837X_REGS_H_
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#define _RTL837X_REGS_H_
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#define RTL837X_REG_HW_CONF 0x6040
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// Bits 4 & 5: CLOCK DIVIDER from 125MHz for Timer
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#define RTL837X_REG_LED_MODE 0x6520
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// Defines the LED Mode for steering the Port LEDS and the System LED
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// BIT 17 set: LED solid on
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// Bytes 0/1 hold the LED mode, e.g. serial, RTL8231?
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// Blink rate is defined by setAsicRegBits(0x6520,0xe00000,rate);
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#define RTL837X_REG_SMI_CTRL 0x6454
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#define RTL837X_REG_RESET 0x0024
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// Writing 0x01 into this register causes a reset of the entire SoC
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#define RTL837X_REG_SEC_COUNTER 0x06f4
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#define RTL837X_REG_SEC_COUNTER2 0x06f8
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// Used for counting seconds
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#define RTL837X_REG_SDS_MODES 0x7b20
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/*
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* 5 Bits each give the state of the 2 SerDes of the RTL8372
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* Values are:
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*/
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#define SDS_SGMII 0x02
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#define SDS_1000BX_FIBER 0x04
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#define SDS_QXGMII 0x0d
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#define SDS_HISGMII 0x12
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#define SDS_HSG 0x16
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#define SDS_10GR 0x1a
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#define SDS_OFF 0x1f
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#define RTL837X_REG_LINKS 0x63f0
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/* Each nibble encodes the link state of a port.
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Port 0 appears to be the CPU port
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The RTL8372 serves ports 4-7, port 3 is the RTL8221
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2: 1Gbit
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5: 2.5Gbit
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*/
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/*
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* Pin configuration (pinmux)
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*/
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#define RTL837X_PIN_MUX_0 0x7f8c
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#define RTL837X_PIN_MUX_1 0x7f90
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// Output Registers
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#define RTL837X_REG_GPIO_00_31_OUTPUT 0x3c
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#define RTL837X_REG_GPIO_32_63_OUTPUT 0x40
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// BIT 4 resets RTL8224 on 9000-9XH
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// Input Registers
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#define RTL837X_REG_GPIO_00_31_INPUT 0x44
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#define RTL837X_REG_GPIO_32_63_INPUT 0x48
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// Bit 1e cleared: SFP Module inserted on 9000-6XH (MOD_DEF0 pin)
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// BIT 5 set: SIGNAL LOS of SFP module on 9000-6XH (RX_LOS pin)
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// Direction Registers, 0 = input, 1 = output
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#define RTL837X_REG_GPIO_00_31_DIRECTION 0x4c
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#define RTL837X_REG_GPIO_32_63_DIRECTION 0x50
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/*
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* I2C controller
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*/
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#define RTL837X_REG_I2C_MST_IF_CTRL 0x0414
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#define RTL837X_REG_I2C_CTRL 0x0418
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#define I2C_DEV_ADDR 3
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#define I2C_MEM_ADDR_WIDTH 20
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#define RTL837X_REG_I2C_CTRL2 0x041c
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#define RTL837X_REG_I2C_IN 0x0420
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#define RTL837X_REG_I2C_OUT 0x0424
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/*
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* NIC Related registers
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*/
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#define RTL837X_REG_RX_CTRL 0x785c
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#define RTL837X_REG_TX_CTRL 0x7860
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#define RTL837X_REG_RX_AVAIL 0x7874
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#define RTL837X_REG_RX_RINGPTR 0x787c
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#define RTL837X_REG_RX_DONE 0x784c
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/*
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* Statistics related registers
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*/
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#define RTL837X_STAT_GET 0x0f60
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#define RTL837X_STAT_V_HIGH 0x0f64
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#define RTL837X_STAT_V_LOW 0x0f68
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/*
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* Table access registers of the RTL837x
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* See e.g. RTL8366/RTL8369 datasheet for explanation
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*/
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#define RTL837X_TBL_CTRL 0x5cac
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/* Bytes in control register: EE EE TT CC: EE: Entry, TT: Table type, CC: Command
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* CC: BIT 0: 01: Execute. Bit 1: 1: WRITE, 0: READ
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* TT: 04: L2-table, 03: VLAN-table
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*/
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// Table operation bit-smasks
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#define TBL_WRITE 0x02
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#define TBL_EXECUTE 0x01
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// Table types
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#define TBL_L2_UNICAST 0x04
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#define TBL_VLAN 0x03
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#define RTL837X_L2_CTRL 0x5350
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#define RTL837x_TBL_DATA_0 0x5cb0
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#define RTL837x_L2_DATA_OUT_A 0x5ccc
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#define RTL837x_L2_DATA_OUT_B 0x5cd0
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#define RTL837x_L2_DATA_OUT_C 0x5cd4
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#define RTL837x_TBL_DATA_IN_A 0x5cb8
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#define RTL837x_PVID_BASE_REG 0x4e1c
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#define RTL837x_L2_TBL_FLUSH_CTRL 0x53d4
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#define L2_TBL_FLUSH_EXEC 0x10000
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#define RTL837x_L2_TBL_FLUSH_CNF 0x53dc
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#define RTL837X_L2_LRN_PORT_CONSTRAINT 0x5384
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#define RTL837X_L2_LRN_PORT_CONSTRT_ACT 0x4f80
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/*
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* VLAN configuration
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*/
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#define RTL837X_VLAN_CTRL 0x4e14
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#define VLAN_CVLAN_FILTER 0x4
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#define RTL837X_VLAN_PORT_EGR_TAG 0x6738
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#define RTL837X_VLAN_PORT_IGR_FLTR 0x4e18
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#define RTL837X_VLAN_L2_LRN_DIS_0 0x4e30
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#define RTL837X_VLAN_L2_LRN_DIS_1 0x4e34
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/*
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* Egress / ingress filtering
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*/
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// 2 bits per port: allow tagged (01) / untagged (10) and all (00)
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#define RTL837x_REG_INGRESS 0x4e10
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#define INGR_ALLOW_TAGGED 1
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#define INGR_ALLOW_UNTAGGED 2
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#define INGR_ALLOW_ALL 0
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/*
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* Mirroring
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*/
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#define RTL837x_MIRROR_CONF 0x604c
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#define RTL837x_MIRROR_CTRL 0x6048
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/*
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* Link Aggregation aka Trunking
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*/
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#define RTL837X_TRK_MBR_CTRL_BASE 0x4f38
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#define RTL837X_TRK_HASH_CTRL_BASE 0x4f48
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#define LAG_HASH_SOURCE_PORT_NUMBER 0x01
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#define LAG_HASH_L2_SMAC 0x02
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#define LAG_HASH_L2_DMAC 0x04
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#define LAG_HASH_L3_SIP 0x08
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#define LAG_HASH_L3_DIP 0x10
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#define LAG_HASH_L4_SPORT 0x20
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#define LAG_HASH_L4_DPORT 0x40
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#define LAG_HASH_DEFAULT (LAG_HASH_L2_SMAC | LAG_HASH_L2_DMAC | LAG_HASH_L3_SIP | LAG_HASH_L3_DIP | LAG_HASH_L4_SPORT | LAG_HASH_L4_DPORT)
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/*
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* Port isolation
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*/
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#define RTL837X_PORT_ISOLATION_BASE 0x50c0
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/*
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* Multicast handling
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*/
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#define RTL837X_MC_LOOKUPMISS_ACTIONS 0x4f78
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#define RTL837X_IGMP_PORT_CFG 0x52a0
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#define RTL837X_MC_FLOODMASK 0x5368
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/*
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* Loop detection / STP
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*/
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#define RTL8373_RLDP_TIMER 0x1074
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#define RTL837X_RMA0_CONF 0x4ecc
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#define RTL837X_RMA_CONF 0x4f1c
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#define RTL837X_MSTP_STATES 0x5310
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/*
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* EEE
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*/
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#define RTL837X_EEE_STATUS 0x125C
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#define RTL837X_MAC_EEE_ABLTY 0x6404
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#define RTL8373_PHY_EEE_ABLTY 0x642C
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#define RTL8373_EEE_CTRL_BASE 0x606c
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#define EEE_100 0x01
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#define EEE_1000 0x04
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#define EEE_2G5 0x10
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/*
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* RANDOM
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*/
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#define RTL837X_RLDP_RLPP 0x106C
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#define RLDP_RND_EN 3
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#define RTL837X_RAND_NUM0 0x107C
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#define RTL837X_RAND_NUM1 0x1080
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#ifdef REGDBG
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#define REG_SET(r, v) SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \
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SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \
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SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \
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SFR_DATA_0 = (v) & 0xff; \
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reg_write(r); \
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write_char('R'); print_byte(r >> 8); print_byte(r); write_char('-'); \
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print_byte(((v) >> 24) & 0xff); print_byte((v) >> 16 & 0xff); print_byte((v) >> 8 & 0xff); print_byte( (v) & 0xff); write_char(' ');
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#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
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SFR_DATA_16 = (v16); \
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SFR_DATA_8 = (v8); \
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SFR_DATA_0 = (v0); \
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reg_write(r); \
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write_char('R'); print_byte(r>>8); print_byte(r); write_char('-'); print_byte(v24); print_byte(v16); print_byte(v8); print_byte(v0); write_char(' ');
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#else
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#define REG_SET(r, v) SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \
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SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \
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SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \
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SFR_DATA_0 = (v) & 0xff; \
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reg_write(r);
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#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
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SFR_DATA_16 = (v16); \
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SFR_DATA_8 = (v8); \
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SFR_DATA_0 = (v0); \
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reg_write(r);
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#endif
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#endif
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