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https://github.com/logicog/RTLPlayground.git
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d00f
7fa26e0ae3
The common segment is the scarce one: sixteen kilobytes shared by every bank, and before this it had about 2.5 kB left. Most of what moves here runs once at startup and does not have to sit in it. The two SerDes helpers are the exception: the link-change handler and the SFP polling both reach sds_config() while the switch is running, so they are not startup-only. None of it is reached from an interrupt. boot.c takes setup_i2c, init_smi, nic_setup, rtl8373_revision, rtl8224_enable, early_boot_handle_button, set_hostname_default and the two SerDes helpers. BANK3 is enabled with the linker flag; nothing else in the build needed changing. Everything moved is declared __banked, since every caller is outside BANK3: main() and friends run from the common area and rtl837x_init.c calls sds_config() and sds_config_mac() from BANK2. The calls the moved code makes outward were already banked, so that side needed no work. Common segment 13393 -> 10137 bytes, leaving 5787 free rather than 2531. BANK3 holds 3732. All 34 machines in machine.h build and link. Walking the generated assembly for plain lcalls that cross a bank boundary finds none among 2808 calls; those build cleanly and only fail at run time, so it seemed worth checking by machine rather than by eye.
266 lines
7.3 KiB
C
266 lines
7.3 KiB
C
#include <stdint.h>
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#include "rtl837x_common.h"
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#include "rtl837x_sfr.h"
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#include "rtl837x_regs.h"
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#include "rtl837x_port.h"
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#include "rtl837x_phy.h"
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#include "phy.h"
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#include "machine.h"
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#include "boot.h"
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extern __xdata uint8_t sfr_data[4];
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extern __code struct machine machine;
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extern __xdata struct machine_runtime machine_detected;
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#pragma codeseg BANK2
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#pragma constseg BANK2
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/*
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* Configure the PHY-Side of the SDS-SDS link between SoC and PHY
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*/
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void static sds_init(void)
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{
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phy_read(0, PHY_MMD30, 0xd);
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uint16_t pval = SFR_DATA_U16;
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// PHY Initialization:
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REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
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delay(20);
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pval &= 0xfff0;
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pval |= 0x0a;
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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delay(10);
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phy_write_mask(0x1, PHY_MMD30, 0xd, pval);
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phy_read(0, PHY_MMD30, 0xd);
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pval = SFR_DATA_U16;
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REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
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pval &= 0xfff0;
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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phy_write_mask(0x1, PHY_MMD30, 0xd, pval);
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if (machine_detected.isN) {
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uint16_t pval;
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print_string(" N-settings");
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if (machine.n_10g)
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print_string(" - 10g");
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// Serdes 0 RX PN swap for 64B/66B
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sds_read(1, 6, 2);
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pval = SFR_DATA_U16;
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sds_write_v(1, 6, 2, pval | 0x2000);
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// Serdes 1 RX PN swap for 8B/10B
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sds_read(1, 0, 0);
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pval = SFR_DATA_U16;
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sds_write_v(1, 0, 0, pval | 0x200);
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// Serdes 0 RX PN swap for 64B/66B
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sds_read(0, 6, 2);
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pval = SFR_DATA_U16;
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sds_write_v(0, 6, 2, pval | 0x2000);
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if (!machine.n_10g) {
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if (machine_detected.isRTL8373) {
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// RTL8224: Serdes 0 RX PN swap for 64B/66B
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// We assume that RTL8373N always paired with RTL8224N.
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// This sds register value is 0x0000 at reset.
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// So only write to it.
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RTL8224_SDS_WRITE(0, 6, 2, 0x2000);
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} else {
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// Serdes 0 RX PN swap for 8B/10B
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sds_read(0, 0, 0);
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pval = SFR_DATA_U16;
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sds_write_v(0, 0, 0, pval | 0x200);
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}
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} else if (machine.n_10g == 1) {
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reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
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sfr_mask_data(0, 0x0f,0x0c);
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reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
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REG_SET(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x0000596a);
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} else if (machine.n_10g == 2) {
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REG_SET(RTL837X_CFG_PHY_MDI_REVERSE, 0xc);
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REG_SET(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x0000596a);
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}
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}
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print_string("\nsds_init done\n");
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}
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void rtl8373_init(void) __banked
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{
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print_string("\nrtl8373_init called\n");
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// r65d8:3ffbedff R65d8-3ffbedff
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reg_bit_set(0x65d8, 0x1d);
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sds_init();
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// Disable all SERDES for configuration
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REG_SET(RTL837X_REG_SDS_MODES, 0x000037ff);
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// q000601:c800 Q000601:c804 q000601:c804 Q000601:c800
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sds_read(0, 0x06, 0x01);
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uint16_t pval = SFR_DATA_U16;
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sds_write_v(0, 0x06, 0x01, pval | 0x04);
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delay(50);
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sds_read(0, 0x06, 0x01);
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pval = SFR_DATA_U16;
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sds_write_v(0, 0x06, 0x01, pval & 0xfffb);
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phy_config_8224();
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sds_config_mac(1, SDS_OFF); // Off for now until SFP+ port used
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sds_config_mac(2, SDS_SGMII); // For RTL8224
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sds_config(0, SDS_QXGMII); // For RTL8224
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// SDS 1 setup
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// q012100:4902 Q012100:4906 q013605:0000 Q013605:4000 Q011f02:001f q011f15:0086
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sds_write_v(1, 0x21, 0x00, 0x4906);
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sds_write_v(1, 0x36, 0x05, 0x4000);
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sds_write_v(1, 0x1f, 0x02, 0x001f);
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sds_read(1, 0x1f, 0x15);
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pval = SFR_DATA_U16;
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// r0a90:000000f3 R0a90-000000fc
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reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
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sfr_mask_data(0, 0x0f,0x0c);
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reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
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if (machine_detected.isN) {
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print_string(" TX_POLARITY_SWAP\n");
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// FOR N-Version: #TX_POLARITY_SWAP
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reg_read_m(RTL837X_CFG_PHY_TX_POLARITY_SWAP);
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sfr_data[2] = 0x59;
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sfr_data[3] = 0x6a;
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reg_write_m(RTL837X_CFG_PHY_TX_POLARITY_SWAP);
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}
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rtl8224_phy_enable();
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// Disable PHYs for configuration
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phy_write_mask(0xff,PHY_MMD31,0xa610,0x2858);
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// Set bits 0x13 and 0x14 of 0x5fd4
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// r5fd4:0002914a R5fd4-001a914a
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reg_bit_set(0x5fd4, 0x13);
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reg_bit_set(0x5fd4, 0x14);
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// Configure ports
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uint16_t reg = 0x1238; // Port base register for the bits we set
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for (char i = 0; i < 9; i++) {
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// Bit 7 (0x40) enables replacement of the RTL-VLAN tag with an 802.1Q VLAN tag
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REG_SET(reg, 0xe77);
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reg += 0x100;
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}
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// r0b7c:000000d8 R0b7c-000000f8 r6040:00000030 R6040-00000031
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reg_bit_set(0xb7c, 5);
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// R7124-00001050 R7128-00001050 R712c-00001050 R7130-00001050 R7134-00001050 R7138-00001050
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// R713c-00001050 R7140-00001050 R7144-00001050 R7148-00001050
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REG_SET(0x7124, 0x1050); REG_SET(0x7128, 0x1050); REG_SET(0x712c, 0x1050);
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REG_SET(0x7130, 0x1050); REG_SET(0x7134, 0x1050); REG_SET(0x7138, 0x1050);
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REG_SET(0x713c, 0x1050); REG_SET(0x7140, 0x1050); REG_SET(0x7144, 0x1050);
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REG_SET(0x7148, 0x1050);
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reg_bit_set(RTL837X_REG_HW_CONF, 0);
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// enable EEE for all ports at 2.5G, but don't reset the PHYs
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port_eee_enable_all(EEE_2G5 | EEE_NORESET);
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// TODO: patch the PHYs
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// Re-enable PHY after configuration
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phy_write_mask(0xff,PHY_MMD31,0xa610,0x2058);
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// Enables MAC access
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// Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init
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// r632c:00000540 R632c-001f8540 // RTL8373: 001ff540
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reg_read_m(0x632c);
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sfr_mask_data(1, 0x70, 0xf0); // The ports of the RTL8824
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sfr_mask_data(2, 0x10, 0x1f);
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reg_write_m(0x632c);
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print_string("\nrtl8373_init done\n");
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}
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void rtl8372_init(void) __banked
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{
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print_string("\nrtl8372_init called\n");
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sds_init();
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if (machine.n_10g != 2)
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phy_config(8); // PHY configuration: External 8221B?
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if (machine.n_10g)
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phy_config_8261(3, 0);
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if (machine.n_10g == 2)
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phy_config_8261(8, 1);
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else
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phy_config(3); // PHY configuration: all internal PHYs?
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// Set the MAC SerDes Modes Bits 0-4: SDS 0 = 0x2 (0x2), Bits 5-9: SDS 1: 1f (off)
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// r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-000003ff r7b20:000003ff R7b20-000003e2 r7b20:000003e2 R7b20-000003e2
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if (machine.n_10g == 1) {
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REG_SET(RTL837X_REG_SDS_MODES, 0x3ed); // Disable SFP for now, set RTL8261BE SDS 0 to 0xd
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} else if(machine.n_10g == 2) {
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REG_SET(RTL837X_REG_SDS_MODES, 0x1ad); // Both 10g ports use SDS_QXGMII
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} else {
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reg_read_m(RTL837X_REG_SDS_MODES);
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sfr_mask_data(1, 0, 0x03);
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sfr_mask_data(0, 0, 0xe2);
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reg_write_m(RTL837X_REG_SDS_MODES);
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}
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// r0a90:000000f3 R0a90-000000fc
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reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
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sfr_mask_data(0, 0x0f, 0x0c);
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reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
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// Disable PHYs for configuration
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phy_write_mask(0xf0,PHY_MMD31,0xa610,0x2858);
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// Set bits 0x13 and 0x14 of 0x5fd4
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// r5fd4:0002914a R5fd4-001a914a
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reg_bit_set(0x5fd4, 0x13);
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reg_bit_set(0x5fd4, 0x14);
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// Configure ports 3-8:
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//
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// r1538:00000e33 R1538-00000e37 r1538:00000e37 R1538-00000e37 r1538:00000e37 R1538-00000f37
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// [...]
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///
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uint16_t reg = 0x1238 + 0x300; // Port base register for the bits we set
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for (char i = machine.min_port; i <= machine.max_port; i++) {
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// Bit 7 (0x40) enables replacement of the RTL-VLAN tag with an 802.1Q VLAN tag
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REG_SET(reg, 0xe77);
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reg += 0x100;
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}
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// r0b7c:000000d8 R0b7c-000000f8 r6040:00000030 R6040-00000031
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reg_bit_set(0xb7c, 5);
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reg_bit_set(RTL837X_REG_HW_CONF, 0);
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// enable EEE for all ports at 2.5G and 10G, but don't reset the PHYs
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port_eee_enable_all(EEE_10G | EEE_NORESET);
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// TODO: patch the PHYs
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// Re-enable PHY after configuration
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phy_write_mask(0xf0,PHY_MMD31,0xa610,0x2058);
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// Enables MAC access
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// Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init
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// r632c:00000540 R632c-001f8540 // RTL8373: 001ff540
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reg_read_m(0x632c);
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sfr_mask_data(1, 0x70, 0x80);
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sfr_mask_data(2, 0x10, 0x1f);
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reg_write_m(0x632c);
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print_string("\nrtl8372_init done\n");
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}
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