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https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Tobias Diedrich
c3a6a46852
This adds the MPAGE (sdcc _XPAGE) SFR, which is used by sdcc in `--xstack` mode to provide the upper byte of the address for `MOVX A, @Ri` and `MOVX @Ri, A` instructions. Classic 8051 uses the P2 SFR value for this, but the RTL IP block does not seem to be using the "Port 2 module". From the databook: ``` To replace the function of the Port 2 latch in designs that do not use a Port 2 module, the DW8051 provides an additional special function register, MPAGE, at SFR address 92h. During MOVX A, @Ri and MOVX @Ri, A instructions, the DW8051 places the contents of the MPAGE register on the upper 8 address bits (mem_addr[15:8]). This provides the paging function that is normally provided by the Port 2 latch. The MPAGE register has no function when a Port 2 module is used to connect external RAM. ```
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/* SFR control registers for switch register access */
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__sfr __at(0xa0) SFR_EXEC_GO;
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__sfr __at(0xa1) SFR_EXEC_STATUS;
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__sfr16 __at(0xa2a3) SFR_REG_ADDR_U16;
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__sfr __at(0xa2) SFR_REG_ADDRH;
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__sfr __at(0xa3) SFR_REG_ADDRL;
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__sfr16 __at(0xa6a7) SFR_DATA_U16;
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__sfr32 __at(0xa4a5a6a7) SFR_DATA_U32;
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__sfr32 __at(0xa7a6a5a4) SFR_DATA_U32LE;
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__sfr __at(0xa4) SFR_DATA_24;
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__sfr __at(0xa5) SFR_DATA_16;
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__sfr __at(0xa6) SFR_DATA_8;
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__sfr __at(0xa7) SFR_DATA_0;
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// Command bytes to write to SFR_EXEC_GO
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#define SFR_EXEC_READ_REG 1
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#define SFR_EXEC_WRITE_REG 3
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#define SFR_EXEC_READ_SDS 5
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#define SFR_EXEC_WRITE_SDS 7
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#define SFR_EXEC_READ_SMI 9
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#define SFR_EXEC_WRITE_SMI 11
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/* SFR control registers for phy access via SMI/MDIO */
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__sfr16 __at(0xc2c3) SFR_SMI_REG_U16;
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__sfr __at(0xc2) SFR_SMI_REG_H;
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__sfr __at(0xc3) SFR_SMI_REG_L;
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__sfr __at(0xc4) SFR_SMI_DEV;
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__sfr __at(0xc5) SFR_SMI_PHYMASK;
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#define SFR_SMI_PHY SFR_DATA_16
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/* Extended IRQ EIE register for external interrupts */
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__sfr __at(0xe8) EIE;
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__sbit __at(0xe8) EX2;
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__sbit __at(0xe9) EX3;
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/* EXIF additional external IRQ control register */
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__sfr __at(0x91) EXIF;
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/* Extended IRQ EIP register for external interrupt priority */
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__sfr __at(0xf8) EIP;
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__sbit __at(0xf9) PX3;
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/* MPAGE page (sdcc _XPAGE) register for "movx @Ri" */
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__sfr __at(0x92) _XPAGE; /* _XPAGE is used by sdcc in xstack mode */
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__sfr __at(0x92) MPAGE;
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/* SFR Bank control register: 0x0-3f. A value of 0 is bank 1 */
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__sfr __at(0x96) PSBANK;
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// SFR used to store return bank for trampoline
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__sfr __at(0xbb) SFR_BANK_RET;
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__sfr __at(0x8e) CKCON;
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__sfr __at(0x97) SFR_97; // HADDR?
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__sfr __at(0xb9) SFR_b9;
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__sfr __at(0xba) SFR_ba;
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// Clause 22 PHY access ???
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__sfr __at(0x93) SFR_93;
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__sfr __at(0x94) SFR_94;
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/* FLASH controller SFRs */
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__sfr __at(0x80) SFR_FLASH_EXEC;
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__sbit __at(0x82) SFR_FLASH_EXEC_GO;
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__sbit __at(0x80) SFR_FLASH_EXEC_BUSY;
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__sfr __at(0xb1) SFR_FLASH_CMD_R;
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__sfr __at(0xb2) SFR_FLASH_CMD;
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__sfr __at(0xbc) SFR_FLASH_CONFIG;
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__sfr __at(0x9b) SFR_FLASH_CONF_DIV;
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__sfr __at(0x9c) SFR_FLASH_CONF_RCMD;
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__sfr __at(0x9d) SFR_FLASH_DUMMYCYCLES;
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__sfr __at(0x9a) SFR_FLASH_MODEB;
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__sfr __at(0x9e) SFR_FLASH_TCONF;
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__sfr __at(0xaf) SFR_FLASH_DATA24;
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__sfr __at(0xae) SFR_FLASH_DATA16;
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__sfr __at(0xad) SFR_FLASH_DATA8;
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__sfr __at(0xac) SFR_FLASH_DATA0;
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__sfr __at(0xab) SFR_FLASH_ADDR16;
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__sfr __at(0xaa) SFR_FLASH_ADDR8;
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__sfr __at(0xa9) SFR_FLASH_ADDR0;
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/*
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* NIC Interface
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* CAREFUL: This is now Little Endian
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*/
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__sfr __at(0xb7) SFR_NIC_CTRL;
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__sfr16 __at(0xb4b3) SFR_NIC_DATA_U16LE;
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__sfr __at(0xb3) SFR_NIC_DATA_L;
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__sfr __at(0xb4) SFR_NIC_DATA_H;
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__sfr16 __at(0xb6b5) SFR_NIC_RING_U16LE;
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__sfr __at(0xb5) SFR_NIC_RING_L;
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__sfr __at(0xb6) SFR_NIC_RING_H;
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/* Standard 8051 sfr */
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// Timer 0 value
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__sfr16 __at(0x8c8a) T0_U16;
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// Timer 1 enable interrupt
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__sbit __at(0xad) ET2;
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// Timer 2
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__sfr __at(0xcc) TL2;
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__sfr __at(0xcd) TH2;
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__sfr16 __at(0xcdcc) T2_U16;
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__sfr __at(0xc8) T2CON;
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__sfr __at(0xca) RCAP2L;
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__sfr __at(0xcb) RCAP2H;
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__sfr16 __at(0xcbca) RCAP2_U16;
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