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64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
#ifndef _PHY_H_
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#define _PHY_H_
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/*
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* The RTL8272/RTL8273 appear to comprise an RTL8224 PHY
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* which in turn is a 4x RTL8221B PHY
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* These phys are all Clause 45
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* The defines below are taken from the RTL8221B datasheet
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*/
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/*
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* Define PHY pages
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*/
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#define PHY_MMD_PMAPMD 1
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#define PHY_MMD_AN 7
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#define PHY_MMD30 30
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#define PHY_MMD31 31
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/*
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* Define registers in Auto-Negotiation page
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*/
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#define PHY_ANEG_CTRL 0x00
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#define PHY_ANEG_ADV 0x10
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#define PHY_ANEG_LP_ABILITY 0x13
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#define PHY_ANEG_MGBASE_CTRL 0x20
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#define PHY_ANEG_MGBASE_ADV 0x21
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#define PHY_EEE_ADV 0x3c
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#define PHY_EEE_LP_ABILITY 0x3d
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#define PHY_EEE_ADV2 0x3e
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#define PHY_EEE_LP_ABILITY2 0x3f
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// Register bits for EEE capabilities at a given speed
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// PHY_EEE_ADV2
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#define PHY_EEE_BIT_2G5 0x01
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#define PHY_EEE_BIT_5G 0x02
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// PHY_EEE_ADV
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#define PHY_EEE_BIT_1G 0x04
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#define PHY_EEE_BIT_100M 0x02
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#define PHY_EEE_BIT_10G 0x08
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/*
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* MMD 31 Registers
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*/
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#define PHY_MMD31_FEDCR 0xa400
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#define PHY_MMD31_GBCR 0xa412
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#define PHY_MMD31_GANLPAR 0xa414
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#define PHY_MMD31_PHYCR2 0xa432
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#define PHY_MMD31_PHYSR 0xa434
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/*
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* Define registers in Control page
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*/
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#define PHY_CTRL_5 0x7582
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/*
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* Duplex settings
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*/
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#define PHY_DUPLEX_HALF 0
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#define PHY_DUPLEX_FULL 1
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#define PHY_DUPLEX_BOTH 2
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#endif
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