mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
René van Dorst
8b061d5fb9
Downside of Timer0 is, we have to manually reload the timer value. Timer2 can do that automaticly. This saves a lot of time in the interrupt-handler of the Timer. Currently Timer2 is used for baudrate-generation but in a separete commit this is moved to Timer1.
58 lines
1.0 KiB
NASM
58 lines
1.0 KiB
NASM
.globl __start__stack
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;--------------------------------------------------------
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; Stack segment in internal ram
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;--------------------------------------------------------
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.area SSEG (DATA)
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__start__stack:
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.ds 1
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.area VECTOR (CODE)
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.globl __interrupt_vect
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__interrupt_vect:
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ljmp __sdcc_gsinit_startup
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ljmp _isr_ext0 ; 0x03
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.ds 5
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ljmp _isr_timer0 ; 0x0b
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.ds 5
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ljmp _isr_ext1 ; 0x13
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.ds 5
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reti ; 0x1b TIMER 1 IRQ
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.ds 7
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ljmp _isr_serial ; 0x23
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.ds 5
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ljmp _isr_timer2 ; 0x2b TIMER 2 IRQ
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.ds 5
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reti ; 0x33 NOT used by DW8051
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.ds 7
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reti ; 0x3b Serial port 1 RX/TX IRQ
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.ds 7
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ljmp _isr_ext2 ; 0x43
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.ds 5
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ljmp _isr_ext3 ; 0x4b
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.globl __start__stack
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.area GSINIT0 (CODE)
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__sdcc_gsinit_startup::
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mov sp,#__start__stack - 1
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.area GSFINAL (CODE)
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ljmp _bootloader
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__sdcc_banked_call::
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push _PSBANK
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xch a,r0
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push a
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mov a,r1
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push a
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mov a,r2
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anl a,#0x1f
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mov _PSBANK, a
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xch a, r0
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ret
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__sdcc_banked_ret::
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pop _PSBANK
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ret
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