mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
386 lines
9.1 KiB
C
386 lines
9.1 KiB
C
#include <8051.h>
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#include <stdint.h>
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// #define REGDBG 1
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// #define RXTXDBG 1
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#define UPDATE_LOC 0x0001D000
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#define HEADER_LENGTH 0x14
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#define UPDATE_CODE_LOC (UPDATE_LOC + HEADER_LENGTH)
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#include "../rtl837x_sfr.h"
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#include "../rtl837x_regs.h"
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// See setup_serial_timer1() for valid baudrate settings!
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#define SERIAL_BAUD_RATE 57600
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#define CLOCK_HZ 125000000
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// Derive the divider settings for the internal clock
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#if CLOCK_HZ == 20800000
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#define CLOCK_DIV 3
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#elif CLOCK_HZ == 31250000
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#define CLOCK_DIV 2
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#elif CLOCK_HZ == 62500000
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#define CLOCK_DIV 1
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#elif CLOCK_HZ == 125000000
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#define CLOCK_DIV 0
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#endif
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// We buffer 1 sector as this is also the erase size
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__xdata uint8_t buffer[0x1000];
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__xdata uint8_t dio_enabled;
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__code uint8_t * __code hex = "0123456789abcdef";
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void isr_timer0(void) __interrupt(1)
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{
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}
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void isr_ext0(void) __interrupt(0)
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{
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EX0 = 0; // Disable interrupt for the moment
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IT0 = 1; // Trigger on falling edge of external interrupt
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EX0 = 1; // Re-enable interrupt
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}
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void isr_ext1(void) __interrupt(2)
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{
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EX1 = 0;
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EX1 = 1;
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}
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void write_char(char c)
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{
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do {
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} while (TI == 0);
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TI = 0;
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if (c =='\n') {
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SBUF = '\r';
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do {
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} while (TI == 0);
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TI = 0;
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}
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SBUF = c;
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}
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void print_string(__code char *p)
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{
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while (*p)
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write_char(*p++);
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}
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void print_byte(uint8_t a)
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{
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write_char(hex[(a >> 4) & 0xf]);
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write_char(hex[a & 0xf]);
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}
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void print_short(uint16_t a)
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{
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print_string("0x");
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for (signed char i = 12; i >= 0; i -= 4) {
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write_char(hex[(a >> i) & 0xf]);
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}
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}
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/* Set up serial port 0 using Timer 1 as baudrate generator.
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* For x Bd these settings are needed, see table below.
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* NOTE: Settings only valid for F_SYS = 125 MHz!
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* | Wanted | | TMR | F_SYS | | Actual | |
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* | baudrate | SMOD0 | DIV | DIV | TH1 | baudrate | Error |
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* | -------- | ----- | --- | ----- | ---- | -------- | ------ |
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* | 1200 | 0 | 12 | 255 | 0x01 | 1276.6 | 6.00% |
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* | 2400 | 0 | 12 | 136 | 0x78 | 2393.5 | −0.27% |
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* | 4800 | 0 | 4 | 203 | 0x35 | 4810.7 | 0.22% |
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* | 9600 | 1 | 4 | 203 | 0x35 | 9621.3 | 0.22% |
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* | 14400 | 1 | 4 | 136 | 0x78 | 14361.2 | −0.27% |
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* | 19200 | 1 | 4 | 102 | 0x9a | 19148.3 | −0.27% |
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* | 38400 | 1 | 4 | 51 | 0xcd | 38296.6 | −0.27% |
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* | 57600 | 1 | 4 | 34 | 0xde | 57444.9 | −0.27% |
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* | 115200 | 1 | 4 | 17 | 0xef | 114889.7 | −0.27% |
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*/
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#if CLOCK_HZ != 125000000
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#warning "SERIAL 0 baudrate setting may only valid for F_CPU = 125 MHz!"
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#endif
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void setup_serial_timer1(void)
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{
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// Timer 1: Mode 2: automatic reload
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TMOD &= 0x0F;
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TMOD |= 0x20; // Timer1: Mode2: Timer, 8-bit with auto-reload
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CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
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PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.
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SCON = 0x50; // Mode = 1: ASYNC 8N1 with Timer 2 as baud-rate generator, REN_0 Receive enable
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/* The TH1 register contain the reload value, timer1 when T1 overflows to 0x100.
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* NOTE: compiler computs the wrong value. 0xF0 is calculated but 0xEF is the right value for 115200.
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* Also https://www.keil.com/products/c51/baudrate.asp confirms this.
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* Added 32 before div by 64 to make sure rounding is correct so that the results are right.
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*
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* TH1 = 0x100 - (2^SMOD0 * F_SYS) / ( TMR1_DIV / BAUDRATE * 32)
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*/
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TH1 = (0x100 - (((CLOCK_HZ / SERIAL_BAUD_RATE) + 32) / (4 * 16))) & 0xff;
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TCON |= 0x40; // Start timer 1
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ET1 = 0; // Timer1 Interrupt is NOT wanted!
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TI = 1; // Set TI-interrupt/flag, to flag that the TX-buf is empty.
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RI = 0; // Clear RI-interrupt flag
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ES = 0; // Disable serial IRQ, software is only printing data and just polls TI-flag.
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}
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/*
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* Configure Memory Managed IO
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*/
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void flash_configure_mmio(void)
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{
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// Set configuration for MMIO access by controller
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if (dio_enabled) {
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SFR_FLASH_MODEB = 0x18;
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SFR_FLASH_CMD_R = 0xbb; // By default we read with Dual speed
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SFR_FLASH_DUMMYCYCLES = 4;
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return;
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}
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = 0xb; // By default we read with single speed
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SFR_FLASH_DUMMYCYCLES = 8;
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}
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/*
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* Initializes the flash controller for programmed control
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* The configuration options are not really understood, the SPI speed
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* seems to be directly linked to the CPU frequency
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* This configures fast single IO at 20.8 MHz when the CPU clock is at 20.8MHz
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* and 62.5MHz when the CPU clock is configured at 125MHz
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*/
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void flash_init(uint8_t enable_dio)
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{
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if (enable_dio) {
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// Configure fast DIO via divider/DIO/SIOconfig = 4 and read-cmd being 0xbb (for mmio)
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SFR_FLASH_CONFIG = 9; // There may be a chip-select in here
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SFR_FLASH_CONF_RCMD = 0xbb;
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SFR_FLASH_CONF_DIV = 4;
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} else {
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// Configure fast read via divider = 8 and read-cmd being 0xb (for mmio)
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SFR_FLASH_CONFIG = 9;
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SFR_FLASH_CONF_RCMD = 0xb;
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SFR_FLASH_CONF_DIV = 8;
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}
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// Test Controller Busy
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while(SFR_FLASH_EXEC_BUSY);
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// Write 0 to status register
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SFR_FLASH_DUMMYCYCLES = 8;
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SFR_FLASH_MODEB = 0;
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SFR_FLASH_TCONF = 0x19;
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SFR_FLASH_CMD = 1;
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SFR_FLASH_DATA0 = 0;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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dio_enabled = enable_dio;
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flash_configure_mmio();
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}
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uint8_t flash_read_status(void)
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{
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// Test Controller Busy (we might call this directly after executing a command)
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while(SFR_FLASH_EXEC_BUSY);
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// setup status read command
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SFR_FLASH_TCONF = 0x11;
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SFR_FLASH_CMD_R = 5;
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// execute and wait for controller done
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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return SFR_FLASH_DATA0;
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}
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/*
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* Reads bulk data of length len from the flash memory starging at address src
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* and writes the data into a buffer pointed to by dst in XMEM
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*/
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void flash_read_bulk(register __xdata uint8_t *dst, __xdata uint32_t src, register uint16_t len)
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{
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short status;
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do {
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status = flash_read_status();
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} while (status & 0x1);
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// Set fast read mode
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if (dio_enabled) {
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SFR_FLASH_MODEB = 0x18;
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SFR_FLASH_CMD_R = 0xbb;
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SFR_FLASH_DUMMYCYCLES = 4;
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} else {
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SFR_FLASH_MODEB = 0x0;
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SFR_FLASH_CMD_R = 0xb; // Fast read
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SFR_FLASH_DUMMYCYCLES = 8; // Add 8 dummy clocks after read?
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}
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// Read 4 bytes
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SFR_FLASH_TCONF = 4;
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while (len) {
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SFR_FLASH_ADDR16 = src >> 16;
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SFR_FLASH_ADDR8 = src >> 8;
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SFR_FLASH_ADDR0 = src;
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src += 4;
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SFR_FLASH_EXEC_GO = 1;
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while(SFR_FLASH_EXEC_BUSY);
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*dst++ = SFR_FLASH_DATA0;
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if (len == 1)
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return;
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*dst++ = SFR_FLASH_DATA8;
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if (len == 2)
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return;
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*dst++ = SFR_FLASH_DATA16;
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if (len == 3)
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return;
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*dst++ = SFR_FLASH_DATA24;
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len -= 4;
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}
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}
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void flash_write_enable(void)
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{
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short status;
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// Wait until busy bit clear
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do {
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status = flash_read_status();
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} while (status & 0x1);
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// while (flash_read_status() & 0x1);
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SFR_FLASH_TCONF = 0x18;
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SFR_FLASH_CMD = 6;
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SFR_FLASH_DUMMYCYCLES = 0;
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SFR_FLASH_MODEB = 0;
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SFR_FLASH_EXEC_GO = 1;
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// Wait for write status enabled
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do {
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status = flash_read_status();
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} while (!(status & 0x2));
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}
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// Erases the 4k sector in which the address lies
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void flash_sector_erase(uint32_t addr)
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{
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flash_write_enable();
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SFR_FLASH_TCONF = 8;
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SFR_FLASH_CMD = 0x20;
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SFR_FLASH_ADDR16 = addr >> 16;
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SFR_FLASH_ADDR8 = addr >> 8;
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SFR_FLASH_ADDR0 = addr;
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SFR_FLASH_EXEC_GO = 1;
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while (flash_read_status() & 0x1);
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flash_configure_mmio();
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}
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void flash_write_bytes(__xdata uint32_t addr, __xdata uint8_t *ptr, uint16_t len)
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{
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uint8_t exit_loop = 0;
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while(1) {
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flash_write_enable();
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SFR_FLASH_CMD = 2;
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SFR_FLASH_TCONF = 0x40 | 8 | 4; // Bytes written is 4, 8 enables write, 0x40 is unknown
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// Last transfer?
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if (len < 5) {
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SFR_FLASH_TCONF = 8 | len;
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exit_loop = 1;
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}
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SFR_FLASH_ADDR16 = addr >> 16;
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SFR_FLASH_ADDR8 = addr >> 8;
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SFR_FLASH_ADDR0 = addr;
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SFR_FLASH_DATA0 = *ptr++;
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SFR_FLASH_DATA8 = *ptr++;
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SFR_FLASH_DATA16 = *ptr++;
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SFR_FLASH_DATA24 = *ptr++;
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// Execute transfer, we wait for completion at top of loop
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SFR_FLASH_EXEC_GO = 1;
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if (exit_loop)
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break;
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len -= 4;
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addr += 4;
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}
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while (flash_read_status() & 0x1);
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flash_configure_mmio();
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}
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void reg_write(uint16_t reg_addr)
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{
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/* Data to write must be in SFR A4, A5, A6, A7 */
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SFR_REG_ADDR_U16 = reg_addr;
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SFR_EXEC_GO = SFR_EXEC_WRITE_REG;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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void installer(void)
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{
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CKCON = 0; // Initial Clock configuration
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SFR_97 = 0; // HADDR?
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// Set in managed mode:
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SFR_b9 = 0x00;
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SFR_ba = 0x80;
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// Disable all interrupts (global and individually) by setting IE register (SFR A8) to 0
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IE = 0;
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EIE = 0; // SFR e8: EIE. Disable all external IRQs
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setup_serial_timer1();
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print_string("\nRTLPlayground installer starting...\n");
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// Initialize flash functions with disable DIO because writing does not work otherwise
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flash_init(0);
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__xdata uint32_t dest = 0x0;
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__xdata uint32_t source = UPDATE_CODE_LOC;
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// A 512kByte = 4MBit Flash has 128 sectors, we copy only 120
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for (uint8_t i=0; i < 120; i++) {
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print_string("Moving block\n");
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flash_read_bulk(buffer, source, 0x1000);
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for (uint8_t j = 0; j < 32; j++) {
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write_char(' '); print_byte(buffer[j]);
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}
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write_char('\n');
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flash_sector_erase(dest);
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flash_write_bytes(dest, buffer, 0x1000);
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dest += 0x1000;
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source += 0x1000;
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}
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print_string("Done.\n");
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print_string("Reseting now\n");
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REG_SET(RTL837X_REG_RESET, 1);
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}
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