Merge pull request #775 from brunoz78/de-stp

i18n(de): translate the new Spanning Tree texts

.github/workflows/build.yml

@@ -7,8 +7,6 @@ on:
 
 permissions:
   contents: read
-  pull-requests: write
-  issues: write
 
 jobs:
   build:
@@ -40,19 +38,16 @@ jobs:
       - name: Check that every machine definition can be compiled
         run: cd branch && make machine_check
       - name: Make project (4x2/RTL8372)
-        run: cd branch && make CI=1 MACHINE="KP_9000_6XHML_X2" && cp output/KP_9000_6XHML_X2/rtlplayground.map /tmp/branch.map
+        run: mkdir -p /tmp/branch /tmp/main && cd branch && make CI=1 MACHINE="KEEPLINK_KP_9000_6XHML_X2" && cp -r output/KEEPLINK_KP_9000_6XHML_X2/rtlplayground.map output/KEEPLINK_KP_9000_6XHML_X2/rtlplayground.mem output/KEEPLINK_KP_9000_6XHML_X2/html_min /tmp/branch/
       - name: Make project (8x1/RTL8373)
-        run: cd branch && make CI=1 MACHINE="KP_9000_9XHML_X_V3_1"
+        run: cd branch && make CI=1 MACHINE="KEEPLINK_KP_9000_9XHML_X_V3_1"
       - name: Make project with the health instrumentation
-        run: cd branch && make clean && make CI=1 MACHINE="KP_9000_6XHML_X2" HEALTH=1
+        run: cd branch && make clean && make CI=1 MACHINE="KEEPLINK_KP_9000_6XHML_X2" HEALTH=1
       - name: Make main
         run: |
           ln -s ../branch/toolchain main/toolchain
           PATH="$(echo "$PWD"/branch/toolchain/sdcc-*/bin):$PATH"
-          cd main && make CI=1 MACHINE="KP_9000_6XHML_X2" && cp output/KP_9000_6XHML_X2/rtlplayground.map /tmp/main.map
+          cd main && make CI=1 MACHINE="KEEPLINK_KP_9000_6XHML_X2" && cp -r output/KEEPLINK_KP_9000_6XHML_X2/rtlplayground.map output/KEEPLINK_KP_9000_6XHML_X2/rtlplayground.mem output/KEEPLINK_KP_9000_6XHML_X2/html_min /tmp/main/
       - name: Calculate bank growth
         run: |
-          sed -rn 's/^([XCD]SEG|(BANK[0-9])).*=\s+([0-9]+)\. bytes.*$/MAIN_\1=\3/p' /tmp/main.map | sort -u >> "$GITHUB_ENV"
-          sed -rn 's/^([XCD]SEG|(BANK[0-9])).*=\s+([0-9]+)\. bytes.*$/BRANCH_\1=\3/p' /tmp/branch.map | sort -u >> "$GITHUB_ENV"
-          du -sb main/output/KP_9000_6XHML_X2/html_min | awk '{print "MAIN_WEB="$1}' >> "$GITHUB_ENV"
-          du -sb branch/output/KP_9000_6XHML_X2/html_min | awk '{print "BRANCH_WEB="$1}' >>"$GITHUB_ENV"
+          bash branch/tools/bank_occupancy.sh KP_9000_6XHML_X2 /tmp/main /tmp/branch >> "$GITHUB_STEP_SUMMARY"

CHANGELOG.md

@@ -23,6 +23,11 @@
 
 ## Changed
 
+- Web UI
+  - The web session expires after one hour without a request (was 200 seconds). The UI stops
+    polling while its tab is hidden, so with 200 seconds switching tabs for a few minutes logged
+    you out. `session <seconds>` still sets it.
+
 ## Fixed
 
 - Time

Makefile

@@ -150,10 +150,12 @@ SRCS += \
 	rtl837x_lldp.c \
 	rtl837x_storm.c \
 	rtl837x_lacp.c \
-	rtl837x_trap.c
+	rtl837x_trap.c \
+	rtl837x_stp_cli.c
 SRCS += \
 	httpd/httpd.c \
-	httpd/page_impl.c
+	httpd/page_impl.c \
+	httpd/page_stp.c
 SRCS += \
 	uip/timer.c \
 	uip/uip.c \
@@ -165,7 +167,7 @@ SRCS += \
 
 OBJS = ${SRCS:%.c=$(BUILDDIR)/%.rel}
 DEPS := ${SRCS:%.c=$(BUILDDIR)/%.d}
-HTML := $(shell find html -name '*.js' -or -name '*.html' -or -name '*.svg' -or -name '*.css' -or -name '*.ico')
+HTML := $(shell find html -name '*.html' -or -name '*.svg' -or -name '*.css' -or -name '*.ico')
 
 # Minified copy of the web UI sources, used as the fileadder input.
 # The raw html/ sources stay untouched for development; the minified
@@ -181,10 +183,11 @@ $(HTML_MIN_LIST): FORCE
 	@echo $(sort $(HTML)) > $@.tmp
 	@cmp -s $@.tmp $@ && rm -f $@.tmp || mv $@.tmp $@
 
-$(HTML_MIN_STAMP): $(HTML) $(HTML_MIN_LIST) tools/minify.py $(if $(wildcard $(HTML_MIN)),,FORCE)
+$(HTML_MIN_STAMP): $(HTML) html/app.js $(HTML_MIN_LIST) tools/minify.py tools/rjsmin.py $(if $(wildcard $(HTML_MIN)),,FORCE)
 	rm -rf $(HTML_MIN)
 	mkdir -p $(HTML_MIN)
 	@for f in $(HTML); do python3 tools/minify.py $$f $(HTML_MIN)/$$(basename $$f) || exit 1; done
+	python3 tools/rjsmin.py < html/app.js > $(HTML_MIN)/app.js || exit 1
 	@touch $@
 
 html_data.c html_data.h &: $(HTML_MIN_STAMP) | tools
@@ -246,7 +249,7 @@ $(BUILDDIR)/%.rel: %.asm $(CCFLAGS_STAMP) | create_build_dir
 #	mv -f $(addprefix $(basename $^), .lst .rel .sym) .
 
 $(BUILDDIR)/rtlplayground.ihx: $(OBJS) $(BUILDDIR)/crtbank.rel $(BUILDDIR)/crc16.rel
-	$(CC) $(CC_FLAGS) --xram-size 49151 -Wl-bHOME=0x00000 -Wl-bBANK1=0x14000 -Wl-bBANK2=0x24000 -Wl-bBANK3=0x34000 -Wl-r -o $@ $^
+	$(CC) $(CC_FLAGS) --xram-size 49151 -Wl-bHOME=0x00000 -Wl-bBANK1=0x14000 -Wl-bBANK2=0x24000 -Wl-bBANK3=0x34000 -Wl-bBANK4=0x44000 -Wl-r -o $@ $^
 
 $(BUILDDIR)/rtlplayground.img: $(BUILDDIR)/rtlplayground.ihx
 	objcopy --input-target=ihex -O binary $< $@

README.md

@@ -97,17 +97,25 @@ docker run --rm -v $(pwd):/workspace rtlplayground-dev make MACHINE=DEFAULT_8C_1
 
 The resulting `.bin` file appears in `output/` on your host.
 
+Build the OEM web upgrade bin (after building the firmware bin)
+
+```
+docker run --rm -v $(pwd):/workspace rtlplayground-dev make -C installer
+```
+
+The resulting `rtlplayground_oem_upgrade.bin` file appears in `installer/output/` on your host.
+
 Build host tools only:
 
 ```
 docker run --rm -v $(pwd):/workspace rtlplayground-dev make -C tools
 ```
 
-Run the web-interface simulator locally:
+Run the web-interface simulator through docker:
 
 ```
-docker run --rm -p 8080:8080 -v $(pwd):/workspace rtlplayground-dev \
-  tools/output/httpd_sim /workspace/html
+docker run --rm -p 8081:8081 -v $(pwd):/workspace rtlplayground-dev \
+  tools/output/httpd_sim.py /workspace/html
 ```
 
 Edit `config.txt` on your host, then re-run `make` — the
@@ -363,13 +371,37 @@ netmask zzz.zzz.zzz.zzz = Network mask of the switch
 port x name xxx         = Name xxx the port number x
 port z 1g               = Set 1g speed for port z
 igmp on/off             = Turn IGMP on or off
-session xxxx            = Web session timeout in seconds (default 200)
+session xxxx            = Web session timeout in seconds (default 3600)
 ```
 [To be continue]
 
 Enjoy playing!
 
-## (11) Other documents
+## (13) HTTP Simulator for front-end development
+
+The simulator is available in tools as `./httpd_sim.py`
+By default it will serve the content in the current working directory so the easiest way to run this is to:
+```
+cd ./html
+../tools/httpd_sim.py
+```
+And the simulator will be available on http://127.0.0.1:8081
+
+There are commandline options available:
+```
+usage: httpd_sim.py [-h] [--machine MACHINE] [--port PORT] [--bindaddr BINDADDR] [--verbose]
+
+options:
+  -h, --help           show this help message and exit
+  --machine MACHINE    path to machine.c or .h file to parse (optional)
+  --port PORT          port to bind to (default 8081)
+  --bindaddr BINDADDR  address to bind (default 127.0.0.1)
+  --verbose            enable verbose output
+```
+
+The machine parsing is somewhat experimental.
+
+## (12) Other documents
 
 The following documents give further documentation on specific features of the RTL837x SoCs:
 - [Adding a new device](doc/adding-a-device.md)

cmd_parser.c

@@ -945,6 +945,8 @@ void parse_port(void)
 		print_string("\"\n");
 	} else if (cmd_compare(2, "lldp")) {
 		if (cmd_compare(3, "block")){
+			if (lldp_enabled)
+				lldp_shutdown((uint16_t)1 << phy_settings.port);
 			lldp_logical_port_status &= ~((uint16_t)1 << phy_settings.port);
 		} else if (cmd_compare(3, "permit")) {
 			lldp_logical_port_status |= (uint16_t)1 << phy_settings.port;
@@ -1870,6 +1872,10 @@ void cmd_parser(void) __banked
 		if (cmd_compare(0, "reset")) {
 			print_string("\nRESET\n\n");
 			reset_chip();
+		} else if (cmd_compare(0, "factory-reset")) {
+			print_string("\nFACTORY RESET\n\n");
+			flash_default_config();
+			reset_chip();
 		} else if (cmd_compare(0, "sfp")) {
 			parse_sfp();
 		} else if (cmd_compare(0, "stat")) {
@@ -2089,6 +2095,8 @@ void cmd_parser(void) __banked
 				trap_rma_set(RTL837X_RMA0E_CONF, RTL837X_RMA_ACT_TRAP);
 			} else {
 				print_string("LLDP disabled\n");
+				if (lldp_enabled)
+					lldp_shutdown(lldp_logical_port_status);
 				lldp_enabled = 0;
 				trap_rma_set(RTL837X_RMA0E_CONF, RTL837X_RMA_ACT_FORWARD);
 			}

doc/devices/270-NB1-MS206B004A1-REV.A1.md

@@ -26,11 +26,11 @@ Manufacturer information be found [on the product page](https://www.trendnet.com
 
 Top side
 
-<img src="photos/TEG-S562/TEG-S562-v1.0R-top.jpg" width="300" />
+<img src="photos/270-NB1-MS206B004A1-REV.A1/TEG-S562-v1.0R-top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/TEG-S562/TEG-S562-v1.0R-bottom.jpg" width="300" />
+<img src="photos/270-NB1-MS206B004A1-REV.A1/TEG-S562-v1.0R-bottom.jpg" width="300" />
 
 ## Connectors
 

doc/devices/2G5F4_10G2_V1.01.md

@@ -167,9 +167,9 @@ each cage - the left cage reports `sds_config sds: 01` and the right cage
 
 ### Machine target
 
-Build for this device with `make MACHINE=2G5F4_10G2_V1_01`, which selects the
-`machine/2G5F4_10G2_V1_01.c` board definition. It is derived from
-`machine/KP_9000_6XHML_X2.c` with the SFP cage order and the reset pin changed.
+Build for this device with `make MACHINE=HONGYAVISION_HYWS_SGT0204S`, which selects the
+`machine/HONGYAVISION_HYWS_SGT0204S.c` board definition. It is derived from
+`machine/KEEPLINK_KP_9000_6XHML_X2.c` with the SFP cage order and the reset pin changed.
 The fitted T25S40 cannot be read in DIO mode on this board: an image that leaves
 DIO enabled does not come up at all, both at the default read clock divider of 4
 and at 8 (two boards tested), while the same image with single-IO boots and runs

doc/devices/2G5F_20G_V1.01.md

@@ -32,15 +32,15 @@ Stock flash chip is 512KB in size. Consider replacing for update through Web UI.
 
 Top side
 
-<img src="photos/HYWS-SGT0108S-unmanaged\Assembled-top.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/Assembled-top.jpg" width="300" />
 
 Front
 
-<img src="photos/HYWS-SGT0108S-unmanaged\Assembled-front.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/Assembled-front.jpg" width="300" />
 
 Bottom
 
-<img src="photos/HYWS-SGT0108S-unmanaged\Assembled-bottom.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/Assembled-bottom.jpg" width="300" />
 
 ### PCB overview
 
@@ -49,15 +49,15 @@ Bottom
 
 Top side
 
-<img src="photos/HYWS-SGT0108S-unmanaged\PCB-top.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/PCB-top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/HYWS-SGT0108S-unmanaged\PCB-bot.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/PCB-bot.jpg" width="300" />
 
 Original SPI Flash Chip
 
-<img src="photos/HYWS-SGT0108S-unmanaged\og_spi_flash.jpg" width="300" />
+<img src="photos/2G5F_20G_V1.01/og_spi_flash.jpg" width="300" />
 
 ## Power supply
 

doc/devices/2M-PCB23-V2.2.md

@@ -7,7 +7,7 @@
 
 ## PCB
 
-<img src="photos/2M-PCB23-V2.2-managed/2M-PCB23-V2.2-top.jpg" width="300" />
+<img src="photos/2M-PCB23-V2.2/2M-PCB23-V2.2-top.jpg" width="300" />
 
 ## Port overview
 

doc/devices/2M-PCB23-V3.1.md

@@ -7,7 +7,7 @@
 
 ## PCB
 
-<img src="photos/2M-PCB23-V3.1-managed/2M-PCB23-V3.1-top.jpeg" width="300" />
+<img src="photos/2M-PCB23-V3.1/2M-PCB23-V3.1-top.jpeg" width="300" />
 
 ## Port overview
 

doc/devices/2M-PCB23-V3.2.md

@@ -10,14 +10,14 @@ The original web interface reports this board as hardware version V3.2
 
 ## PCB
 
-<img src="photos/2M-PCB23-V3.2-managed/2M-PCB23-V3.2-top.jpeg" width="300" />
+<img src="photos/2M-PCB23-V3.2/2M-PCB23-V3.2-top.jpeg" width="300" />
 
 ## Compared to V3.1
 
-The component placement matches [2M-PCB23-V3.1](2M-PCB23-V3_1.md): same
+The component placement matches [2M-PCB23-V3.1](2M-PCB23-V3.1.md): same
 positions for the flash (U8), the T7/T8/T9/T10 headers, the SFP cage and its
 LED, and the unpopulated U7/U9 footprints. Build with
-`make MACHINE=KP_9000_9XHML_X_V3_2`, whose board file is a symlink to the V3.1
+`make MACHINE=KEEPLINK_KP_9000_9XHML_X_V3_2`, whose board file is a symlink to the V3.1
 definition and only differs in the reported name.
 
 ## Tested

doc/devices/2M-PCB43-V1.1.md

@@ -15,17 +15,17 @@ and sold by Mokerlink.
 The device is fully supported:
 - All 4 2.5GBASE-T RJ45 ports work at 10/100/1000/2500 Mbps
 - The SFP+ port supports 1G, 2.5G and 10G modules 
-- LEDs work with the same indiciations as the OEM firmware (build with `make MACHINE=KP_9000_6XHML_X2_V1_1` if building yourself, or use the corresponding pre-compiled binary)
+- LEDs work with the same indiciations as the OEM firmware (build with `make MACHINE=MOKERLINK_2G040210GSM` if building yourself, or use the corresponding pre-compiled binary)
 - untested due to missing Hardware: SFP+ ports equipped with 1G or 2.5G SFPs.
 
 ### Hardware overview
 Front
 
-<img src="photos/2M-PCB43-V1.1-managed/2M-PCB43-V1.1-front.jpeg" width="300" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-front.jpeg" width="300" />
 
 Label
 
-<img src="photos/2M-PCB43-V1.1-managed/2M-PCB43-V1.1-label.jpeg" width="300" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-label.jpeg" width="300" />
 
 ### PCB overview
 
@@ -34,11 +34,11 @@ Label
 
 Top side
 
-<img src="photos/2M-PCB43-V1.1-managed/2M-PCB43-V1.1-top.jpeg" width="300" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-top.jpeg" width="300" />
 
 Bottom
 
-<img src="photos/2M-PCB43-V1.1-managed/2M-PCB43-V1.1-bottom.jpeg" width="300" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-bottom.jpeg" width="300" />
 
 ### J1, serial console
 

doc/devices/2M-PCB43-V2.1.md

@@ -22,9 +22,9 @@ reliable indicator of PCB wiring. The PCB revision defines the hardware layout.
 
 | PCB silkscreen | Known labels / devices | Recommended machine target | Equivalent target | Legacy target |
 | --- | --- | --- | --- | --- |
-| `2M-PCB43-V1.1` | Mokerlink 2G040210GSM web-managed 4+2 switch | `MACHINE_KP_9000_6XHML_X2_V1_1` | `MACHINE_KP_9000_6XH_X2_V1_1` | `MACHINE_KP_9000_6XHML_X2` |
-| `2M-PCB43-V1.2` | `KP-9000-6XHML-X2` | `MACHINE_KP_9000_6XHML_X2_V1_2` | `MACHINE_KP_9000_6XH_X2_V1_2` | `MACHINE_KP_9000_6XHML_X2` |
-| `2M-PCB43-V2.1` | `KP-9000-6XH-X2`, `KP-9000-6XHML-X2` | `MACHINE_KP_9000_6XH_X2_V2_1` or `MACHINE_KP_9000_6XHML_X2_V2_1` | same V2.1 layout | `MACHINE_KP_9000_6XH_X2` |
+| `2M-PCB43-V1.1` | Mokerlink 2G040210GSM web-managed 4+2 switch | `MACHINE_MOKERLINK_2G040210GSM` | `MACHINE_KEEPLINK_KP_9000_6XH_V1_1` | `MACHINE_KEEPLINK_KP_9000_6XHML_X2` |
+| `2M-PCB43-V1.2` | `KP-9000-6XHML-X2` | `MACHINE_KEEPLINK_KP_9000_6XHML_V1_2` | `MACHINE_KEEPLINK_KP_9000_6XH_V1_2` | `MACHINE_KEEPLINK_KP_9000_6XHML_X2` |
+| `2M-PCB43-V2.1` | `KP-9000-6XH-X2`, `KP-9000-6XHML-X2` | `MACHINE_KEEPLINK_KP_9000_6XH_X2_V2_1` or `MACHINE_KEEPLINK_KP_9000_6XHML_V2_1` | same V2.1 layout | `MACHINE_KEEPLINK_KP_9000_6XH_X2` |
 
 The V1.1 and V1.2 boards currently use the same V1.x GPIO, SFP, port and LED
 layout. The V2.1 board uses a different V2.1 layout with custom LED muxing.
@@ -42,11 +42,11 @@ new builds should prefer the explicit PCB-revision targets.
 
 Front side:
 
-<img src="photos/2M-PCB43-V2.1-unmanaged/KP-9000-6XH-X2-front.jpg" width="600" />
+<img src="photos/2M-PCB43-V2.1/KP-9000-6XH-X2-front.jpg" width="600" />
 
 Label:
 
-<img src="photos/2M-PCB43-V2.1-unmanaged/KP-9000-6XH-X2-label.jpg" width="600" />
+<img src="photos/2M-PCB43-V2.1/KP-9000-6XH-X2-label.jpg" width="600" />
 
 
 
@@ -57,11 +57,11 @@ Label:
 
 Top side
 
-<img src="photos/2M-PCB43-V2.1-unmanaged/2M-PCB43-V2.1-top.jpg" width="600" />
+<img src="photos/2M-PCB43-V2.1/2M-PCB43-V2.1-top.jpg" width="600" />
 
 Bottom
 
-<img src="photos/2M-PCB43-V2.1-unmanaged/2M-PCB43-V2.1-bottom.jpg" width="600" />
+<img src="photos/2M-PCB43-V2.1/2M-PCB43-V2.1-bottom.jpg" width="600" />
 
 ### Hardware overview: 2M-PCB43-V1.1 / V1.2
 
@@ -71,15 +71,15 @@ Both use the same V1.x layout.
 
 Label:
 
-<img src="photos/KP-9000-6XHML-X2/label.jpg" width="600" />
+<img src="photos/2M-PCB43-V2.1/KP-9000-6XH-X2-label.jpg" width="600" />
 
 Top side:
 
-<img src="photos/KP-9000-6XHML-X2/pcb_top.jpg" width="600" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-top.jpeg" width="600" />
 
 Bottom:
 
-<img src="photos/KP-9000-6XHML-X2/pcb_bottom.jpg" width="600" />
+<img src="photos/2M-PCB43-V1.1/2M-PCB43-V1.1-bottom.jpeg" width="600" />
 
 ## Reset Button
 

doc/devices/2M-PCB51-ML-V1.1.md

@@ -12,11 +12,11 @@ The`KP-9000-9XHP-X` is the KeepLink rebrand for same product.
 ## Hardware overview
 Front
 
-<img src="photos/POE-2G080110GS/POE-2G080110GS-front.jpg" width="300" />
+<img src="photos/2M-PCB51-ML-V1.1/POE-2G080110GS-front.jpg" width="300" />
 
 Label
 
-<img src="photos/POE-2G080110GS/POE-2G080110GS-label.jpg" width="300" />
+<img src="photos/2M-PCB51-ML-V1.1/POE-2G080110GS-label.jpg" width="300" />
 
 The stock firmware from a POE-2G080110GS device had a sha256sum of `4c280853465eaad80e1772075c0f2d29c11fb8c561547f06353d3a5443c388e9`.
 
@@ -24,11 +24,11 @@ The stock firmware from a POE-2G080110GS device had a sha256sum of `4c280853465e
 
 Top silkscreen is marked `2M-PCB51-ML-V1.1`. PoE is provided by RTL8238C. Flash chip is 4 MB Winbond 25Q32JV (U8).
 
-<img src="photos/POE-2G080110GS/POE-2G080110GS-pcb.jpg" width="300" />
+<img src="photos/2M-PCB51-ML-V1.1/POE-2G080110GS-pcb.jpg" width="300" />
 
 > [!CAUTION]
 > This device operates on mains voltage, which can be a dangerous or potentially lethal hazard. Even after the device is unplugged, high-voltage capacitors can remain charged afterward and may still shock you. Do not attempt to open/disassemble a mains powered device unless you understand how to do so safely. Also, opening the device may void your warranty.
 
 ## Notes
 
-The stock firmware blinks both the 2.5G and 1G LEDs on activity, despite the front of the device indicating that each LED should be independent. The `POE_2G080110GS` machine config behaves as the front of the device indicates (and what seems more logical) -- each port LED turns on and blinks independently.
+The stock firmware blinks both the 2.5G and 1G LEDs on activity, despite the front of the device indicating that each LED should be independent. The `MOKERLINK_POE_2G080110GS` machine config behaves as the front of the device indicates (and what seems more logical) -- each port LED turns on and blinks independently.

doc/devices/F7008-2.5GPOE-V1.2.md

@@ -27,7 +27,7 @@ Documentation for the unmanaged 8 + 1 switch sold as `7018-2.5G` by Guangnianwei
 ### Build target
 
 ```
-make MACHINE=F7008_2_5
+make MACHINE=GUANGNIANWEI_7018_2_5G
 ```
 
 ### LED wiring
@@ -57,11 +57,11 @@ The board is marked `F7008-2.5GPOE-V1.2`.
 
 Top side:
 
-<img src="photos/F7008-2.5/PCB-top.jpg" width="600" />
+<img src="photos/F7008-2.5GPOE-V1.2/PCB-top.jpg" width="600" />
 
 Bottom side:
 
-<img src="photos/F7008-2.5/PCB-bottom.jpg" width="600" />
+<img src="photos/F7008-2.5GPOE-V1.2/PCB-bottom.jpg" width="600" />
 
 ### Hardware notes
 

doc/devices/HG0402XG-V1.1.md

@@ -12,12 +12,12 @@
 - **Ports**:
   - 4 × RJ45: 10/100/1000/2500 Mbps
   - 2 × SFP+: 1000 / 2500 / 10000 Mbps
-<img src="photos/HG0402XG_V1_1/HG0402XG_V1_1_bottom.jpg" width="300" />
+<img src="photos/HG0402XG-V1.1/ZOERAX_HG0402XG_V1_1_bottom.jpg" width="300" />
 
 ## PCB
 
-<img src="photos/HG0402XG_V1_1/HG0402XG_V1_1_top.jpg" width="300" />
-<img src="photos/HG0402XG_V1_1/HG0402XG_V1_1_bottom.jpg" width="300" />
+<img src="photos/HG0402XG-V1.1/ZOERAX_HG0402XG_V1_1_top.jpg" width="300" />
+<img src="photos/HG0402XG-V1.1/ZOERAX_HG0402XG_V1_1_bottom.jpg" width="300" />
 
 Be aware that the UART header is metric, the pitch is 2mm. The JST PH2.0mm header shown was addeded after purchase
 

doc/devices/NONAME-20240111.md

@@ -18,13 +18,13 @@ ONT-S207CW-62TS-SE, Binardat 2G06-04210GSM (managed), and Binardat 2G06-04210GS
 ### Binardat 2G06-04210GSM
 
 **Front View:**
-<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-front.jpg" width="400" />
+<img src="photos/NONAME-20240111/binardat-2g06-04210gsm-front.jpg" width="400" />
 
 **Back View:**
-<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-back.jpg" width="400" />
+<img src="photos/NONAME-20240111/binardat-2g06-04210gsm-back.jpg" width="400" />
 
 **PCB View:**
-<img src="photos/ONT-S207CW-Binardat-2G06-04210GSM/binardat-2g06-04210gsm-pcb.jpg" width="400" />
+<img src="photos/NONAME-20240111/binardat-2g06-04210gsm-pcb.jpg" width="400" />
 
 *Photos courtesy of [andreas5232](https://github.com/andreas5232) from [emesix/ONT-S207CW-62TS-SE#1](https://github.com/emesix/ONT-S207CW-62TS-SE/issues/1)*
 

doc/devices/PB-2131.md

@@ -26,7 +26,7 @@ Using SPI clamp in-board is the only method for initial installation.
 
 Top side
 
-<img src="photos/STEAMEMO_IG204_V1/PCB-top.jpg" width="600" />
+<img src="photos/PB-2131/PCB-top.jpg" width="600" />
 
 ### Connectors
 ### T7, serial console

doc/devices/PCB-310S-4T2XT-V1.0.0_22273.md

@@ -17,7 +17,7 @@ PHY 2x RTL8261BE
   - 2 x RJ45: 10/100/1000/2500/5000/10000 Mbps
 - **Power**: 12V DC, 2A barrel connector
 
-<img src="photos/ZX310S-4T2XT/label.jpg" width="300" />
+<img src="photos/PCB-310S-4T2XT-V1.0.0_22273/label.jpg" width="300" />
 
 ### What works
 The device is fully supported:
@@ -28,15 +28,15 @@ The device is fully supported:
 ### PCB overview
 
 **Board markings**
-- Top silkscreen: PCB-SL310S-4T2XT-V1.0.0-22273
+- Top silkscreen: PCB-310S-4T2XT-V1.0.0_22273
 
 Top side
 
-<img src="photos/ZX310S-4T2XT/pcb_top.jpg" width="300" />
+<img src="photos/PCB-310S-4T2XT-V1.0.0_22273/pcb_top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/ZX310S-4T2XT/pcb_bottom.jpg" width="300" />
+<img src="photos/PCB-310S-4T2XT-V1.0.0_22273/pcb_bottom.jpg" width="300" />
 
 ### J1, serial console
 

doc/devices/PCB-AFGW-SWTG218ANS_V2.0.2_23308.md

@@ -25,21 +25,21 @@ RTL8373-based 8×2.5G PoE + 1×10G SFP+ web-managed switch, sold as the
 
 Front panel:
 
-<img src="photos/PCB-AFGW_SWTG218ANS_V2.0.2/device_front.jpg" width="800" />
+<img src="photos/PCB-AFGW-SWTG218ANS_V2.0.2_23308/device_front.jpg" width="800" />
 
 Board mounted in the case, with the internal PSU above it:
 
-<img src="photos/PCB-AFGW_SWTG218ANS_V2.0.2/dev_top_w_pcb.jpg" width="800" />
+<img src="photos/PCB-AFGW-SWTG218ANS_V2.0.2_23308/dev_top_w_pcb.jpg" width="800" />
 
 ### PCB overview
 
 Top side:
 
-<img src="photos/PCB-AFGW_SWTG218ANS_V2.0.2/pcb_front.jpg" width="800" />
+<img src="photos/PCB-AFGW-SWTG218ANS_V2.0.2_23308/pcb_front.jpg" width="800" />
 
 Bottom side:
 
-<img src="photos/PCB-AFGW_SWTG218ANS_V2.0.2/pcb_back.jpg" width="800" />
+<img src="photos/PCB-AFGW-SWTG218ANS_V2.0.2_23308/pcb_back.jpg" width="800" />
 
 A 4-pad UART header with `RXD` / `TXD` silkscreened sits next to the right heatsink. 
 

doc/devices/PCB-K0402W-U13-V2.0.md

@@ -30,11 +30,11 @@ Using SPI clamp in-board is the only method for initial installation.
 
 Front panel
 
-<img src="photos/FNS-1200P/chassis-front.jpg" width="400" />
+<img src="photos/PCB-K0402W-U13-V2.0/chassis-front.jpg" width="400" />
 
 Top side (PCB)
 
-<img src="photos/FNS-1200P/PCB-top.jpg" width="300" />
+<img src="photos/PCB-K0402W-U13-V2.0/PCB-top.jpg" width="300" />
 
 ### Port layout
 

doc/devices/PCB-K0402W-V1.0.md

@@ -6,7 +6,7 @@ The board does have footprints for a VLAN modeswitch at the front and a second f
 
 ### Brands
 
-* YuanLey YS25-0402 <sup><sub>Note: there are [multiple revisions](PCB-K0402WS-V3.0.md) of the YS25-0402. This first revision lacks the "Vlan" switch cutout on the front of the enclosure.</sub></sup>
+* YuanLey YS25-0402 <sup><sub>Note: there are [multiple revisions](PCB-K0402W-V3.0.md) of the YS25-0402. This first revision lacks the "Vlan" switch cutout on the front of the enclosure.</sub></sup>
 
 ### Programming
 
@@ -14,7 +14,7 @@ Use a SOIC-8 clamp to the flash chip (U1 on silkscreen) at the top of the board,
 
 The board has been seen to ship with a single [BoyaMicro BY25Q16BSSIG](https://www.lcsc.com/datasheet/C382744.pdf) 16Mbit (2MiB) chip, though exact BOM may vary.
 
-<a href="photos/PCB-K0402WS-V1.0/flash.jpg"><img src="photos/PCB-K0402WS-V1.0/flash.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/flash.jpg"><img src="photos/PCB-K0402W-V1.0/flash.jpg" width="300" /></a>
 
 ### What works
 
@@ -33,19 +33,19 @@ The board has been seen to ship with a single [BoyaMicro BY25Q16BSSIG](https://w
 
 Front panel
 
-<a href="photos/PCB-K0402WS-V1.0/ports.jpg"><img src="photos/PCB-K0402WS-V1.0/ports.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/ports.jpg"><img src="photos/PCB-K0402W-V1.0/ports.jpg" width="300" /></a>
 
 PCB top
 
-<a href="photos/PCB-K0402WS-V1.0/pcb-top.jpg"><img src="photos/PCB-K0402WS-V1.0/pcb-top.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/pcb-top.jpg"><img src="photos/PCB-K0402W-V1.0/pcb-top.jpg" width="300" /></a>
 
 PCB bottom
 
-<a href="photos/PCB-K0402WS-V1.0/pcb-bottom.jpg"><img src="photos/PCB-K0402WS-V1.0/pcb-bottom.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/pcb-bottom.jpg"><img src="photos/PCB-K0402W-V1.0/pcb-bottom.jpg" width="300" /></a>
 
 Bottom and rear
 
-<a href="photos/PCB-K0402WS-V1.0/bottom.jpg"><img src="photos/PCB-K0402WS-V1.0/bottom.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/bottom.jpg"><img src="photos/PCB-K0402W-V1.0/bottom.jpg" width="300" /></a>
 
 ### Power supply
 
@@ -69,4 +69,4 @@ Standard 0.1" / 2.54mm pin headers will not fit, so wires or clips may be used i
 
 The image below shows some oversized clips clumsily attached.
 
-<a href="photos/PCB-K0402WS-V1.0/uart.jpg"><img src="photos/PCB-K0402WS-V1.0/uart.jpg" width="300" /></a>
+<a href="photos/PCB-K0402W-V1.0/uart.jpg"><img src="photos/PCB-K0402W-V1.0/uart.jpg" width="300" /></a>

doc/devices/PCB-K0402W-V2.0.md

@@ -30,15 +30,15 @@ Using SPI clamp in-board is the only method for initial installation.
 
 Front panel
 
-<img src="photos/PCB-K0402WS-V2.0/chassis-front.jpg" width="400" />
+<img src="photos/PCB-K0402W-V2.0/chassis-front.jpg" width="400" />
 
 Bottom label
 
-<img src="photos/PCB-K0402WS-V2.0/chassis-bottom.jpg" width="400" />
+<img src="photos/PCB-K0402W-V2.0/chassis-bottom.jpg" width="400" />
 
 Top side (PCB)
 
-<img src="photos/PCB-K0402WS-V2.0/PCB-top.jpg" width="300" />
+<img src="photos/PCB-K0402W-V2.0/PCB-top.jpg" width="300" />
 
 ### Port layout
 

doc/devices/PCB-K0402W-V3.0.md

@@ -11,21 +11,21 @@ of the device just above the big label, might be covered by a QC sticker.
 
 * Hisource Hi-K0402WS
 
-<img src="photos/PCB-K0402WS-V3.0/HiSource_HI-K0402WS.jpg" width="300" />
+<img src="photos/PCB-K0402W-V3.0/HiSource_HI-K0402WS.jpg" width="300" />
 
 * Ztyuav Z-QWYT0402
 
-<img src="photos/PCB-K0402WS-V3.0/Ztyuav_Z-QWYT0402.jpg" width="300" />
+<img src="photos/PCB-K0402W-V3.0/Ztyuav_Z-QWYT0402.jpg" width="300" />
 
-<img src="photos/PCB-K0402WS-V3.0/Ztyuav_Z-QWYT0402_label.jpg" width="300" />
+<img src="photos/PCB-K0402W-V3.0/Ztyuav_Z-QWYT0402_label.jpg" width="300" />
 
 * SICSOLINK SL-G0402F
 
-<img src="photos/PCB-K0402WS-V3.0/SICSOLINK SL-G0402F.jpg" width="300"/>
+<img src="photos/PCB-K0402W-V3.0/SICSOLINK SL-G0402F.jpg" width="300"/>
 
-* YuanLey YS25-0402 <sup><sub>Note: there are [multiple revisions](PCB-K0402WS-V1.0.md) of the YS25-0402. This is the newer revision that has a "Vlan" switch on the front.</sub></sup>
+* YuanLey YS25-0402 <sup><sub>Note: there are [multiple revisions](PCB-K0402W-V1.0.md) of the YS25-0402. This is the newer revision that has a "Vlan" switch on the front.</sub></sup>
 
-<img src="photos/PCB-K0402WS-V3.0/YuanLey_YS25-0402.jpg" width="300"/>
+<img src="photos/PCB-K0402W-V3.0/YuanLey_YS25-0402.jpg" width="300"/>
 
 ### Programming
 
@@ -37,7 +37,7 @@ The switch actually controls the HOLD line of each flash chip, and toggling the
 
 If the programming clip keeps HOLD not connected, the flashing will commence on whatever the switch selected, regardless on which chip was clipped.
 
-For the initial flash (at least with flashrom), the bin file produced by the build is much smaller than the flash chip, it is suggested to pad the file to keep flashrom happy: `truncate -s 2097152 rtlplayground-*-PCB_K0402WS_V3.bin`. Note: do not then proceed to use this resulting padded file for the web flashing (as it bricks the device), use the original unpadded .bin.
+For the initial flash (at least with flashrom), the bin file produced by the build is much smaller than the flash chip, it is suggested to pad the file to keep flashrom happy: `truncate -s 2097152 rtlplayground-*-HISOURCE_HI_K0402WS_PCB_K0402WS_V3_0.bin`. Note: do not then proceed to use this resulting padded file for the web flashing (as it bricks the device), use the original unpadded .bin.
 
 ### What works (expected from label + similar devices)
 
@@ -52,11 +52,11 @@ For the initial flash (at least with flashrom), the bin file produced by the bui
 
 Top side
 
-<img src="photos/PCB-K0402WS-V3.0/PCB-top.jpg" width="300" />
+<img src="photos/PCB-K0402W-V3.0/PCB-top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/PCB-K0402WS-V3.0/PCB-bottom.jpg" width="300" />
+<img src="photos/PCB-K0402W-V3.0/PCB-bottom.jpg" width="300" />
 
 ### T2, serial console
 
@@ -82,3 +82,15 @@ Voltage is made by a `Techcode TD1720` .
 Voltage is created by chip marked as `Techcode TD1720`.
 
 **There seems to have been a miscalculation when choosing the inductor and the device is ~25% more efficient with an 5V power supply.**
+
+
+## Reset Mod
+
+A reset button can be easily added by soldering a push button from TP131 (near the Spi ROM) to ground via a 1KOhm resistor.
+
+**PS:** `The reset button GPIO must be defined in the machine.c file before building the image, it must be selected the GPIO30_ACL_BIT3_EN instead of GPIO_NA under the PCB-K0402W-V3.0 configuration.`
+
+Photo of the mod
+
+<img src="photos/PCB-K0402W-V3.0/Reset_mod.jpg" width="300" />
+

doc/devices/PCB-K0501W-V2.0.md

@@ -18,6 +18,6 @@ The BoyaMicro 25Q16BSSIG flash chip is supported by flashprog with chip name "B.
 
 The board is marked `PCB-K0501W-V2.0 DIP-K0501WS-V2.0`.
 
-<img src="photos/K0501W_V2_0/pcb-top.jpg" width="300" />
+<img src="photos/PCB-K0501W-V2.0/pcb-top.jpg" width="300" />
 
-<img src="photos/K0501W_V2_0/pcb-bottom.jpg" width="300" />
+<img src="photos/PCB-K0501W-V2.0/pcb-bottom.jpg" width="300" />

doc/devices/PCB-K0801W-V2.0.md

@@ -21,15 +21,15 @@ Using SPI clamp in-board is the only method for initial installation.
 ### PCB overview
 
 **Board markings**  
-- Top silkscreen: PCB-KO801W-V2.0 / DIP-KO801WS-V2.0  
+- Top silkscreen: PCB-K0801W-V2.0 / DIP-KO801WS-V2.0  
 
 Top side
 
-<img src="photos/K0801W-V2.0-unmanaged\PCB-top.jpg" width="300" />
+<img src="photos/PCB-K0801W-V2.0/PCB-top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/K0801W-V2.0-unmanaged\PCB-bottom.jpg" width="300" />
+<img src="photos/PCB-K0801W-V2.0/PCB-bottom.jpg" width="300" />
 
 ## Power supply
 

doc/devices/PCB-SL310S-4T1T1X-V1.0.1-24107.md

@@ -22,7 +22,7 @@ PHY RTL8261BE
   - 1 × SFP+: 1000 / 2500 / 10000 Mbps
 - **Power**: 12V DC, 2A barrel connector 
 
-<img src="photos/ZX310S-4T2XH/label.jpg" width="300" />
+<img src="photos/PCB-SL310S-4T1T1X-V1.0.1-24107/label.jpg" width="300" />
 
 ### What works
 The device is fully supported:
@@ -38,11 +38,11 @@ The device is fully supported:
 
 Top side
 
-<img src="photos/ZX310S-4T2XH/pcb_top.jpg" width="300" />
+<img src="photos/PCB-SL310S-4T1T1X-V1.0.1-24107/pcb_top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/ZX310S-4T2XH/pcb_bottom.jpg" width="300" />
+<img src="photos/PCB-SL310S-4T1T1X-V1.0.1-24107/pcb_bottom.jpg" width="300" />
 
 ### J1, serial console
 

doc/devices/PCB-SWTG018AS-A-V2.0.1_19649.md

@@ -1,14 +1,14 @@
-# SWTG018AS-A V2.0
+# PCB-SWTG018AS-A V2.0.1_19649
 ## Brands
 | Brand   | Type             |Managed| PCB              | Flash           | Chip RTL      |
 |---------|------------------|-------|------------------|-----------------|---------------|
-| Ampcom  | SWTG018AS-A V2.0 | No    | SWTG018AS-A V2.0 | 2MB             | 8273N + 8224N |
-| Horaco  | HC-SWTGW218AS-A  | Yes   | SWTG018AS-A V2.0 | 2MB(25Q16JVSIQ) | 8273N + 8224N |
-| GoodTop | GT-ST018M        | Yes   | SWTG018AS-A V2.0 | 2MB             | 8273N + 8224N |
-| MokerLink | 2G08110GSN     | No    | SWTG018AS-A V2.0 | 512KB(25Q40)    | 8273N + 8224N |
+| Ampcom  | PCB-SWTG018AS-A V2.0.1_19649 | No    | PCB-SWTG018AS-A V2.0.1_19649 | 2MB             | 8273N + 8224N |
+| Horaco  | HC-MOKERLINK_ZX_SWTGW218AS-A  | Yes   | PCB-SWTG018AS-A V2.0.1_19649 | 2MB(25Q16JVSIQ) | 8273N + 8224N |
+| GoodTop | GT-ST018M        | Yes   | PCB-SWTG018AS-A V2.0.1_19649 | 2MB             | 8273N + 8224N |
+| MokerLink | MOKERLINK_2G08110GSN     | No    | PCB-SWTG018AS-A V2.0.1_19649 | 512KB(25Q40)    | 8273N + 8224N |
 
 
-The following is a documentation for the unmanaged switch marked as `SWTG018AS-A V2.0`.
+The following is a documentation for the unmanaged switch marked as `PCB-SWTG018AS-A V2.0.1_19649`.
 It is e.g. sold under the Ampcom brand, but no branh-markings are found on the device.
 
 The original software is running UART on 9600 baud rate. 
@@ -26,7 +26,7 @@ These can be programed independently by using said switch - so it is e.g. possib
   - 1 × SFP+: 1000 / 2500 / 10000 Mbps
 - **Power**: 12V DC, 1A barrel connector 
 
-<img src="photos/SWTG018AS_A_V_2_0/label.jpg" width="300" />
+<img src="photos/PCB-SWTG018AS-A-V2.0.1_19649/label.jpg" width="300" />
 
 ### What works
 The device is fully supported:
@@ -41,11 +41,11 @@ The device is fully supported:
 
 Top side
 
-<img src="photos/SWTG018AS_A_V_2_0/pcb_top.jpg" width="300" />
+<img src="photos/PCB-SWTG018AS-A-V2.0.1_19649/pcb_top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/SWTG018AS_A_V_2_0/pcb_bottom.jpg" width="300" />
+<img src="photos/PCB-SWTG018AS-A-V2.0.1_19649/pcb_bottom.jpg" width="300" />
 
 ### J1, serial console
 

doc/devices/PCB-SWTG024AS-A-V2.0.1_19650-HORACO.md

@@ -1,5 +1,5 @@
 ### SWTG024AS-A-V2.0.1_5C_1SFP
-It is highly similar to SWTG024AS-V2.0, with the only difference being the GPIO configuration for the SFP port.
+It is highly similar to PCB-SWTG024AS-V2.0_16895, with the only difference being the GPIO configuration for the SFP port.
 
 ## Brands
 |Brand|Type|Managed|PCB|Flash|Chip RTL|

doc/devices/PCB-SWTG024AS-A-V2.0.1_19650.md

@@ -1,12 +1,12 @@
 ### SWTG024AS-A-V2.0.1_4C_2SFP
-It is highly similar to SWTG024AS-V2.0, with the only difference being the GPIO configuration for the SFP port.
+It is highly similar to PCB-SWTG024AS-V2.0_16895, with the only difference being the GPIO configuration for the SFP port.
 
 ## Brands
 |Brand    |Type          |Managed|PCB                           |Flash           |Chip RTL|
 |---------|--------------|-------|------------------------------|----------------|--------|
 | Horaco  | ZX-SG4T2     | No    | PCB-SWTG024AS-A-V2.0.1_19650 | 512K (P25D40SH)| 8372N  |
 | Horaco  | HC-SWTG124AS | Yes   | PCB-SWTG024AS-A-V2.0.1_19650 | 2M   (W25Q16JV)| 8372N  |
-| GoodTop | GT-ST024M    | Yes   | PCB-SWTG024AS-A-V2.0.1       | 2M             | 8372N  |
+| GoodTop | GT-ST024M    | Yes   | PCB-SWTG024AS-A-V2.0.1_19650 | 2M             | 8372N  |
 
 ### Label specifications
 
@@ -15,7 +15,7 @@ It is highly similar to SWTG024AS-V2.0, with the only difference being the GPIO
   - 4 × RJ45: 10/100/1000/2500 Mbps
   - 2 × SFP+: 1000 / 2500 / 10000 Mbps
 
-<img src="photos/SWTG024AS-A-V2_0_1_19650/horaco-zx-sg4t2-label.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-A-V2.0.1_19650/horaco-zx-sg4t2-label.jpg" width="300" />
 
 ### What works
 The device is fully supported:
@@ -29,11 +29,11 @@ The device is fully supported:
 
 Top side
 
-<img src="photos/SWTG024AS-A-V2_0_1_19650/horaco-zx-sg4t2-pcb-top.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-A-V2.0.1_19650/horaco-zx-sg4t2-pcb-top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/SWTG024AS-A-V2_0_1_19650/horaco-zx-sg4t2-pcb-bottom.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-A-V2.0.1_19650/horaco-zx-sg4t2-pcb-bottom.jpg" width="300" />
 
 On Horaco HC-SWTG124AS with board PCB-SWTG024AS-A-V2.0.1_19650 the reset button is soldered at `SW1` (on the top left, GPIO48).
 

doc/devices/PCB-SWTG024AS-V2.0-17452.md

@@ -8,14 +8,14 @@ Also the RJ45 connectors can be all plastic/non-shielded or with metal shielding
 ## Brands
 |Brand|Type|Managed|PCB|PCB Label|Flash|Chip RTL|
 |---|---|---|---|---|---|---|
-| LIANGUO |SWTG024AS |No|  SWTG024AS-v2.0-17452 | CM-23-11-2336 023-17453| 512 KiB | 8272 |
-| Horaco |ZX-SWTG124AS | Yes |  SWTG024AS-v2.0 | ??? | ??? | 8272 |
-| Xikestore |SKS3200M-4GPY2XF | Yes |  SWTG024AS-v1.0 | CM-23-08-2043 023-16721 | 2048 KiB | 8272 |
-| Sodola | SL-SWTG124AS-D | Yes | SWTG024AS-v2.0-17452 | ??? | 2048 KiB | 8272 |
+| LIANGUO |SWTG024AS |No| PCB-SWTG024AS-V2.0-17452 | CM-23-11-2336 023-17453| 512 KiB | 8272 |
+| Horaco |ZX-SWTG124AS | Yes | PCB-SWTG024AS-V2.0-17452 | ??? | ??? | 8272 |
+| Xikestore |SKS3200M-4GPY2XF | Yes | PCB-SWTG024AS-V2.0-17452 | CM-23-08-2043 023-16721 | 2048 KiB | 8272 |
+| Sodola | SL-SWTG124AS-D | Yes | PCB-SWTG024AS-V2.0-17452 | ??? | 2048 KiB | 8272 |
 
 ## PCB
 
-<img src="photos/SWTG024AS-v2.0-unmanaged/SWTG024AS-v2.0-top-uman.png" width="300" />
+<img src="photos/PCB-SWTG024AS-V2.0-17452/SWTG024AS-v2.0-top-uman.png" width="300" />
 
 # SWTG024AS-v2.0 managed vs unmanged
 Changes I found with my board vs [Managed version](https://github.com/up-n-atom/SWTG118AS/tree/main/photos/SWGT024AS-v2.0) of the PCB.

doc/devices/PCB-SWTG024AS-V2.0_16895.md

@@ -1,4 +1,4 @@
-### SWTG024AS-V2.0
+### PCB-SWTG024AS-V2.0_16895
 
 ## Brands
 |Brand|Type|Managed|PCB|Flash|Chip RTL|
@@ -13,7 +13,7 @@
   - 1 × SFP+: 1000 / 2500 / 10000 Mbps
 - **Power**: 12V DC, 1A  5525 connector 
 
-<img src="photos/SWTG024AS-V2.0/label.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-V2.0_16895/label.jpg" width="300" />
 
 ### What works
 The device is fully supported:
@@ -24,15 +24,15 @@ The device is fully supported:
 ### PCB overview
 
 **Board markings**
-- Top silkscreen: PCB-SWTG024AS-V2.0
+- Top silkscreen: PCB-SWTG024AS-V2.0_16895
 
 Top side
 
-<img src="photos/SWTG024AS-V2.0/pcb_top.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-V2.0_16895/pcb_top.jpg" width="300" />
 
 Bottom
 
-<img src="photos/SWTG024AS-V2.0/pcb_bottom.jpg" width="300" />
+<img src="photos/PCB-SWTG024AS-V2.0_16895/pcb_bottom.jpg" width="300" />
 
 ### J1, serial console
 

doc/devices/PCB-SWTG024AS-V2.1.0_19023.md

@@ -0,0 +1,48 @@
+### SWTG024AS-V2.1
+
+## Brands
+|Brand|Type|Managed|PCB|Flash|Chip RTL|
+|---|---|---|---|---|---|
+| Xikestor | SKS3200-4E2X    | Yes | PCB-SWTG024AS-V2.1.0_19023 | 25Q16A | 8372N |
+| Solola   | SL902-SWTG024AS | Yes | PCB-SWTG024AS-V2.1.0_19023 |        | 8372N |
+
+### Label specifications
+
+- **Ports**:
+  - 4 × RJ45: 10/100/1000/2500 Mbps
+  - 2 × SFP+: 1000/2500/10000 Mbps
+- **Power**: 1A @ 12V DC
+
+#### Xikestore SKS-3200-4E2X label
+<img src="photos/PCB-SWTG024AS-V2.1.0_19023/label.jpg" width="300" />
+
+### What works
+- ALL 2.5GBASE-T RJ45 ports work at 10/100/1000/2500 Mbps
+- The SFP+ ports supports 1G, 2.5G and 10G modules.
+- LEDs work with the same indiciations as the OEM firmware.
+
+### PCB overview
+
+**Board markings**
+- Top silkscreen: PCB-SWTG024AS-V2.1.0_19023
+
+Top side
+
+<img src="photos/PCB-SWTG024AS-V2.1.0_19023/pcb-top.jpg" width="300" />
+
+Bottom
+
+<img src="photos/PCB-SWTG024AS-V2.1.0_19023/pcb-bottom.jpg" width="300" />
+
+### Serial console
+
+The four-pin through-hole serial header can be seen to the right of the CPU heatsink in the photo above. It is labelled J1, with pin 1 (Indicated by a triangle on the silkscren) at the bottom. the pinout is also on the silkscreen:
+
+| Pin | Label  |
+|-----|--------|
+| 1   | TX     |
+| 2   | RX     |
+| 3   | GND    |
+| 4   | 3V3    |
+
+Adding a header is a few moments work with a soldering iron. Only pins 1-3 are required for serial port use, and the stock firmware outputs at 57600bps at boot.

doc/devices/PCB-SWTG115AS-V2.0-16030.md

@@ -6,6 +6,7 @@
 |---|---|---|---|---|---|
 | Lianguo | ZX-SWTGW215AS | Yes | PCB-SWTG115AS-V2.0 | FM25Q16A | 8372 |
 | sold as Lianguo, actual device unbranded | ZX-SWTGW215AS | Yes | PCB-SWTG115AS-V2.1 | W25Q16JVSIQ (2MiB) | 8372 |
+| Sodola | SL-SWTGW215AS-D | Yes | SWTG115AS-V2.1-17433 | W25Q16JVSIQ (2MiB) | 8372 |
 
 ## RTLPlayground target
 
@@ -16,17 +17,17 @@ Port 5 RJ45 is interfaced through a RTL8221B IC.
 
 ## Label (V2.0)
 
-<img src="photos/ZX-SWTGW215AS-V2.0/label.jpg" width="300" />
+<img src="photos/PCB-SWTG115AS-V2.0-16030/label.jpg" width="300" />
 
 ## PCB (V2.0)
 
-<img src="photos/ZX-SWTGW215AS-V2.0/pcb_top.jpg" width="300" />
-<img src="photos/ZX-SWTGW215AS-V2.0/pcb_bottom.jpg" width="300" />
+<img src="photos/PCB-SWTG115AS-V2.0-16030/pcb_top.jpg" width="300" />
+<img src="photos/PCB-SWTG115AS-V2.0-16030/pcb_bottom.jpg" width="300" />
 
 ## PCB (V2.1)
 
-<img src="photos/ZX-SWTGW215AS-V2.1/pcb-top.jpg" width="300" />
-<img src="photos/ZX-SWTGW215AS-V2.1/pcb-bottom.jpg" width="300" />
+<img src="photos/PCB-SWTG115AS-V2.1-17443/pcb-top.jpg" width="300" />
+<img src="photos/PCB-SWTG115AS-V2.1-17443/pcb-bottom.jpg" width="300" />
 
 ## Connectors
 
@@ -68,7 +69,7 @@ Port 5 RJ45 is interfaced through a RTL8221B IC.
 
 This connector goes to U4 `I2C EEPROM` and U10 `SPI FLASH` (mappings identical to SWTG024AS).
 
-For detailed Slave Interface functionality and protocol information, see [T3 documentation in SWTG024AS.md](SWTG024AS.md#t3-slave-interface).
+For detailed Slave Interface functionality and protocol information, see [T3 documentation in SWTG024AS.md](PCB-SWTG024AS-V2.0-17452.md#t3-slave-interface).
 
 |`T3` pin|what|Signal|
 |---|---|---|
@@ -108,7 +109,7 @@ For detailed Slave Interface functionality and protocol information, see [T3 doc
 
 #### Notes
 * 1 pin is square shaped.
-* Mapping unverified but assumed the same as [LIANGUO SWTG024AS](SWTG024AS.md#t8).
+* Mapping unverified but assumed the same as [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#t8).
 
 ## Reset Circuit
 | Function | GPIO |
@@ -120,7 +121,7 @@ For detailed Slave Interface functionality and protocol information, see [T3 doc
 
 ## GPIO
 
-Note: T3/U4/U10-related signal annotations below are copied from [LIANGUO SWTG024AS T3 section](SWTG024AS.md#t3-slave-interface) as well as T8 port from [LIANGUO SWTG024AS T8 section](SWTG024AS.md#t8). They should be treated as assumed identical for ZX-SWTGW215AS as it has not been 100% confirmed true at the moment. 
+Note: T3/U4/U10-related signal annotations below are copied from [LIANGUO SWTG024AS T3 section](PCB-SWTG024AS-V2.0-17452.md#t3-slave-interface) as well as T8 port from [LIANGUO SWTG024AS T8 section](PCB-SWTG024AS-V2.0-17452.md#t8). They should be treated as assumed identical for ZX-SWTGW215AS as it has not been 100% confirmed true at the moment. 
 
 | HEX VAL. | GPIO   | Component / Purpose | Notes |  | GPIO | Component / Purpose | Notes |
 | -------- | ------ |  ---- | ---- | ---- | ---- | ---- | ---- |
@@ -134,14 +135,14 @@ Note: T3/U4/U10-related signal annotations below are copied from [LIANGUO SWTG02
 | 00000080 | GPIO07 | | |  | GPIO39 | J4-4 | SFP I2C SDA |
 | 00000100 | GPIO08 | | |  | GPIO40 | J4-5 | SFP I2C SCL |
 | 00000200 | GPIO09 | | |  | GPIO41 |   |  |
-| 00000400 | GPIO10 | | |  | GPIO42 | U10-P6, U4-P6, T3-1 | SPI FLASH CLK / I2C-SCL (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00000800 | GPIO11 | | |  | GPIO43 | U10-P5, U4-P5, T3-3 | SPI FLASH DI/IO0 / I2C-SDA (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00001000 | GPIO12 | | |  | GPIO44 | U10-P2, T3-5 | SPI FLASH DO/IO1 (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00002000 | GPIO13 | PORT1 LED GREEN |  |  | GPIO45 | U10-P1, T3-6 | SPI FLASH CS (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00004000 | GPIO14 | PORT1 LED ORANGE |  |  | GPIO46 | T8-1 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00008000 | GPIO15 | | |  | GPIO47 | T8-5 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00010000 | GPIO16 | PORT2 LED GREEN |  |  | GPIO48 | T8-3 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
-| 00020000 | GPIO17 | PORT2 LED ORANGE |  |  | GPIO49 | T8-6 | (from [LIANGUO SWTG024AS](SWTG024AS.md#gpio)) |
+| 00000400 | GPIO10 | | |  | GPIO42 | U10-P6, U4-P6, T3-1 | SPI FLASH CLK / I2C-SCL (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00000800 | GPIO11 | | |  | GPIO43 | U10-P5, U4-P5, T3-3 | SPI FLASH DI/IO0 / I2C-SDA (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00001000 | GPIO12 | | |  | GPIO44 | U10-P2, T3-5 | SPI FLASH DO/IO1 (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00002000 | GPIO13 | PORT1 LED GREEN |  |  | GPIO45 | U10-P1, T3-6 | SPI FLASH CS (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00004000 | GPIO14 | PORT1 LED ORANGE |  |  | GPIO46 | T8-1 | (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00008000 | GPIO15 | | |  | GPIO47 | T8-5 | (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00010000 | GPIO16 | PORT2 LED GREEN |  |  | GPIO48 | T8-3 | (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
+| 00020000 | GPIO17 | PORT2 LED ORANGE |  |  | GPIO49 | T8-6 | (from [LIANGUO SWTG024AS](PCB-SWTG024AS-V2.0-17452.md#gpio)) |
 | 00040000 | GPIO18 | PORT3 LED GREEN |  |  | GPIO50 |   |  |
 | 00080000 | GPIO19 | PORT3 LED ORANGE |  |  | GPIO51 |   |  |
 | 00100000 | GPIO20 | PORT4 LED GREEN |  |  | GPIO52 |   |  |
@@ -176,7 +177,7 @@ Note: T3/U4/U10-related signal annotations below are copied from [LIANGUO SWTG02
 
 ## Notes
 
-While [SWTG024AS.md](SWTG024AS.md) can be used as a general reference for hardware concepts and interface specifications, this device should not be assumed to be identical beside the difference implicitely highlighted below. Not all information has been validated for compatibility with the SWTG215AS. Consult the SWTG024AS documentation with caution and verify any critical details against this device's.
+While [SWTG024AS.md](PCB-SWTG024AS-V2.0-17452.md) can be used as a general reference for hardware concepts and interface specifications, this device should not be assumed to be identical beside the difference implicitely highlighted below. Not all information has been validated for compatibility with the SWTG215AS. Consult the SWTG024AS documentation with caution and verify any critical details against this device's.
 
 ## Flashing
 

doc/devices/PCB-SWTG115AS-V2.1-17443.md

@@ -0,0 +1 @@
+PCB-SWTG115AS-V2.0-16030.md

doc/devices/PCB-SWTG118AS-V2.0-16029.md

@@ -0,0 +1,31 @@
+### ZX-MOKERLINK_ZX_SWTGW218AS
+
+## Brands
+|Brand|Type|Managed|PCB|Flash|Chip RTL|
+|---|---|---|---|---|---|
+| Mokerlink | ZX-MOKERLINK_ZX_SWTGW218AS | Yes|  PCB-SWTG118AS-V2.0-16029 | 2MB (FM25Q16A)| 8273N + 8224N |
+| Sodola | | | | | |
+| Horaco | HC-MOKERLINK_ZX_SWTGW218AS | Yes | SWTG118AS-V2.1 | 2MB | 8373 (non-N) |
+| XikeStor | SKS3200-8E1X | Yes | SWTG118AS-V2.1-17462 | 2MB (25Q16JVSIQ) | |
+
+All boards in this table use `MACHINE=MOKERLINK_ZX_SWTGW218AS`. The Horaco HC-MOKERLINK_ZX_SWTGW218AS is also sold with the
+[PCB-SWTG018AS-A V2.0.1_19649](PCB-SWTG018AS-A-V2.0.1_19649.md) board, which needs a different firmware. Check the marking
+on the PCB before flashing.
+
+The PHY and flash-chip models for the tested Horaco units remain unverified.
+
+
+## Photos
+
+<img src="photos/PCB-SWTG118AS-V2.0-16029/front.png" width="800" />
+
+<img src="photos/PCB-SWTG118AS-V2.0-16029/label.jpg" width="800" />
+
+## PCB
+
+See up'n'atom's Repo:
+
+https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-top.JPG
+
+https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-bottom.JPG
+

doc/devices/S1100P-8GT-1SX-73N-S-V1.01.md

@@ -1,4 +1,4 @@
-# Hasivo S1100P-8GT-1SX-S
+# Hasivo S1100P-8GT-1SX-73N-S-V1.01
 
 RTL8373N switch with 8 × 2.5G RJ45 ports and 1 × SFP port. GD25Q16 2 MiB flash.
 
@@ -29,13 +29,13 @@ PoE is managed by an RTL8238B and a separate STC8H8K64U controller, not directly
 
 Front panel:
 
-![Front panel](photos/Hasivo-S1100P-8GT-1SX-S/front.jpg)
+![Front panel](photos/S1100P-8GT-1SX-73N-S-V1.01/front.jpg)
 
 PCB top:
 
-![PCB top](photos/Hasivo-S1100P-8GT-1SX-S/pcb_top.jpg)
+![PCB top](photos/S1100P-8GT-1SX-73N-S-V1.01/pcb_top.jpg)
 
 PCB bottom:
 
-![PCB bottom](photos/Hasivo-S1100P-8GT-1SX-S/pcb_bottom.jpg)
+![PCB bottom](photos/S1100P-8GT-1SX-73N-S-V1.01/pcb_bottom.jpg)
 

doc/devices/S1100W-8GT-1SX_SE-V1.05.md

@@ -22,21 +22,21 @@ RTL8373-based 8×2.5G PoE + 1×SFP switch.
 
 Front panel:
 
-<img src="photos/HASIVO_S1100WP-8GT-1SX-SE/front.jpg" width="600" />
+<img src="photos/S1100W-8GT-1SX_SE-V1.05/front.jpg" width="600" />
 
 Label:
 
-<img src="photos/HASIVO_S1100WP-8GT-1SX-SE/label.jpg" width="600" />
+<img src="photos/S1100W-8GT-1SX_SE-V1.05/label.jpg" width="600" />
 
 ### PCB overview
 
 Top side:
 
-<img src="photos/HASIVO_S1100WP-8GT-1SX-SE/pcb_top.jpg" width="600" />
+<img src="photos/S1100W-8GT-1SX_SE-V1.05/pcb_top.jpg" width="600" />
 
 Bottom side:
 
-<img src="photos/HASIVO_S1100WP-8GT-1SX-SE/pcb_bottom.jpg" width="600" />
+<img src="photos/S1100W-8GT-1SX_SE-V1.05/pcb_bottom.jpg" width="600" />
 
 ### Port layout
 

doc/devices/S25G1109FP-V1.3.md

@@ -0,0 +1,148 @@
+# Sirivision SR-S25G2109F (S25G1109FP V1.3)
+
+RTL8373 (non-N) with an RTL8224 quad 2.5G PHY: 8 × 2.5G RJ45 + 1 × SFP+,
+2 MB flash, no PoE.
+
+## Label specifications
+
+| Item | Value |
+|------|-------|
+| Manufacturer | Sirivision |
+| Model | SR-S25G2109F |
+| Ports | 8 × RJ45 10/100/1000/2500 Mbps, 1 × SFP+ 1G/2.5G/10G |
+| Power input | 12 V DC, 1.5 A |
+| Stock firmware | version 1.0.8.0 |
+| Stock defaults | IP 192.168.1.199, user `admin`, password `admin` |
+| Serial number | 001008130002003A000005 (also on the PCB barcode sticker) |
+
+The label does not carry a MAC address.  After a factory initialisation the
+stock firmware uses exactly the values printed on the label.
+
+## PCB silkscreen and naming
+
+Top side: `S25G1109FP V1.3 SIRIVISION`.  That model name belongs to an unmanaged
+PoE switch; this board omits the PoE section entirely.  What is actually shipped
+is the label model `SR-S25G2109F`: a simply managed, non-PoE switch.  Its stock
+firmware provides a web interface, but it responds very slowly.
+
+## CPU, PHY and flash
+
+| Part | Identification |
+|------|----------------|
+| SoC | RTL8373, non-N: `regget 4` returns `0x83730000` and the boot console prints `Detecting CPU: RTL8373` |
+| PHY | RTL8224, reported as `RTL8224 ID: 0x82240000` |
+| Flash | GigaDevice 25Q16ESIG (U7), 2 MB, JEDEC id `c8 40 15` |
+
+The two large ICs sit under soldered heatsinks, their markings are not readable.
+
+## Build
+
+```
+make MACHINE=SIRIVISION_SR_S25G2109F CI=1
+```
+
+The resulting image can be uploaded through the web interface (`System` page)
+or the stock web UI.
+
+## Port mapping
+
+| Front port | ASIC MAC | Interface |
+|------------|----------|-----------|
+| 1–8 | 0–7 | RJ45 2.5G |
+| 9 | 8 | SFP+ (SDS1) |
+
+## Board signals
+
+| Function | GPIO |
+|----------|------|
+| SFP detect (ModAbs) | 30, low with a module inserted |
+| SFP LOS | 37, high without light |
+| SFP TX disable | not connected, `GPIO_NA` |
+| SFP I2C | SDA 39 / SCL 40, `I2CBUS(GPIO39_I2C_SDA4, GPIO40_I2C_SCL3_MDC1)` |
+| Reset button | 54 |
+
+ModAbs and LOS are separate signals here: GPIO30 tells whether a module is
+inserted, GPIO37 whether it receives light, so a module is identified even
+before the link comes up and loss of signal is reported.  GPIO38 and GPIO48,
+which the 8+1 reference boards use for ModAbs and for the reset button, never
+change on this board; with GPIO38 as ModAbs the firmware believed a module was
+permanently present and retried the I2C read forever.
+
+Serial console: the stock firmware runs the loader at 57600 baud and the runtime
+at 9600 baud, RTLPlayground uses 115200.
+
+## Front panel
+
+Each copper port has two LEDs, labelled `Link/Act` (left, yellow) and `2.5G`
+(right, green).  The SFP cage has a single green `Link/Act` LED; next to it are
+a `Power` LED and the `Reset` button.
+
+## LED configuration
+
+Copper ports use LED set 0, the SFP port uses LED set 1:
+
+| Set | Function 0 (left / SFP) | Function 1 (right) |
+|-----|-------------------------|--------------------|
+| SET0 | all speeds, link with activity | 2.5G link |
+| SET1 | all speeds, link with activity | not populated |
+
+The board is wired in the stock port order — LED pin `3n+m` belongs to port
+`n+1`, LED function `m` — so the mux table is the chip default with a single
+change: the SFP LED sits on pin 25 and is driven by LED function 0, while the
+default table maps pin 25 to function 1, which is unpopulated in SET1.  Without
+that change the SFP LED stays dark.
+
+A speed condition alone leaves an LED dark, `LEDS_LINK` has to be set as well.
+
+## Reset button
+
+| Hold time while running | Effect |
+|-------------------------|--------|
+| less than 3 s | no action |
+| 3–10 s | reset the switch chip, the firmware reboots (~20 s of downtime) |
+| more than 10 s | additionally restore the default configuration |
+
+The system LED blinks slowly while the button is held.  Holding the button
+during power-up instead waits for the release and restores the default
+configuration when it is released after 10–30 s.
+
+## MAC address
+
+The factory MAC sits at `0x1FC000`, six bytes followed by `0xFF` padding.  The
+stock value is a locally administered address (`1A:5D:23:47:4D:EB`), which the
+firmware rejects, so the device runs with a UUID-derived MAC (`06:…`).  A valid
+globally administered address stored there is used instead.
+
+## What works
+
+- all eight 2.5GBASE-T ports at 10/100/1000/2500 Mbps
+- SFP+ with 10G and 1G modules, including DDM data where the module provides it
+  - 10G: Finisar FCBG110SD1C05 AOC (no DDM), rate `0x67`, SerDes mode `1a`
+  - 1G: ETU ESB5312-3SCD20 (DDM), rate `0x0d`, SerDes mode `04`
+- LEDs, module insert/remove detection, loss of signal reporting, reset button
+
+## Unverified
+
+- 2.5G SFP modules, none was available for testing
+
+## Photos
+
+Front panel:
+
+![Front panel](photos/S25G1109FP-V1.3/front.jpg)
+
+Label:
+
+![Label](photos/S25G1109FP-V1.3/label.jpg)
+
+PCB top side:
+
+![PCB top side](photos/S25G1109FP-V1.3/pcb_top.jpg)
+
+PCB bottom side:
+
+![PCB bottom side](photos/S25G1109FP-V1.3/pcb_bottom.jpg)
+
+Flash chip, GigaDevice 25Q16ESIG:
+
+![Flash chip](photos/S25G1109FP-V1.3/flash.jpg)

doc/devices/S25G2206FP-V1.1.md

@@ -25,7 +25,7 @@ The device is fully supported:
 
 Top side
 
-<img src="photos/SIRIVISION_S25G2206FP_V1_1/dev_pcb_top.jpg" width="300" />
+<img src="photos/S25G2206FP-V1.1/dev_pcb_top.jpg" width="300" />
 
 ## Power supply
 

doc/devices/SWTGW218AS.md

@@ -1,31 +0,0 @@
-### ZX-SWTGW218AS
-
-## Brands
-|Brand|Type|Managed|PCB|Flash|Chip RTL|
-|---|---|---|---|---|---|
-| Mokerlink | ZX-SWTGW218AS | Yes|  SWTG118AS-V2.0-16029 | 2MB (FM25Q16A)| 8273N + 8224N |
-| Sodola | | | | | |
-| Horaco | HC-SWTGW218AS | Yes | SWTG118AS-V2.1 | 2MB | 8373 (non-N) |
-| XikeStor | SKS3200-8E1X | Yes | SWTG118AS-V2.1-17462 | 2MB (25Q16JVSIQ) | |
-
-All boards in this table use `MACHINE=SWTGW218AS`. The Horaco HC-SWTGW218AS is also sold with the
-[SWTG018AS-A V2.0](SWTG018AS_A_V2_0.md) board, which needs a different firmware. Check the marking
-on the PCB before flashing.
-
-The PHY and flash-chip models for the tested Horaco units remain unverified.
-
-
-## Photos
-
-<img src="photos/SWTGW218AS-managed/front.png" width="800" />
-
-<img src="photos/SWTGW218AS-managed/label.jpg" width="800" />
-
-## PCB
-
-See up'n'atom's Repo:
-
-https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-top.JPG
-
-https://github.com/up-n-atom/SWTG118AS/blob/main/photos/SWTG118AS-v2.0/SWTG118AS-v2.0-pcb-bottom.JPG
-