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Author SHA1 Message Date
René van Dorst cc132a8734 phy_write(): also use SFR_DATA_U16 and SFR_SMI_REG_U16 
Was added by pr#7.
 2025-09-01 09:59:41 +02:00
René van Dorst 689d208ff1 phy: fix whitespace and comments alinement 2025-09-01 09:59:06 +02:00
René van Dorst d865862625 phy: fix or/and-opperation conversion errors 2025-09-01 09:27:28 +02:00
René van Dorst 94cf079fcb PHY: also use SFR_DATA_U16. 
Again less error prone and easier to read.

Also see a lot of better optimalizations.
A snipped.

390c390
< ;pval          Allocated to registers r3 r4
---
> ;pval          Allocated to registers
838,852c838,844
< ;     rtl837x_phy.c:181: pval = SFR_DATA_8 & 0xbf;
<       mov     r7,_SFR_DATA_8
<       anl     ar7,#0xbf
< ;     rtl837x_phy.c:182: pval <<= 8;
<       mov     ar4,r7
<       mov     r7,#0x00
< ;     rtl837x_phy.c:183: pval |= SFR_DATA_0;
<       mov     r2,_SFR_DATA_0
<       mov     r3,#0x00
<       mov     a,r2
<       orl     a,r7
<       mov     _phy_write_PARM_4,a
<       mov     a,r3
<       orl     a,r4
<       mov     (_phy_write_PARM_4 + 1),a
---
> ;     rtl837x_phy.c:181: pval = SFR_DATA_U16 & 0xbfff;
>       mov     r4,((_SFR_DATA_U16 >> 0) & 0xFF)
>       mov     a,#0xbf
>       anl     a,((_SFR_DATA_U16 >> 8) & 0xFF)
>       mov     r7,a
>       mov     _phy_write_PARM_4,r4
>       mov     (_phy_write_PARM_4 + 1),r7
864c856
<       mov     _phy_write_PARM_3,r7
---
>       mov     _phy_write_PARM_3,#0x00
 2025-09-01 09:25:33 +02:00
René van Dorst b8928a8bcd Replace manual SFR_DATA_0 and SFR_DATA_8 pair read and write with SFR_DATA_U16. 
Also added SFR_SMI_REG_U16.

Doing pval = reg_h; pval <<= 8; pval |= reg_l; dont always optimized by the compiler a some places, not all.

A snipped of the diff between two .asm files.

5414,5424c5414,5416
< ;     rtlplayground.c:1382: uint16_t pval = SFR_DATA_8;
< ;     rtlplayground.c:1383: pval <<= 8;
<       mov     r7,_SFR_DATA_8
<       mov     r6,#0x00
< ;     rtlplayground.c:1384: pval |= SFR_DATA_0;
<       mov     r4,_SFR_DATA_0
<       mov     r5,#0x00
<       mov     a,r6
<       orl     ar4,a
<       mov     a,r7
<       orl     ar5,a
---
> ;     rtlplayground.c:1382: uint16_t pval = SFR_DATA_U16;
>       mov     r6,((_SFR_DATA_U16 >> 0) & 0xFF)
>       mov     r7,((_SFR_DATA_U16 >> 8) & 0xFF)
 2025-09-01 09:20:36 +02:00
René van Dorst 9dafeab490 Added SFR_NIC_DATA_U16LE and SFR_NIC_RING_U16LE. 
Let's use sfr16 for NIC data and ring.
SFR define can so reordered to it does the BE to LE swap for us.
 2025-09-01 09:20:36 +02:00
René van Dorst af0135bcce Add sfr16 SFR_REG_ADDR_U16. 
So instead do it manual split a uint16_t in to two uint8_t.
The compiler can do it, so reduces user error.
Note: compiler writes the lower/LSB part first.
      When that is importent this can´t be used.

Assembly is still the same except note above.
 2025-09-01 09:20:36 +02:00
logicog 250beae09b Merge pull request #7 from vDorst/phy_write_main 
bit_mask lookup before calling phy_write() is expensive.
 2025-09-01 08:10:21 +02:00
logicog a939e2e92b Fix protocol structure and filling 2025-09-01 07:45:33 +02:00
René van Dorst 7ff028303d Add phy_write() with bit_mask lookup inside the function. 
Move the lookup saves a lot of instructions for every phy_write() call.

Assembly diff for one change.
< ;     rtl837x_phy.c:240: phy_write_mask(bit_mask[port], 0x07, 0x00, 0x3200);  // Enable AN
<       mov     dpl,r5
<       mov     dph,r6
---
> ;     rtl837x_phy.c:240: phy_write(port, 0x07, 0x00, 0x3200); // Enable AN
>       mov     _phy_write_PARM_2,#0x07
1345,1359c1019,1024
<       movc    a,@a+dptr
<       mov     r5,a
<       inc     dptr
<       clr     a
<       movc    a,@a+dptr
<       mov     r6,a
<       mov     _phy_write_mask_PARM_2,#0x07
<       clr     a
<       mov     _phy_write_mask_PARM_3,a
<       mov     (_phy_write_mask_PARM_3 + 1),a
<       mov     _phy_write_mask_PARM_4,a
<       mov     (_phy_write_mask_PARM_4 + 1),#0x32
<       mov     dpl, r5
<       mov     dph, r6
<       lcall   _phy_write_mask
---
>       mov     _phy_write_PARM_3,a
>       mov     (_phy_write_PARM_3 + 1),a
>       mov     _phy_write_PARM_4,a
>       mov     (_phy_write_PARM_4 + 1),#0x32
>       mov     dpl, r7
>       lcall   _phy_write

Replace all phy_write_mask(bit_mask[<var>], ...) to phy phy_write(<var>, ...).
 2025-09-01 00:12:12 +02:00
René van Dorst d6ea9be4c0 rename phy_write() to phy_write_mask(). 
It seems that bit_mask[phy] lookup is expensive and it used in many places.
But most of the time we only addressing a single phy.
 2025-09-01 00:07:27 +02:00
logicog e499007666 Merge pull request #5 from vDorst/compfix1 
fix: comp. warning 283: function declarator with no prototype.
 2025-08-31 17:54:13 +02:00
René van Dorst 3d80f73383 fix: comp. warning 283: function declarator with no prototype. 2025-08-30 22:51:19 +02:00
logicog 546d385bf1 Add RLDP setup 2025-08-30 18:44:17 +02:00
logicog 829fbf707a Use uip for mac-address, enable STP packages 2025-08-30 18:43:31 +02:00
logicog 326d94f48d Add support for STP 2025-08-30 18:42:46 +02:00
logicog 83dcd22863 Add STP packet identification 2025-08-30 08:29:25 +02:00
logicog 963d53335c Add initial IGMP handling via ASIC 2025-08-29 17:23:14 +02:00
logicog 739ab5ef40 Cleanup of register definitions 2025-08-29 17:12:58 +02:00
logicog a0239b72f4 Add support for VLAN names 2025-08-28 16:58:51 +02:00
logicog e8c6492786 Reduce IRAM memory footprint 2025-08-28 16:58:51 +02:00
logicog fab02c947e Merge pull request #4 from vDorst/compfix 
http: use python3.
 2025-08-28 07:00:32 +02:00
René van Dorst e859769e5c http: use python3. 
Fix compile issue where system don't have python2.
I get error below.

/bin/sh: line 1: ./treatasm.py: cannot execute: required file not found
make[1]: *** [Makefile:15: httpd.rel] Error 127

Debian has python3 a long time so use it.
See https://wiki.debian.org/Python
 2025-08-27 23:11:12 +02:00
logicog ef742f8f19 Cleanup and fix flushing of L2 UC entries 2025-08-24 19:26:24 +02:00
logicog 81b7e4fa87 Identify pin configuration registers 2025-08-22 09:04:34 +02:00
logicog 0a05fe923e Add port isolation methods 2025-08-22 07:15:49 +02:00
logicog 857a91ffc4 Add support for VLAN configuration via web 2025-08-21 16:13:38 +02:00
logicog ae80aa1017 Add support for different statistic counters 2025-08-21 16:12:59 +02:00
logicog 7968b03c57 Fix inclusion of stdint required by intger types in header 2025-08-21 16:12:09 +02:00
logicog 52f8366d03 Improve command parser to work with other than serial buffer 2025-08-21 16:11:22 +02:00
logicog 8fc4354ec4 Add retrieval of VLAN config and cleanup statisics counters 2025-08-20 10:22:26 +02:00
logicog d7667cb5b4 Cleanup statistic counters 2025-08-20 10:21:41 +02:00
logicog 7b4a95b806 Use nicer function to set clicked ports 2025-08-20 10:20:39 +02:00
logicog 940ee648df Use definition of NSFP in header file 2025-08-20 10:19:07 +02:00
logicog e924431344 Move definition of NSFP to header file 2025-08-20 10:17:15 +02:00
logicog 12b53c22f1 Add simulation tool running on x86 host for web-pages of an RTL8372 switch 2025-08-20 10:16:00 +02:00
logicog 1caadbe631 Fix finding makers for text lengths that are not multiples of 4 2025-08-20 10:14:18 +02:00
logicog 53a8046874 Implement sending of status and VLAN info 2025-08-20 10:13:14 +02:00
logicog 9173d2c6c7 Provide MIME type enums 2025-08-20 10:12:06 +02:00
logicog 942de2d0df Add caching and usage of MIME-type enums 2025-08-20 10:11:31 +02:00
logicog cc55131fed Implement statistics counters 2025-08-20 10:06:14 +02:00
logicog 2241db371f Fix error due to logical ports not being in the same sequence as physical ports 2025-08-20 10:04:54 +02:00
logicog 4a72dfedf2 Add documentation of packet RX and TX control on the ASIC side 2025-08-19 09:56:34 +02:00
logicog c3e0ad52bc Link to VLAN doc updated. Add python as dependency 2025-08-19 09:46:02 +02:00
logicog ad53165351 Introduce identified RX/TX control register names 2025-08-19 09:34:14 +02:00
logicog 74fbec1044 Add logical to physical mapping of ports on RTL8372 2025-08-19 09:31:32 +02:00
logicog acba08d001 Removing old version 2025-08-19 09:30:22 +02:00
logicog 7727c1e561 Add VLAN configuration page 2025-08-19 09:28:00 +02:00
logicog 41b181d9fb Add port statistics page 2025-08-19 09:27:24 +02:00
logicog 72d8f3639c Script to generate port overview dynamically 2025-08-19 09:26:48 +02:00