Commit Graph
105 Commits
Author SHA1 Message Date
feelfree69 9714818b1f Erase flash before writing upload image 2026-05-03 15:55:36 +02:00
René van Dorst 09d90d6d97 Merge pull request #175 from logicog/ZX310S-4T2XH
10GBit Ethernet Switch support (Horaco ZX310S-4T2XH)
2026-05-02 17:22:52 +00:00
logicog 2e0e55967c Do not send SFP info if no SFP port present 2026-04-24 10:53:05 +02:00
feelfree69 f7989cc737 Merge branch 'logicog:main' into syslog 2026-04-21 14:29:44 +02:00
René van Dorst 791f68582d httpd: de-__gptrget()-call in string_to_html() 2026-04-18 22:20:46 +02:00
feelfree69 b31179acbe move extern declaration for port_names to trl837x_common.h 2026-04-13 19:14:24 +02:00
feelfree69 41f0dad49d Add ability to assign a name to a port 2026-04-13 14:55:10 +02:00
feelfree69 c1a414833d Various refactorings 2026-04-12 13:02:42 +02:00
feelfree69 193eacf51b rebase add syslog-addr to web-interface 2026-04-12 13:00:12 +02:00
Jan Hoffmann 6eaa1985aa Fix SFP diagnostic monitoring data in web interface
If the module is not internally calibrated, it is necessary to apply
calibration values to get meaningful results.
2026-03-29 00:33:48 +01:00
Jan Hoffmann 0b4f59483b Don't write SFP options value twice in status JSON 2026-03-29 00:33:48 +01:00
Jan Hoffmann efe0c282ba Fix I2C access code
While the current implementation works for what it is actually used, it
is broken when trying to do larger transfers.

The length field in the control register has a size of 4 bits. In every
transfer, length+1 bytes are read. Thus, each transfer is limited to a
maximum of 16 bytes. Add a check for the length, and write the correct
value to the register.

Also update the loop in "sfp_send_data" to properly increment the output
register. Remove the unused special case for a length of 128 bytes.
2026-03-28 18:14:15 +01:00
logicog d21d269d49 Merge pull request #152 from mmmspatz/mspatz/fix_vlan_page
Fix "Get Configuration" on vlan.html
2026-03-19 11:36:59 +01:00
logicog 59e7a21955 Merge pull request #159 from diijkstra/web_sfp_state
Web: Add SFP state/pin status
2026-03-19 05:22:24 +01:00
logicog 7e3a0f5d8f Allow javascript to modify svg styles for Firefox version >140 2026-03-16 17:32:15 +01:00
diijkstra b47a868db3 Web: Handle missing LOS pin
When device has no LOS pin and module has no extended status, the
RX LOS value will not be shown. When both are present, the equality
check is performed. When only one is present, the present value
will be shown.

json from the switch, will still contain the field, but can be
null for when pin is not available.
2026-03-15 12:18:02 +01:00
diijkstra 1f6e07a1af Web: Add SFP state/pin status
The state of the SFP module is being already send in status.json,
but was not parsed via Web UI. When debuging SFP LOS/Signal detection
it is usefull to see what module is reporting back.

Extended the SFP mouse-over information with:
 - RX LOS as reported in 0x02 bit of register 238
 - External TX Disabled from 0x80 bit of register 238
 - TX fault from 0x04 of the same register
 - The last state of RX LOS pin (available also when there is no 0x40
   option on the module)

This should help identify missing/incorrect setup of TX disabled pin.
2026-03-13 23:56:43 +01:00
feelfree69 fc4b12725c Cleanup Makefile 2026-03-10 21:57:16 +01:00
logicog 7949975191 Add backend support for bandwidth control 2026-03-08 20:55:50 +01:00
Mark H. Spatz 4cef63200f Fix "Get Configuration" on vlan.html
I noticed that entering some vlan config, clicking "Update/Create", then
clicking "Get Configuration" resulted in Tagged/Untagged/PVID displaying
completely wrong data. It looks like the parisng in fetchVLAN() in
vlan.js was just completely disconnected from the layout of the
registers read by vlan_get() in rtl837x_port.c. Who knows how that
happened.

1. Fix fetchVLAN() member/untag parsing: the old code read bits [9:0]
   as untagged and bits [10:19] as tagged, but the VLAN table register
   layout is members in [9:0] and untag in [19:10]. Now correctly
   derives tagged (member && !untag) and untagged (member && untag).

2. Add PVID to vlan.json response: PVID is stored per-port in separate
   PVID registers (RTL837x_PVID_BASE_REG), not in the VLAN table entry.
   The old code nonsensically tried to read it from bits [20:29] of the
   VLAN table. Add port_pvid_get() and build a pvid bitmask in
   send_vlan() so the JS can parse it correctly.

3. Remove auto-PVID logic from setC(): setC() is called by fetchVLAN()
   while it's loading existing config, and so this logic mangled the
   display of the existing config. Also, it doesn't make sense to
   auto-set the PVID for tagged members (PVID relates to untagged
   ingress.)
2026-03-07 15:18:06 -05:00
feelfree69 494320b191 Resolve review comments 2026-03-05 08:55:51 +01:00
feelfree69 7a0f248424 Add flash_size to web interface 2026-02-28 19:56:18 +01:00
feelfree69 ffbd2c512d Check for sifficient flashsize before applying an update 2026-02-25 18:51:00 +01:00
logicog 284b2b003d Merge pull request #127 from feelfree69/resetbutton
Add button handling with the possibility to revert to default settings
2026-02-23 21:01:14 +01:00
feelfree69 e5d23f11de Demagic FLASH_BUF_SIZE 2026-02-15 13:28:31 +01:00
chriz 5d731393f1 Delay reset, to allow TCP reset to be transmitted. 2026-02-14 11:17:42 +01:00
feelfree69 79c9d0deab Add button handling with the possibility to revert to default settings 2026-02-14 10:55:35 +01:00
chriz ea37126e87 New apporach: Make startup config independent. 2026-02-12 14:17:22 +01:00
TylerDurden-23 1d91c1bf2c Merge branch 'logicog:main' into opt-system-settings 2026-02-11 21:15:56 +01:00
TylerDurden-23 7e652f3fb7 Merge branch 'logicog:main' into opt-system-settings 2026-02-11 12:31:00 +01:00
chriz 859a50bd82 fix-link-speed 2026-02-10 23:17:04 +01:00
logicog ea230615f9 Use a MAC address based on the SoC's UUID
We use the SoC's UUID to generate a fixed MAC for a particular
switch device. The MAC generated uses a Realtek prefix and then
is followed by 3 bytes genertaed from the first 3 bytes of the
UUID xored with the last byte in order to prevent being able
to deduce the UUID from the public MAC.
2026-02-08 15:49:49 +01:00
TylerDurden-23 97b46071e0 Merge branch 'logicog:main' into opt-system-settings 2026-02-06 10:50:46 +01:00
diijkstra 48455a57b2 PIN module
Added GPIO defines, moved GPIO MUX initialization to new module.
Converted if/else to switch in GPIO initialization.
2026-02-01 14:32:50 +01:00
diijkstra 7d62b24a42 Advanced I2C pin definition
RTL has up to 3 SCL pins and up to 4 SDA pins. Lets allow configuring
I2C with individual BUS numbers instead of 0/1 I2C.

This enables support for devices where SCL line is not shared between
SFP modules. MUX registry is now initialized depending on needed
pin function.

More over, some SFP pins require special MUX settings, lets initialize
those depending on SFP configuration. This adds TX Disable pin,
which right now is set to low at startup.

Caveats:
 - We may still override MUX registry later
 - Not sure how to handle invalid bus definitions
 - Without SFP is it fine to *not* initialize anything?
 - Do to RAM limitation we do inititalize output GPIO to low
2026-02-01 12:58:16 +01:00
logicog 2c200417b5 Merge pull request #98 from vDorst/fix_soc_init
Fix soc init
2026-01-30 23:29:32 +01:00
chriz 5a11515c36 Improve firefox compatibility. 2026-01-27 14:59:57 +01:00
chriz 5662285a3e Clear command log after saving. 2026-01-26 23:29:23 +01:00
René van Dorst 3d7ef55ced Demagic PHY_MMD31, 0xa412 to PHY_MMD31, PHY_MMD31_GBCR 2026-01-26 22:35:03 +01:00
René van Dorst 44779404df Demagic PHY_MMD_AN, 0x20 to PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL 2026-01-26 22:31:44 +01:00
René van Dorst 1997d7379b Demagic PHY_MMD_AN, 0x10 to PHY_MMD_AN, PHY_ANEG_ADV 2026-01-26 22:28:33 +01:00
chriz b5c249995f Add startup config editor. 2026-01-26 20:40:30 +01:00
René van Dorst 13d0781455 Rename PHY_MMD_CTRL to PHY_MMD31.
So demagic the `phy_(, 0x1f, )` to `phy_(, PHY_MMD31, )`.
2026-01-25 23:38:04 +01:00
feelfree69 0345bf7bf2 Use DIO mode for normal operation; disable DIO before flashing. Use SYS_LED for indicating booting (slow), flashing (fast) and normal operation (on) 2026-01-22 19:38:17 +01:00
feelfree69 8dc914eb07 make fw upload working; nicer debug outputs for console 2026-01-22 08:17:07 +01:00
logicog fd1d14a3e7 Use main directory for includes in httpd 2026-01-18 07:50:38 +01:00
logicog 73a355cff5 Add L2-table access method defintions 2026-01-17 12:56:43 +01:00
logicog e53f5e7134 Add L2 entry deletion support via web 2026-01-17 12:56:43 +01:00
logicog e59158e006 Add backend support for L2 entries in web 2026-01-16 18:04:22 +01:00
logicog 84fe44cc9a Add httpd backend implementation for MIB counter requests 2026-01-15 18:07:56 +01:00