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Author SHA1 Message Date
logicog e73d82ec33 Update Readme 2025-12-29 18:21:16 +01:00
logicog 52832ff299 Merge pull request #56 from vDorst/doc_SWTG024AS_update 
Doc swtg024 as update
 2025-12-27 19:25:43 +01:00
logicog 787a82e846 Create LICENSE 
Adding MIT license as discussed elsewhere
 2025-12-27 07:01:25 +01:00
logicog 3653f90356 Merge pull request #64 from vDorst/fix_systick_calc 
Fix systick 16-bit writing to timer0 registers.
 2025-12-26 10:42:13 +01:00
René van Dorst 9ff114d234 SYSTICK: Fix writing value to TMR0 registers. 
A `%` modulo operator was used instead of a
`&` and-operator, to split a 16 bit value into two
8 bit values.
This causes that the SYSTICKs were 0.1% too fast.

Replace the manual split with a sfr16 type, so the
compiler does the split for us.
 2025-12-26 10:07:13 +01:00
René van Dorst 0abe83e3e5 sfr: add 16 bit SFR for the timer0. 
So we don't have to manual split 16-bit value into
for bytes.
Let the compiler do the work.
 2025-12-26 10:07:11 +01:00
René van Dorst 2a7b8f9838 Merge pull request #59 from logicog/timer_fixes 
Fix internal timer tick counter for housekeeping.
Because of the high F_CPU and low SYS_TICK.
Timer0 can easy overflow.
Now this is known and fixed.
 2025-12-25 09:54:58 +00:00
logicog 7fdf9ca86d Add time command to show system time 2025-12-25 10:27:37 +01:00
logicog 2b364943c2 Fix system clock 2025-12-25 10:27:37 +01:00
René van Dorst a8227f1855 Merge pull request #54 from logicog/speeds 
Add a Port Speed and MTU configuration Web-Page
 2025-12-25 09:11:31 +00:00
logicog 34a0e2d338 Right align speed option selection 2025-12-25 09:46:59 +01:00
logicog 4878a36638 Use changed signatures in parse_port for PHY speed setting 2025-12-25 09:46:59 +01:00
logicog dd7a5ebb95 Merge pull request #62 from vDorst/fix_SWTG024AS_port_mapping 
SWGT024_V2_0: Fix port mapping. Port 2 & 3 were swapped.
 2025-12-24 09:33:19 +01:00
René van Dorst 3ef7e45649 SWGT024_V2_0: Fix port mapping. Port 2 & 3 were swapped. 2025-12-23 14:30:27 +01:00
logicog 2a7bfdc119 Add duplex setting in PHY speed configuration 2025-12-23 13:04:34 +01:00
logicog 367bef2b2f Add defines for duplex modes 2025-12-23 13:04:34 +01:00
logicog cad74017a9 Remove white space in machine.h 2025-12-23 13:04:34 +01:00
logicog 3af63af4a4 Add MTU setting in web-page 2025-12-23 13:04:34 +01:00
logicog b7cfc73752 Add support in simulator for mtus 2025-12-22 23:28:50 +01:00
logicog 51345a07e6 Add mtu support in http server 2025-12-22 23:28:50 +01:00
logicog 67fbad38ce Add mtu command 2025-12-22 23:28:50 +01:00
logicog 67439efd2b Correctly display 9-port machines 2025-12-22 23:28:50 +01:00
logicog b4b8ad5738 Simulate 9-port machines 2025-12-22 23:28:50 +01:00
logicog eb0106d9f4 Correct bits in advertised PHY speeds 2025-12-22 23:28:50 +01:00
logicog f0537d759f Correct PHY registers for speed selection 2025-12-22 23:28:50 +01:00
logicog 36d5ee3ddd Add port speed page 2025-12-22 23:28:50 +01:00
Tobias Diedrich 6441e85752 Add rounding to baud rate calculation 
Without rounding:
- Divisor: 33 = (125000000 / 115200 / 32)
- RCAP2 value: 65503
- Actual baud rate: 118371 = (125000000 / 32 / 33)
- Error: 2.75%

With rounding:
- Divisor: 34 = ((125000000 / 115200 + 16) / 32)
- RCAP2 value: 65502
- Actual baud rate: 114889 = (125000000 / 32 / 34)
- Error: 0.27%

Should fix https://github.com/logicog/RTLPlayground/issues/48
 2025-12-22 23:28:50 +01:00
René van Dorst 053c16b84e SWTG024AS: Document Slave Interface 2025-12-22 14:32:23 +01:00
René van Dorst 4e9fb19e05 SWTG024AS: more small changes 2025-12-20 20:36:41 +01:00
René van Dorst 0a0e1856ae SWTG024AS: Link to photo 2025-12-20 14:50:25 +01:00
René van Dorst cedd81cf00 SWTG024AS: Fix and use unit KiB, add missing managed flag. 2025-12-20 14:44:38 +01:00
René van Dorst bf00f9aa2c Merge pull request #57 from ranma/baudrate-rounding 
Add rounding to baud rate calculation
 2025-12-20 11:55:42 +00:00
Tobias Diedrich f46cb02828 Add rounding to baud rate calculation 
Without rounding:
- Divisor: 33 = (125000000 / 115200 / 32)
- RCAP2 value: 65503
- Actual baud rate: 118371 = (125000000 / 32 / 33)
- Error: 2.75%

With rounding:
- Divisor: 34 = ((125000000 / 115200 + 16) / 32)
- RCAP2 value: 65502
- Actual baud rate: 114889 = (125000000 / 32 / 34)
- Error: 0.27%

Should fix https://github.com/logicog/RTLPlayground/issues/48
 2025-12-20 08:37:28 +01:00
René van Dorst 0779222194 SWTG024AS: Add Sodola SL-SWTG124AS-D 
Info from #55.
 2025-12-19 21:07:11 +01:00
René van Dorst 44ce073869 SWTG024AS: Add port overview, rename SDS to SerDes 2025-12-19 21:03:47 +01:00
logicog c20ec6b081 Merge pull request #53 from sergewar/main 
Add github actions
 2025-12-18 10:17:10 +01:00
sergewar ed62e46790 Add github actions 2025-12-18 10:23:52 +02:00
René van Dorst 12595f806a Merge pull request #50 from logicog/sfp_readings 
Show SFP + DOM info while hovering over the port.
 2025-12-17 06:50:41 +00:00
logicog 58c9af242d Cleanup code in rtl837x_phy.c 2025-12-17 06:44:11 +01:00
logicog dc9bc5ec7d Add SFP data to send_basic_info 2025-12-17 06:44:09 +01:00
logicog 44792699bf Add sfr_mask_data function header 2025-12-17 06:43:31 +01:00
logicog 12db61faf7 Add tooltips 2025-12-17 06:43:28 +01:00
logicog 519c224dd2 Use charset=UTF-8 in http header 
This allows us to use the degree sign for the temperatur
readings of the SFP modules.
 2025-12-16 20:08:47 +01:00
logicog b442417a8a Add tooltips for ports 2025-12-16 20:08:47 +01:00
logicog 87717a0790 Move drawing of ports into main.js 
This reduces the number of .js which are pulled by the browser
when loading a http page, which should reduce the loading time.
Also prepare for device-dependent logical to physical port
mappings.
 2025-12-16 20:08:47 +01:00
logicog 81fdb14213 Fix http_sim.c 2025-12-16 20:08:47 +01:00
logicog 6fd32d290c Printout of dynamic SFP information 2025-12-16 20:06:27 +01:00
logicog 6272d949cd Add readout of SFF-8472 A2h info from SFPs 2025-12-16 20:06:27 +01:00
René van Dorst 9c4d49bc8c Merge pull request #49 from logicog/igmp 
Add basic IGMP support.
 2025-12-15 06:45:20 +00:00
logicog 95fae8bad2 Display actual link speed 2025-12-15 06:54:41 +01:00