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Author SHA1 Message Date
logicog 8302b0d0d2 Update on console 2025-06-10 18:14:37 +02:00
logicog fdec0ad80c Status update 2025-06-10 18:11:29 +02:00
logicog 8243a454de Adding support for link status display 2025-06-10 17:57:28 +02:00
logicog 2ae0b5caba Moving registers to dedicated header so they can be better documented 2025-06-10 17:56:42 +02:00
logicog c54227f057 Fix SFR_DATA access, make internal switch work 2025-06-09 11:22:52 +02:00
logicog c5d7628ea0 Adding support for the ASIC second counter register and sleeping 2025-06-06 20:49:15 +02:00
logicog a0a5328ecd Document default baud of 115200 2025-06-05 20:16:24 +02:00
logicog 9f22c49af7 Make C45 PHY access work, support for suspected C22 access, switch to 115200 baud 2025-06-05 20:15:42 +02:00
logicog 98403e25d3 Add definitions for SFRs 0x93 and 0x94 2025-06-05 20:14:08 +02:00
logicog 7c2e1509a5 Cosmetics 2025-06-05 20:13:07 +02:00
logicog 73a6f0f311 Adding more flash functionality and image documentation 2025-05-14 20:40:44 +02:00
logicog 7493089c39 Adding DIO for flash access 2025-05-11 20:29:31 +02:00
logicog 3a953bba47 More commands, fixing strange sdcc behaviour for clock setting defines 2025-05-11 18:28:08 +02:00
logicog 138ed7dd25 More HW info 2025-05-11 06:36:11 +02:00
logicog 8fedd9c997 More on the image 2025-05-10 17:13:04 +02:00
logicog 4f654d5a0b Nicer README 2025-05-10 17:07:31 +02:00
logicog 6d3214d13d More initial documentation 2025-05-10 17:01:33 +02:00
logicog c4835b7a6c Initial commit 2025-05-10 15:52:02 +02:00
logicog d35eaa8a49 Initial commit 2025-05-10 15:45:00 +02:00