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334 Commits 9 Branches 1 Tag
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Author SHA1 Message Date
logicog 8fee855da2 Separate code for rtl8272 from rtl8373 for readability and stability against accidental changes 2025-07-22 09:42:56 +02:00
logicog 995deb313c Cleanup of unused code 2025-07-22 09:41:44 +02:00
logicog 066edd672e Add off-state for SDS 2025-07-22 09:34:40 +02:00
logicog 6be1124ecf Fixed shift arithmetic bug reported by airjinkela 2025-07-21 21:59:20 +02:00
logicog fa4a80c291 Cleanup of printouts 2025-07-21 11:11:52 +02:00
logicog ccd8bf1633 Cleanup 2025-07-17 23:29:20 +02:00
logicog b6d92b10fa Latest status 2025-07-17 15:17:33 +02:00
logicog b0a41a5af6 Add support for RTL8372-devices with 2 SFP+ ports 2025-07-17 13:25:07 +02:00
logicog ec69299a7b Clarification that flashing can always be done via patch-clamp 2025-07-14 08:06:56 +02:00
logicog a6e933fde6 L2 table access feature added 2025-07-14 08:01:59 +02:00
logicog 9b5cfb0e1b Mirroring and VLAN explained 2025-07-14 08:00:48 +02:00
logicog 84b84f5c32 Cleanup of L2 and mirroring features 2025-07-14 07:59:31 +02:00
logicog 20b5c7b833 Latest update on features 2025-07-14 07:58:55 +02:00
logicog 38cc74d1fa Add documentation for mirroring 2025-07-13 23:34:03 +02:00
logicog ba1b03dd63 More documentation on the L2 table 2025-07-13 23:15:51 +02:00
logicog e3bb76ec1b Initial description of L2 table 2025-07-13 20:48:37 +02:00
logicog 1ae617c38b Initial description of L2 table 2025-07-13 20:48:05 +02:00
logicog d66931acdf Adding initial http daemon implementation 2025-07-13 12:03:40 +02:00
logicog e2716da6c8 Typo fixed 2025-07-13 11:53:23 +02:00
logicog 4edc826c39 Accidentally checked in 2025-07-13 11:52:57 +02:00
logicog 8d4b102e97 More porting to RTL837x architecture of psock 2025-07-12 16:11:51 +02:00
logicog b192a87cab Cleaning up printouts for debugging of uIP 2025-07-11 16:36:16 +02:00
logicog a2af2f9151 Empty application for testing 2025-07-11 15:50:55 +02:00
logicog 37cee7692a Use lc-switch, becasue labels as values is not supported by sdcc 2025-07-11 15:17:38 +02:00
logicog 8b761cfcc8 Add UIP stack. Still lots of debug output on packets... 2025-07-11 14:54:57 +02:00
logicog e486c04186 Add initial port of uip TCP/IP stack 2025-07-11 14:16:08 +02:00
logicog f0701295db Add description of checksum offload bits 2025-07-11 14:14:00 +02:00
logicog f25cc47c5f Adding uip lib support 2025-07-06 09:55:12 +02:00
logicog e0924314b4 Add memcpy function for __xdata 2025-07-06 09:53:28 +02:00
logicog 062c5576de Fixing banked call 2025-07-05 23:46:09 +02:00
logicog 65c2336313 Use external command parser module. Add support for mirroring 2025-07-05 09:24:16 +02:00
logicog 846494dc46 Move parsing to external module 2025-07-05 09:23:20 +02:00
logicog 2d8c0efabd Add 802.1Q VLAN and PVID support. Support VLAN tag at CPU-port 2025-07-04 09:17:10 +02:00
logicog 997d85ba02 Add basic VLAN configuration 2025-07-02 11:57:15 +02:00
logicog 6f90e1db53 Add support for changing Ethernet speeds 2025-06-29 20:06:53 +02:00
logicog b59f51b3ca Cleanup of initialitation, make debug code conditional 2025-06-29 11:10:29 +02:00
logicog 669ebdc616 Access to sfp register reading in common 2025-06-29 11:09:41 +02:00
logicog fd48ae80c1 Feature updates 2025-06-29 11:09:01 +02:00
logicog 4f799f3677 Adding port module 2025-06-29 11:08:37 +02:00
logicog 5a87d81b8c Adding port statistics 2025-06-29 11:07:54 +02:00
logicog 5faf31cdb8 Moving PHY code to BANK1 2025-06-25 15:30:50 +02:00
logicog 73a0a7d137 Add banking support 2025-06-25 13:20:06 +02:00
logicog f543b58490 More on checksum offloading 2025-06-25 13:19:44 +02:00
logicog 797ae23865 Banking support 2025-06-24 06:06:49 +02:00
logicog 178e3d2550 More doc on TX 2025-06-23 19:43:33 +02:00
logicog 08d6c27605 More documentation 2025-06-23 19:41:26 +02:00
logicog b8352f9430 Implement ARP broadcast and make ping work 2025-06-23 17:57:54 +02:00
logicog 2776df9ca8 Make RX of packets work 2025-06-21 16:18:19 +02:00
logicog dd039494c2 Add more RTL8224 config 2025-06-21 05:58:55 +02:00
logicog 869db02865 Emable RTL8224 PHY. Better implementation of sleep/delay timer 2025-06-17 18:21:15 +02:00