Horaco HC-SWTGW218AS units on this PCB keep their factory MAC at
0x1FC000, the offset the other boards in machine/ read it from, so use
it instead of a generated locally administered one. If the flash holds
no valid MAC there, the generated one is still used.
SW1 on PCB-SWTG024AS-A-V2.0.1_19650 is wired to GPIO48. Measured on
HC-SWTG124AS: GPIO48 reads 1 idle and 0 while the button is held.
HC_SWTG124AS.c is a symlink to PCB_SWTG024AS_A_2_0_1.c.
RTL8373 (non-N) with an RTL8224 quad 2.5G PHY, 2 MB GD25Q16ESIG flash, no PoE.
The wiring is close to the KP-9000-9XHML-X V3.1 (same 8+1 topology, same I2C on
GPIO39/40), but three things differ and were determined on hardware:
- ModAbs is GPIO30 (low with a module inserted, high with an empty cage) and LOS
is GPIO37 (high without light), not GPIO38. GPIO38, the ModAbs pin of the
KP-9000 reference, is tied low on this board, which made the firmware believe a
module was permanently inserted and retry the I2C read forever.
- The reset button is GPIO54, not GPIO48. GPIO48 never changes here, so the
button appeared to do nothing.
- The LED wiring follows the stock port order (pin 3n+m belongs to port n+1,
LED function m), so the mux table is the chip default except that pin 25 --
the SFP LED -- is driven by function 0, the only populated function in SET1.
Per copper port the left LED shows link/activity and the right LED shows
2.5G, matching the front panel labels.
Verified on hardware: all eight 2.5G ports at 10/100/1000/2500 Mbps, 1G and 10G
SFP modules including DDM data, both LED columns, module insert/remove and the
reset button.
The hongyavision HYWS-SGT0204S is sold as an unmanaged 4x2.5G + 2x10G SFP+
switch and carries the 2G5F4_10G2_V1.01 marking on the PCB. It is a sibling of
the KP-9000-6XH-X2 (2M-PCB43-V1.1), so machine/2G5F4_10G2_V1_01.c is that board
definition with these changes:
- The two SFP+ cages (physical ports 5 and 6) are wired the other way round:
physical 5 is on SDS1 with GPIO30/GPIO37, physical 6 on SDS0 with
GPIO50/GPIO10. Copper ports 1-4 match the KP-9000 layout.
- No reset button is fitted and the case has no opening for one, so reset_pin
is GPIO_NA. GPIO54, the reset pin on the KP-9000 layout, reads as permanently
pressed here.
- The board definition sets flash_sio, so the flash is read with single-IO: the
fitted 512 KB Bright Moon T25S40 cannot be read in DIO mode on this board, an
image that leaves DIO enabled does not come up at all, while the same image
with single-IO boots and runs normally (two units).
- The board is added to the machine_custom_init() group that sets
LED_GLB_IO_EN bit 6, otherwise the RTL837x "solid" conditions (LINK/speed)
never drive the LEDs and the 2.5G LED glows faintly at 100M/1000M.
flash_sio is a new field of struct machine that rtlplayground.c hands to
flash_init(); only this board sets it, every other machine keeps DIO. It costs
management-plane speed only, the ASIC keeps forwarding in hardware.
The stock firmware runs a factory test console on the serial header at 9600
baud, whose silkscreen labels are shifted by one pin.
Verified: warning-free build, `make machine_check` passes for every target, the
host tests pass, and a control build of this target without the LED hook differs
from the KP-9000-6XH_X2_V1_1 image in 44 bytes: all inside the machine
description (including flash_sio) and the image CRC16, nothing else in the
firmware moved. On the board the single-IO image boots and runs on two units;
port order, SFP cages and LED behaviour come from the machine definition
verified on this board earlier.
UART is broken out to the unpopulated switch header at the front of the
board.
This isn't quite the same as the V2.0 definition as the system led is
always on, not routed through the CPU.
Additionally, document that the newer revision of the same "YS25-0402"
is supported via the existing PCB-K0402WS-V3.0 target.
João Silva
René van Dorst
feelfree69
logicog
Zoe O'Connell
Mariappan Ramasamy
rwalli@gmx.at
HL Yi
gtytup
avicarmeli
logicog
Kamikaze94
Matt Merhar