From c5995a418423cc151eb418f492709ef62fa3c249 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Sun, 31 Aug 2025 22:59:09 +0200 Subject: [PATCH 1/3] Add: phy_modify() to modify phy_registers. Makes it easier to modify set/clear bit in a phy register. Simulair like Linux PHY-core: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/phy-core.c#n551 --- rtl837x_common.h | 1 + rtlplayground.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/rtl837x_common.h b/rtl837x_common.h index a84ed6a..46f480d 100644 --- a/rtl837x_common.h +++ b/rtl837x_common.h @@ -63,6 +63,7 @@ void print_phy_data(void); void phy_write_mask(uint16_t phy_mask, uint8_t dev_id, uint16_t reg, uint16_t v); void phy_write(uint8_t phy_id, uint8_t dev_id, uint16_t reg, uint16_t v); void phy_read(uint8_t phy_id, uint8_t dev_id, uint16_t reg); +void phy_modify(uint8_t phy_id, uint8_t dev_id, uint16_t reg, uint16_t mask, uint16_t set); void reg_read(uint16_t reg_addr); void reg_read_m(uint16_t reg_addr); void reg_write(uint16_t reg_addr); diff --git a/rtlplayground.c b/rtlplayground.c index 1ec02d8..c140362 100644 --- a/rtlplayground.c +++ b/rtlplayground.c @@ -1133,6 +1133,41 @@ void phy_read(uint8_t phy_id, uint8_t dev_id, uint16_t reg) #endif } +/* + * Modify a register reg of phy phy_id, in page page + * Set: bit mask of bits to set. + * Mask: bit mask of bits to clear. + + * Note: We assume that the registers `SFR_SMI_REG_U16`, `SFR_SMI_PHY` and `SFR_SMI_DEV` + * keep there value, and dont have to be rewritten everytime. + */ +void phy_modify(uint8_t phy_id, uint8_t dev_id, uint16_t reg, uint16_t mask, uint16_t set) +{ + uint8_t smi_phy = dev_id << 3 | 2; + + // Read the data + SFR_SMI_REG_U16 = reg; // c2, c2 + SFR_SMI_PHY = phy_id; // a5 + SFR_SMI_DEV = smi_phy; // c4 + SFR_EXEC_GO = SFR_EXEC_READ_SMI; + do { + } while (SFR_EXEC_STATUS != 0); + + // Modify the reed data. + // TODO: Check if we directly can modify SFR register directly. + uint16_t data = SFR_DATA_U16 & ~(mask); + data |= ~(set); + + uint16_t phy_mask = bit_mask[phy_id]; + + // Write it back + SFR_SMI_REG_U16 = data; + SFR_SMI_PHYMASK = phy_mask; // SFR_C5 + SFR_SMI_DEV = smi_phy | (phy_mask >> 8); + SFR_EXEC_GO = SFR_EXEC_WRITE_SMI; + do { + } while (SFR_EXEC_STATUS != 0); +} void nic_setup(void) { From 001c52ef39e9bf5ead99e015d6ff7fa60b7bde3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Tue, 2 Sep 2025 10:59:52 +0200 Subject: [PATCH 2/3] Use phy_modify(). This saves 210 bytes. --- rtl837x_phy.c | 44 +++++++++++--------------------------------- 1 file changed, 11 insertions(+), 33 deletions(-) diff --git a/rtl837x_phy.c b/rtl837x_phy.c index dc62bb0..7cf76e2 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -99,36 +99,26 @@ void phy_config(uint8_t phy) __banked delay(20); // PHY configuration: External 8221B? // p081e.75f3:ffff P000100.1e0075f3:fffe - phy_read(phy, 0x1e, 0x75f3); - pval = SFR_DATA_U16 & 0xfffe; - phy_write(phy, 0x1e, 0x75f3, pval); + phy_modify(phy, 0x1e, 0x75f3, 0x0001, 0x0000); delay(20); // p081e.697a:ffff P000100.1e00697a:ffc1 / p031e.697a:0003 P000008.1e00697a:0001 // SERDES OPTION 1 Register (MMD 30.0x6) bits 0-5: 0x01: Set HiSGMII+SGMII - phy_read(phy, 0x1e, 0x697a); - pval = SFR_DATA_U16 & 0xffc0 | 0x0001; - phy_write(phy, 0x1e, 0x697a, pval); + phy_modify(phy, 0x1e, 0x697a, 0x003f, 0x0001); delay(20); // p031f.a432:0811 P000008.1f00a432:0831 // PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE - phy_read(phy, 0x1f, 0xa432); - pval = SFR_DATA_U16 | 0x0020; - phy_write(phy, 0x1f, 0xa432, pval); + phy_modify(phy, 0x1f, 0xa432, 0x0000, 0x0020); // p0307.003e:0000 P000008.0700003e:0001 // EEE avertisment 2 register MMMD 7.0x003e, set bit 0: 2.5G has EEE capability - phy_read(phy, 0x7, 0x3e); - pval = SFR_DATA_U16 | 0x0001; - phy_write(phy, 0x7, 0x3e, pval); + phy_modify(phy, 0x7, 0x3e, 0x0000, 0x0001); delay(20); // p031f.a442:043c P000008.1f00a442:0430 // Unknown, but clear bits 2/3 - phy_read(phy, 0x1f, 0xa442); - pval = SFR_DATA_U16 & 0xfff3; - phy_write(phy, 0x1f, 0xa442, pval); + phy_modify(phy, 0x1f, 0xa442, 0x0006, 0x0000); delay(20); // P000100.1e0075b5:e084 @@ -137,30 +127,22 @@ void phy_config(uint8_t phy) __banked // p031e.75b2:0000 P000008.1e0075b2:0060 // set bits 5/6 - phy_read(phy, 0x1e, 0x75b2); - pval = SFR_DATA_U16 | 0x0060; - phy_write(phy, 0x1e, 0x75b2, pval); + phy_modify(phy, 0x1e, 0x75b2, 0x0000, 0x0060); delay(20); // p081f.d040:ffff P000100.1f00d040:feff // LCR6 (LED Control Register 6, MMD 31.D040), set bits 8/9 to 0b10 - phy_read(phy, 0x1e, 0xd040); - pval = SFR_DATA_U16 & 0xfcff | 0x0200; - phy_write(phy, 0x1e, 0xd040, pval); + phy_modify(phy, 0x1e, 0xd040, 0x0300, 0x0200); delay(20); // p081f.a400:ffff P000100.1f00a400:ffff, then: p081f.a400:ffff P000100.1f00a400:bfff // p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040 // FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400) // Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved - phy_read(phy, 0x1f, 0xa400); - pval = SFR_DATA_U16 | 0x4000; - phy_write(phy, 0x1f, 0xa400, pval); + phy_modify(phy, 0x1f, 0xa400, 0x0000, 0x4000); delay(20); - phy_read(phy, 0x1f, 0xa400); - pval = SFR_DATA_U16 & 0xbfff; - phy_write(phy, 0x1f, 0xa400, pval); + phy_modify(phy, 0x1f, 0xa400, 0x4000, 0x0000); delay(20); print_string("\r\n phy config done\r\n"); @@ -230,16 +212,12 @@ void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t dup // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) phy_write(port, 0x07, 0x20, 0x6001); // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) - phy_read(port, 0x1f, 0xa412); - v = SFR_DATA_U16; - phy_write(port, 0x1f, 0xa412, v | 0x0200); + phy_modify(port, 0x1f, 0xa412, 0x0000, 0x02000); } else if (speed == PHY_SPEED_2G5) { // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) phy_write(port, 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) - phy_read(port, 0x1f, 0xa412); - v = SFR_DATA_U16; - phy_write(port, 0x1f, 0xa412, v & 0xfdff); + phy_modify(port, 0x1f, 0xa412, 0x02000, 0x0000); } phy_write(port, 0x07, 0x00, 0x3200); // Enable AN } From 71eba81421c0322cb82e5c8d84dae93f583d837f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Tue, 2 Sep 2025 22:25:07 +0200 Subject: [PATCH 3/3] Add rtlplaygroud.mem also exclude the file in .gitignore. See PR #10 about mem usage --- .gitignore | 1 + rtlplayground.mem | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 rtlplayground.mem diff --git a/.gitignore b/.gitignore index 0b0321f..07d0aed 100644 --- a/.gitignore +++ b/.gitignore @@ -9,6 +9,7 @@ *.ihex *.lst *.mem +!rtlplayground.mem *.lk html_data.c html_data.h diff --git a/rtlplayground.mem b/rtlplayground.mem new file mode 100644 index 0000000..5b1efa1 --- /dev/null +++ b/rtlplayground.mem @@ -0,0 +1,29 @@ +Internal RAM layout: + 0 1 2 3 4 5 6 7 8 9 A B C D E F +0x00:|0|0|0|0|0|0|0|0|a|a|a|a|a|a|a|a| +0x10:|c|c|c|d|d|d|d|d|d|d| | | | | | | +0x20:|B|T|b|b|b|b|b|b|b|b|b|b|b|b|b|b| +0x30:|b|b|b|b|e|e|e|e|e|e|e|e|f|f|f|f| +0x40:|f|f|f|f|f|g|g|g|g|g|g|g|g|g|g|g| +0x50:|g|h|h|h|h|h|h|h|h|h|h|h|h|i|i|i| +0x60:|i|i|i|i|i|i|i|j|j|j|j|j|j|j|j|j| +0x70:|j|j|j|j|j|Q|Q|Q|Q|Q|Q|Q|S|S|S|S| +0x80:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0x90:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xa0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xb0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xc0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xd0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xe0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0xf0:|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S|S| +0-3:Reg Banks, T:Bit regs, a-z:Data, B:Bits, Q:Overlay, I:iData, S:Stack, A:Absolute + +16 bit mode initial stack starts at: 0x7c (sp set to 0x7b) with 132 bytes available. +The largest spare internal RAM space starts at 0x1a with 6 bytes available. + +Other memory: + Name Start End Size Max + ---------------- -------- -------- -------- -------- + PAGED EXT. RAM 0 256 + EXTERNAL RAM 0x0001 0x1ad8 6872 16777216 + ROM/EPROM/FLASH 0x0000 0x1c195 45278 16777216